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ultra low power 128k , lcd mcu family si102x/3x rev. 0.3 11/11 copyright ? 2011 by silicon laboratories si102x/3x this information applies to a product under development. its characteristics and specifications are subject to change without n otice. ultra low power at 3.6v - 110 a/mhz ibat; dc-dc enabled - 110 na sleep current with data retention; por monitor enabled - 400 na sleep current with smartclock (internal lfo) - 700 na sleep current with smartclock (external xtal) - 2 s wake-up from any sleep mode 12-bit; 16 ch. analog-to-digital converter - up to 75 ksps 12-bit mode or 300 ksps 10-bit mode - external pin or internal vref (no external capacitor required) - on-chip pga allows measuring voltages up to twice the reference voltage - autonomous burst mode with 16-bit automatic averaging accumu - lator - integrated temperature sensor two low current comparators - programmable hysteresis and response time - configurable as interrupt or reset source internal 6-bit current reference - up to 500 a; source and sink capability - enhanced resolution via pwm interpolation integrated lcd controller (si102x only) - supports up to 128 segments (32x4) - integrated charge pump for contrast control metering-specific peripherals - dc-dc buck converter allows dynamic voltage scaling for ? maximum efficiency (250 mw output) - sleep-mode pulse accumulator with programmable switch ? de-bounce and pull-up control interfaces directly to metering sen - sor - dedicated packet processing engine (dppe) includes hardware aes, dma, crc, and encoding blocks for acceleration of wireless protocols - manchester and 3 out of 6 encoder hardware for power efficient implementation of the wireless m-bus specification ezradiopro ? transceiver - frequency range = 240?960 mhz - sensitivity = ?121 dbm - fsk, gfsk, and ook modulation - max output power = +20 dbm or +13 dbm - rf power consumption 18.5 ma receive 18 ma @ +1 dbm transmit 30 ma @ +13 dbm transmit 85 ma @ +20 dbm transmit data rate = 0.123 to 256 kbps auto-frequency calibration (afc) antenna diversity and transmit/receive switch control programmable packet handler tx and rx 64-byte fifos frequency hoppi ng c apability on -chip crystal tuning high-speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks memory - up to 128 kb flash; in-system programmable; full read/ write/erase functionality over the entire supply range - up to 8 kb internal data ram digital peripherals - 53 port i/o; all 5 v tolerant with high sink ? current and programmable drive strength - hardware smbus? (i2c? compatible), 2 x spi?, and uart serial ports available concurrently - four general-purpose 16-bit counter/timers - programmable 16-bit counter/timer array with six capture/compare modules and watchdog timer clock sources - precision internal oscillators: 24.5 mhz with 2% accuracy sup - ports uart operation; spread-spectrum mode for reduced emi - low power internal oscillator: 20 mhz - external oscillator: crystal, rc, c, cmos clock - smartclock oscillator: 32.768 khz crystal or 16.4 khz internal lfo with thr ee independent alarms on-chip debug - on-chip debug circuitry facilitates full-speed, non-intrusive, in-sys - tem debug (no emulator required) - provides 4 breakpoints, single stepping packages - ?85 pin lga (6 x 8 mm) port 0-1 drivers digital peripherals uart timers 0/1/2/3 pca/ wdt smbus priority crossbar decoder p0.0...p1.7 p2.4...p2.7 p3.0...p6.7 crossbar control port i/o configuration cip-51 8051 controller core 128/64/32/16 kbyte isp flash program memory 256 byte sram sfr bus 8192/4096 byte xram spi 0 analog peripherals comparators + - vbat vbat vdc xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset/pmu reset c2d c2ck/rst wake 12-bit 75ksps adc a m u x temp sensor external vref internal vref vdd xtal2 low power 20 mhz oscillator vref gnd cp0, cp0a + - cp1, cp1a enhanced smartclock oscillator xtal3 xtal4 dc/dc buck converter ind gnddc vreg digital power crc engine lcd charge pump aes engine dma cap p7.0/c2d 32 encoder gnd vdd analog power port 2 drivers port 3-6 drivers port 7 driver 4 16 rf xcvr (240-960 mhz, +20/+13 dbm) 30 mhz pa lna agc digital modem delta sigma modulator digital logic mixer pga adc tx rxp rxn xout xin lcd (4x32) emif pulse counter ezradiopro spi 1 vco vbatdc gpiox nirq sdn 3
si102x/3x 2 rev. 0.3
rev. 0.3 3 si102x/3x table of contents 1. system overview ........ .................................................................................. ........... 26 1.1. typical connection di agram ................. ................................................. ........... 29 1.2. cip-51? microcontroller core ............................................................... ........... 30 1.2.1. fully 8051 compatible ...... ............................................................. ........... 30 1.2.2. improved throughput ................. .................................................. ............. 30 1.2.3. additional features ...... .................................................................. ........... 30 1.3. port input/output .... ................................................................................ ........... 31 1.4. serial ports ......... .................................................................................. ............. 32 1.5. programmable counter array... ............... ............................................... ........... 32 1.6. sar adc with 16-bit au to-averaging a ccumulator and ? autonomous low power burst m ode............... .............. ............... ........... ......... 33 1.7. programmable current reference (iref0).................. ............................ ......... 34 1.8. comparators........... ................................................................................ ........... 34 2. ordering information ....... ............................................................................. ........... 36 3. pinout and package definitions ..... ............................................................. ........... 37 3.1. lga-85 package specif ications ......... .................................................. ............. 46 3.1.1. package drawing .............. ............................................................. ........... 46 3.1.2. land pattern.......... ......................................................................... ........... 48 3.1.3. soldering guidelines ....... ............................................................... ........... 49 4. electrical characteristics ......... .................................................................. ............. 50 4.1. absolute maximum specificat ions................ .......................................... ........... 50 4.2. mcu electrical characteristic s .................. ............................................. ........... 51 4.3. ezradiopro ? peripheral electrical characteristic s..................... ........... ......... 70 4.4. definition of test condi tions for the ezradiopro peri pheral ............. ............. 77 5. sar adc with 16-bit auto -averaging accumulator and ? autonomous low power burst mode ........................................................ ........... 78 5.1. output code formatting ....... .................................................................. ........... 78 5.2. modes of operation ... ............................................................................. ........... 80 5.2.1. starting a conversion...... ............................................................... ........... 80 5.2.2. tracking modes............... ............................................................... ........... 80 5.2.3. burst mode................... .................................................................. ........... 82 5.2.4. settling time requirement s........................................................... ........... 83 5.2.5. gain setting ...... ............................................................................. ........... 83 5.3. 8-bit mode ....... ....................................................................................... ........... 84 5.4. 12-bit mode ............ ................................................................................ ........... 84 5.5. low power mode....... ............................................................................. ........... 85 5.6. programmable window detector ............... ............................................. ........... 91 5.6.1. window detector in si ngle-ended mode ........ ............................... ........... 93 5.6.2. adc0 specifications ....... ............................................................... ........... 94 5.7. adc0 analog multiplexer ..... .................................................................. ........... 95 5.8. temperature sensor.. ............................................................................. ........... 97 5.8.1. calibration ......... ............................................................................. ........... 97 5.9. voltage and ground referenc e options ............... ................................. ......... 100
si102x/3x 4 rev. 0.3 5.10. external voltage reference .................................................................. ......... 101 5.11. internal voltage reference.... ............................................................... ......... 101 5.12. analog ground reference....... ............................................................. ......... 101 5.13. temperature sensor enable ... ............................................................. ......... 101 5.14. voltage reference electrical specifications ................. ............... .................. 102 6. comparators.............. .................................................................................. ........... 103 6.1. comparator inputs..... ............................................................................. ......... 103 6.2. comparator outputs ........... .................................................................. ........... 104 6.3. comparator response time ..... ............................................................. ......... 105 6.4. comparator hyst erisis ............. ............................................................... ......... 105 6.5. comparator register descriptions ............... .......................................... ......... 106 7. programmable current referen ce (iref0).............. ................................. ........... 110 7.1. pwm enhanced mode............. ............................................................... ......... 110 7.2. iref0 specifications .......... .................................................................. ........... 111 7.3. comparator0 and comparator1 analog multip lexers ................. ..................... 112 8. cip-51 microcontroller.............. .................................................................. ........... 115 8.1. instruction set......... ................................................................................ ......... 116 8.1.1. instruction and cpu timing ....... ................. ................................. ........... 116 8.2. cip-51 register descr iptions ................ ................................................. ......... 121 9. memory organization ... ................................................................................ ......... 124 9.1. program memory....... ............................................................................. ......... 124 9.1.1. movx instruction and prog ram memory ........... ............................ ......... 127 9.2. data memory .......... ................................................................................ ......... 127 9.2.1. internal ram ..... ............................................................................. ......... 128 9.2.2. external ram ...... ........................................................................... ......... 128 10. external data memory interface and on-c hip xram ......... ............ .................. 130 10.1. accessing xram......... ......................................................................... ......... 130 10.1.1. 16-bit movx example ..... ............... ............................................. ......... 130 10.1.2. 8-bit movx exam ple ............... .................................................. ........... 130 10.2. configuring the external me mory interface ....... ................................. ........... 131 10.3. port configuration.... ............................................................................. ......... 131 10.4. multiplexed a nd non-multiplexed selection........... ............................... ......... 135 10.4.1. multiplexed confi guration............................................................. ......... 135 10.4.2. non-multiplexed configuration............. ................................................. 135 10.5. memory mode selection........ ............................................................... ......... 136 10.5.1. internal xram only ...... ............................................................... ......... 137 10.5.2. split mode without bank se lect............................ ............... .................. 137 10.5.3. split mode with bank sele ct............... .......................................... ......... 137 10.5.4. external only..... ........................................................................... ......... 137 10.6. timing .......... ....................................................................................... ......... 138 10.6.1. non-multiplexed mode ................ ................................................. ......... 140 10.6.2. multiplexed mode ... ...................................................................... ......... 143 11. direct memory access (dma0)..... ............................................................. ......... 147 11.1. dma0 architecture ............. .................................................................. ......... 148 11.2. dma0 arbitration ..... ............................................................................. ......... 149
rev. 0.3 5 si102x/3x 11.2.1. dma0 memory access arbi tration ......... .............. ............... .................. 149 11.2.2. dma0 channel arbitration ........................................................... ......... 149 11.3. dma0 operation in low po wer modes ............... ................................. ......... 149 11.4. transfer configuration........ .................................................................. ......... 150 12. cyclic redundancy check unit (crc0).......... .......................................... ......... 161 12.1. 16-bit crc algorit hm............... ............................................................. ......... 161 12.3. preparing for a crc calculatio n ................ .......................................... ......... 164 12.4. performing a crc calculation . ............... ............................................. ......... 164 12.5. accessing the crc0 result .... ............................................................. ......... 164 12.6. crc0 bit reverse feature.... ............................................................... ......... 168 13. dma-enabled cyclic redund ancy check module (crc1)...... ................ ......... 169 13.1. polynomial specification..... .................................................................. ......... 169 13.2. endianness.............. ............................................................................. ......... 170 13.3. crc seed value ....... ........................................................................... ......... 171 13.4. inverting the final value..... .................................................................. ......... 171 13.5. flipping the fina l value ....................... ................................................. ......... 171 13.6. using crc1 wi th sfr access .............. ............................................... ......... 172 13.7. using the crc1 m odule with the dma . ....... ................................................. 172 14. advanced encryption standard (aes) peripheral .............. ............ .................. 176 14.1. hardware description ......... .................................................................. ......... 177 14.1.1. aes encryption/decrypti on core ................ ................................. ......... 178 14.1.2. data sfrs.... ................................................................................ ......... 178 14.1.3. configuration sfrs ......................................................................... ......... 179 14.1.4. input multiplexer. ............... ........................................................... ......... 179 14.1.5. output multiplexer ...... .................................................................. ......... 179 14.1.6. internal state machine ... ............... ............................................... ......... 179 14.2. key inversion........... ............................................................................. ......... 180 14.2.1. key inversion using dma. ............... ............................................. ......... 181 14.2.2. key inversion using sfrs ............... ............................................. ......... 182 14.2.3. extended key output byte order........... .............. ............... .................. 183 14.2.4. using the dma to unwr ap the extended key ............ ................. ........... 184 14.3. aes block cipher ...... ........................................................................... ......... 185 14.4. aes block cipher data flow........ ........................................................ ......... 186 14.4.1. aes block cipher encryption using dma . ................................. ........... 187 14.4.2. aes block cipher encryption using sfrs ................................. ........... 188 14.5. aes block cipher decryption .. ............................................................. ......... 189 14.5.1. aes block cipher decryp tion using dma................. ................. ........... 189 14.5.2. aes block cipher decryption using sfrs ................................. ........... 190 14.6. block cipher modes .... ......................................................................... ......... 191 14.6.1. cipher block chai ning mode.................. .............. ............... .................. 191 14.6.2. cbc encryption initialization vector lo cation........... ................. ........... 193 14.6.3. cbc encryption using dm a .................................................................. 193 14.6.4. cbc decryption ..... ...................................................................... ......... 196 14.6.5. counter mode ..... ......................................................................... ......... 199 14.6.6. ctr encryption using dma . ........................................................ ......... 201
si102x/3x 6 rev. 0.3 15. encoder/decoder ........... ............................................................................. ......... 208 15.1. manchester encoding............ ............................................................... ......... 209 15.2. manchester decoding............ ............................................................... ......... 210 15.3. three-out-of-six encoding............. ............................................................... 211 15.4. three-out-of-six decoding .... ............................................................... ......... 212 15.5. encoding/decoding with sfr access ................. ................................. ......... 213 15.6. decoder error interrupt....... .................................................................. ......... 213 15.7. using the enc0 m odule with the dma....... .......................................... ......... 214 16. special function registers...... .................................................................. ......... 217 16.1. sfr paging ............. ............................................................................. ......... 217 16.2. interrupts and sfr paging ...... ............................................................. ......... 217 16.3. sfr page stack exampl e ................ .................................................. ........... 219 17. interrupt handler......... ................................................................................ ......... 238 17.1. enabling interrupt s ources ................................................................... ......... 238 17.2. mcu interrupt sour ces and vectors........... .......................................... ......... 238 17.3. interrupt priorities . ................................................................................ ......... 239 17.4. interrupt latency...... ............................................................................. ......... 239 17.5. interrupt register descripti ons .............. ................ ............................... ......... 241 17.6. external interrupts int0 and int1 ........................................................ ......... 248 18. flash memory.............. ................................................................................ ......... 250 18.1. programming the fl ash memory ................ .......................................... ......... 250 18.1.1. flash lock and key functi ons ............... .............. ............... .................. 250 18.1.2. flash erase procedure ..... ........................................................... ......... 250 18.1.3. flash write procedure ..... ............... ............................................. ......... 251 18.1.4. flash write optimization .. ............... ............................................. ......... 252 18.2. non-volatile data storage .. .................................................................. ......... 253 18.3. security options ...... ............................................................................. ......... 253 18.4. determining the device part number at run ti me .............. ................ ......... 255 18.5. flash write and erase guidel ines .............. .......................................... ......... 256 18.5.1. vdd maintenance and t he vdd monitor ...... ............................... ......... 256 18.5.2. pswe maintenance ............. ........................................................ ......... 258 18.5.3. system clock ...... ......................................................................... ......... 258 18.6. minimizing flash read current .................. .......................................... ......... 259 19. power management ....... ............................................................................. ......... 264 19.1. normal mode ........... ............................................................................. ......... 265 19.2. idle mode....... ....................................................................................... ......... 265 19.3. stop m ode ............... ............................................................................. ......... 266 19.4. low power idle mode ......... .................................................................. ......... 266 19.5. suspend mode .......... ........................................................................... ......... 270 19.6. sleep mode ............. ............................................................................. ......... 270 19.7. configuring wakeup s ources.............. ................................................. ......... 271 19.8. determining the event that caused the last wakeup....... ................. ........... 271 19.9. power management spec ifications ................ .............. ............... .................. 275 20. on-chip dc-dc buck converter (dc0)............. ................................................. 276 20.1. startup behavior...... ............................................................................. ......... 277
rev. 0.3 7 si102x/3x 20.4. optimizing board layout ......... ............................................................. ......... 278 20.5. selecting the optimu m switch size..... ................................................. ......... 278 20.6. dc-dc converter clocking opti ons .............. ................................. ........... 278 20.7. bypass mode........... ............................................................................. ......... 279 20.8. dc-dc converter r egister descriptions ...... ................................................. 279 20.9. dc-dc converter spec ifications ......... ................................................. ......... 283 21. voltage regulator (vreg0)...... .................................................................. ......... 284 21.1. voltage regulator electrical specifications ....... ................................. ........... 284 22. reset sources ........... .................................................................................. ......... 285 22.1. power-on reset ...... ............................................................................. ......... 286 22.2. power-fail reset ..... ............................................................................. ......... 287 22.3. external reset ................ ...................................................................... ......... 290 22.4. missing clock detector reset . ............................................................. ......... 290 22.5. comparator0 reset ............ .................................................................. ......... 290 22.6. pca watchdog timer reset ..... ........................................................... ......... 290 22.7. flash error reset .... ............................................................................. ......... 291 22.8. smartclock (real time clock) reset . .............. ................................. ......... 291 22.9. software reset ........ ............................................................................. ......... 291 23. clocking sources.... .................................................................................. ........... 293 23.1. programmable precis ion internal oscillator ............. ............................ ......... 294 23.2. low power internal oscillat or.............. ................................................. ......... 294 23.3. external oscillator drive circuit........ .................................................. ........... 294 23.3.1. external crystal mode.................................................................. ......... 294 23.3.2. external rc mode ........................................................................ ......... 296 23.3.3. external capacitor mode.. ............... ............................................. ......... 297 23.3.4. external cmos clock m ode ................ ................................................. 297 23.4. special function r egisters for selecting and ? configuring the system clock ... ........................................................... ......... 298 24. smartclock (real time clock).. ............................................................... ......... 302 24.1. smartclock interface .......... ............................................................... ......... 303 24.1.1. smartclock lock and key functions............. ............................ ......... 304 24.1.2. using rtc0adr and rt c0dat to access smartclock ? internal registers ............. ........................................................... ......... 304 24.1.3. smartclock interface autoread feature . ................................. ........... 304 24.1.4. rtc0adr autoincrement feature.............. ................................. ......... 304 24.2. smartclock clocking sources ........................................................... ......... 307 24.2.1. using the smartclock o scillator with a crystal or ? external cmos clock .......... ........................................................ ......... 307 24.2.2. using the smartclock o scillator in self-oscillate mode.......... ........... 308 24.2.3. using the low frequency o scillator (lfo) ...... ............................ ......... 308 24.2.4. programmable load capacitance............. ................................. ........... 308 24.2.5. automatic gain contro l (crystal mode only) and ? smartclock bias doubling .... .................................................. ........... 309 24.2.6. missing smartclock dete ctor .............. .............. ............... .................. 311 24.2.7. smartclock oscillator crystal valid detector ......... ................. ........... 311
si102x/3x 8 rev. 0.3 24.3. smartclock timer and alarm function ........ .............. ............... .................. 311 24.3.1. setting and reading the smartclock ti mer value ............. ................ 311 24.3.2. setting a smartclock al arm .............. ................................................. 312 24.3.3. software considerations for using the ? smartclock timer and alarm ... ................................................. ......... 312 25. low-power pulse counter ....... .................................................................. ......... 319 25.1. counting modes ........ ........................................................................... ......... 320 25.2. reed switch types.. ............................................................................. ......... 321 25.3. programmable pull-up resistors ........ ................................................. ......... 322 25.4. automatic pull-up re sistor calibration ...... .......................................... ......... 324 25.5. sample rate............ ............................................................................. ......... 324 25.6. debounce ................ ............................................................................. ......... 324 25.7. reset behavior ........ ............................................................................. ......... 325 25.8. wake up and interrupt sour ces............................................................ ......... 325 25.9. real-time register access ... ............................................................... ......... 326 25.10. advanced features ............. ............................................................... ......... 326 25.10.1. quadrature error ......... ............................................................... ......... 326 25.10.2. flutter detection.......... ............................................................... ......... 327 26. lcd segment driver (s i102x only) .......... ................ ................................. ......... 341 26.1. configuring the lc d segment driver ......... .......................................... ......... 341 26.2. mapping data registers to lcd pins......... .......................................... ......... 342 26.3. lcd contrast adjustment... .................................................................. ......... 345 26.3.1. contrast control mode 1 (bypass mode)...... ............................... ......... 345 26.3.2. contrast control m ode 2 (minimum contra st mode) ............ ................ 346 26.3.3. contrast control mode 3 (constant contrast mode). ................. ........... 346 26.3.4. contrast control m ode 4 (auto-bypass mode) ......... ................. ........... 347 26.4. adjusting the vbat monito r threshold ............. ................................. ........... 351 26.5. setting the lcd refresh rate .. ............... ............................................. ......... 352 26.6. blinking lcd s egments........................................................................ ......... 353 26.7. advanced lcd optimizations... ............... ............................................. ......... 355 27. port input/output ...... .................................................................................. ......... 358 27.1. port i/o modes of operation. ................... ............................................. ......... 359 27.1.1. port pins configured fo r analog i/o.......... ................................. ........... 359 27.1.2. port pins configured fo r digital i/o.......... ................................. ........... 359 27.1.3. interfacing port i/o to high voltage logic... ................................. ......... 360 27.1.4. increasing port i/o drive strength ....... ................................................. 360 27.2. assigning port i/ o pins to analog and digital functi ons................. .............. 360 27.2.1. assigning port i/o pins to analog f unctions ............ ................. ........... 360 27.2.2. assigning port i/o pins to digital f unctions............ ............ .................. 361 27.2.3. assigning port i/o pins to external digital event capture functions ... 361 27.3. priority crossbar decoder .. .................................................................. ......... 362 27.4. port match ............ ................................................................................ ......... 368 27.5. special function regist ers for accessing an d configuring port i/o ............. 370 28. smbus................. ......................................................................................... ......... 388 28.1. supporting document s ......................................................................... ......... 389
rev. 0.3 9 si102x/3x 28.2. smbus configuration.......... .................................................................. ......... 389 28.3. smbus operation ...... ........................................................................... ......... 389 28.3.1. transmitter vs. receiver.. ............... ............................................. ......... 390 28.3.2. arbitration........ ............................................................................. ......... 390 28.3.3. clock low extensio n................ .................................................. ........... 390 28.3.4. scl low timeout... ...................................................................... ......... 390 28.3.5. scl high (smbus free) timeout ............... ................................. ......... 391 28.4. using the smbus..... ............................................................................. ......... 391 28.4.1. smbus configuration regi ster............. ................................................. 391 28.4.2. smb0cn control register ........................................................... ......... 395 28.4.3. hardware slave addre ss recognition ........ ................................. ......... 397 28.4.4. data register .... ........................................................................... ......... 400 28.5. smbus transfer modes......... ............................................................... ......... 400 28.5.1. write sequence (master) .. ........................................................... ......... 400 28.5.2. read sequence (master) ..... ........................................................ ......... 401 28.5.3. write sequence (slave) ... ............... ............................................. ......... 402 28.5.4. read sequence (slave) .... ........................................................... ......... 403 28.6. smbus status decodi ng................... ................. ................................. ........... 404 29. uart0 ................. ......................................................................................... ......... 409 29.1. enhanced baud rate generati on............ ............................................. ......... 410 29.2. operational modes ............. .................................................................. ......... 411 29.2.1. 8-bit uart ........ ........................................................................... ......... 411 29.2.2. 9-bit uart ........ ........................................................................... ......... 411 29.3. multiprocessor communication s ................ .......................................... ......... 412 30. enhanced serial peripheral in terface (spi0) ......... ................................. ........... 418 30.1. signal descriptions.. ............................................................................. ......... 419 30.1.1. master out, slave in (m osi).............. .......................................... ......... 419 30.1.2. master in, slave out (m iso).............. .......................................... ......... 419 30.1.3. serial clock (sck ) ................................................................................ 419 30.1.4. slave select (nss) ....... ............................................................... ......... 419 30.2. spi0 master mode op eration .............. ................................................. ......... 419 30.3. spi0 slave m ode operation .................. ............................................... ......... 421 30.4. spi0 interrupt sources ....... .................................................................. ......... 422 30.5. serial clock phase and polari ty .............. ................. ............................ ......... 422 30.6. spi special function register s ............................................................ ......... 424 31. ezradiopro? serial interface ... ............................................................... ......... 431 31.1. signal descriptions.. ............................................................................. ......... 432 31.1.1. master out, slave in (m osi).............. .......................................... ......... 432 31.1.2. master in, slave out (m iso).............. .......................................... ......... 432 31.1.3. serial clock (sck ) ................................................................................ 432 31.1.4. slave select (nss) ....... ............................................................... ......... 432 31.2. spi1 master mode op eration .............. ................................................. ......... 433 31.3. spi slave operation on the ezradiopro peripheral side......... .................. 433 31.4. spi1 interrupt sources ....... .................................................................. ......... 433 31.5. serial clock phase and polari ty .............. ............................................. ......... 434
si102x/3x 10 rev. 0.3 31.6. using spi1 with the dma ... .................................................................. ......... 435 31.7. master mode spi1 dma transfers............. .......................................... ......... 435 31.8. master mode bidire ctional data transfer ... .......................................... ......... 435 31.9. master mode unidir ectional data transfer... ................................................. 437 31.10. spi special function registers ................ .......................................... ......... 437 32. ezradiopro ? 240?960 mhz transceiver....... .......................................... ......... 443 32.1. ezradiopro operat ing modes ................. .......................................... ......... 444 32.1.1. operating mode control .. ............... ............................................. ......... 445 32.2. interrupts ...... ....................................................................................... ......... 447 32.3. system timing......... ............................................................................. ......... 448 32.3.1. frequency control........... ............................................................. ......... 449 32.3.2. frequency programming...... ........................................................ ......... 449 32.3.3. easy frequency programming for fhss.. ................................. ........... 451 32.3.4. automatic state trans ition for frequency change ...... ................ ......... 452 32.3.5. frequency deviation ....... ............................................................. ......... 452 32.3.6. frequency offset adjustm ent............... ................................................. 453 32.3.7. automatic frequency control (afc) ...... .............. ............... .................. 453 32.3.8. tx data rate generator .. ............... ............................................. ......... 455 32.4. modulation options.... ........................................................................... ......... 455 32.4.1. modulation type..... ...................................................................... ......... 455 32.4.2. modulation data source.. ............................................................. ......... 456 32.4.3. pn9 mode ........... ......................................................................... ......... 460 32.5. internal functional blocks .. .................................................................. ......... 460 32.5.1. rx lna ........ ................................................................................ ......... 460 32.5.2. rx i-q mixer ..... ........................................................................... ......... 460 32.5.3. programmable gain amplif ier ............................................................... 460 32.5.4. adc ............ ................................................................................ ......... 461 32.5.5. digital modem ..... ......................................................................... ......... 461 32.5.6. synthesizer ......... ......................................................................... ......... 462 32.5.7. power amplifier ... ......................................................................... ......... 463 32.5.8. crystal oscillator ............... ........................................................... ......... 464 32.5.9. regulators......... ........................................................................... ......... 464 32.6. data handling and pa cket handler ..... ................................................. ......... 465 32.6.1. rx and tx fifos... ...................................................................... ......... 465 32.6.2. packet configuratio n................ .................................................. ........... 466 32.6.3. packet handler tx mode .............. ............................................... ......... 467 32.6.4. packet handler rx mode.............. ............................................... ......... 467 32.6.5. data whitening, manchester encodi ng, and crc .............. .................. 469 32.6.6. preamble detector .......... ............................................................. ......... 470 32.6.7. preamble length ...... .................................................................. ........... 470 32.6.8. invalid preamble detector ............... ............................................. ......... 471 32.6.9. synchronization word c onfiguration........... ................................. ......... 471 32.6.10. receive header check ...... ........................................................ ......... 472 32.6.11. tx retransmission and au to tx............... ................................. ......... 472 32.7. rx modem conf iguration ..................................................................... ......... 473
rev. 0.3 11 si102x/3x 32.7.1. modem settings for f sk and gfsk ............. ............................... ......... 473 32.8. auxiliary functions ............. .................................................................. ......... 473 32.8.1. smart reset ........ ......................................................................... ......... 473 32.8.2. output clock ..... ........................................................................... ......... 474 32.8.3. general purpose adc ..... ............... ............................................. ......... 475 32.8.4. temperature sensor ....... ............................................................. ......... 476 32.8.5. low battery detect or............ ........................................................ ......... 478 32.8.6. wake-up timer and 32 khz clock source .. ................................ ......... 479 32.8.7. low duty cycle mode ..... ............................................................. ......... 481 32.8.8. gpio configuratio n................ ............................................................... 482 32.8.9. antenna diversity ... ...................................................................... ......... 483 32.8.10. rssi and clear channel assessment ...... ................................. ......... 483 32.9. reference design.... ............................................................................. ......... 484 32.10. application notes and reference designs ............... ................................... 487 32.11. customer support ..... ......................................................................... ......... 487 32.12. register table a nd descriptions .............. .......................................... ......... 488 32.13. required changes to default register values......... ................................... 490 33. timers ................... .................................................................................. .............. 49 1 33.1. timer 0 and timer 1 ... ............... ........................................................... ......... 493 33.1.1. mode 0: 13-bit counter/timer ............ .......................................... ......... 493 33.1.2. mode 1: 16-bit counter/timer ............ .......................................... ......... 494 33.1.3. mode 2: 8-bit counter/timer with auto-reload.... ............... .................. 494 33.1.4. mode 3: two 8-bit co unter/timers (timer 0 only)... ............................. 495 33.2. timer 2 .......... ....................................................................................... ......... 501 33.2.1. 16-bit timer with auto-rel oad................ .............. ............... .................. 501 33.2.2. 8-bit timers with auto -reload...................................................... ......... 502 33.2.3. comparator 0/smartclock capture m ode .............. ................. ........... 502 33.3. timer 3 .......... ....................................................................................... ......... 507 33.3.1. 16-bit timer with auto-rel oad................ .............. ............... .................. 507 33.3.2. 8-bit timers with auto-r eload ............. ................................................. 508 33.3.3. smartclock/external o scillator capture mode ....... ................. ........... 508 34. programmable counter array............ ........................................................ ......... 513 34.1. pca counter/timer ............ .................................................................. ......... 514 34.2. pca0 interrupt sources...... .................................................................. ......... 515 34.3. capture/compare modules ..... ............................................................. ......... 516 34.3.1. edge-triggered capture m ode................ .............. ............... .................. 517 34.3.2. software timer (compare) mode................ ................................. ......... 518 34.3.3. high-speed output mode ............... ............................................. ......... 519 34.3.4. frequency output mode ............... ............................................... ......... 520 34.3.5. 8-bit, 9-bit, 10- bit and 11-bit pulse width modul ator modes.............. 521 34.3.6. 16-bit pulse width m odulator mode........... ................................. ......... 523 34.4. watchdog timer mode ... ...................................................................... ......... 524 34.4.1. watchdog timer o peration .................. ................................................. 524 34.4.2. watchdog timer usage ....... ........................................................ ......... 525 34.5. register descriptions for pc a0............. ............................................... ......... 527
si102x/3x 12 rev. 0.3 35. c2 interface ............. .................................................................................. ........... 533 35.1. c2 interface registers........ .................................................................. ......... 533 35.2. c2 pin sharing ........ ............................................................................. ......... 536 contact information ......... ................................................................................ ......... 538
rev. 0.3 13 si102x/3x list of figures figure 1.1. si102x block diagram ................... ............................................. ........... 28 figure 1.2. si103x block diagram ................... ............................................. ........... 28 figure 1.3. si102x/3x rx/tx dire ct-tie application example .. ............ ........... ......... 29 figure 1.4. si102x/3x antenna diversity application example ............ ........... ......... 29 figure 1.5. port i/o fu nctional block diagram ... .......................................... ........... 31 figure 1.6. pca block dia gram ................ .................................................. ............. 32 figure 1.7. adc0 functional blo ck diagram ............. ................................. ............. 33 figure 1.8. adc0 multiplexer bl ock diagram ............ ................................. ............. 34 figure 1.9. comparator 0 func tional block diagram .............. ............ ........... ......... 35 figure 1.10. comparator 1 func tional block diagram ................................. ........... 35 figure 3.1. lga-85 pinout diagr am (top view) ........ ................................. ............. 45 figure 3.2. lga-85 package drawin g ................ .......................................... ........... 46 figure 3.3. lga-85 land pattern ............. .................................................. ............. 48 figure 4.1. frequency sensitivit y (external cmos clock, 25c) ............... ............. 56 figure 4.2. typical voh curves, 1.8?3.8 v .............. ................................. ............. 58 figure 4.3. typical vol curves, 1.8?3.8 v ........ .......................................... ........... 59 figure 5.1. adc0 functional blo ck diagram ............. ................................. ............. 78 figure 5.2. 10-bit adc track and conversion example timing ? (bursten = 0) ........ .................................................................. ........... 81 figure 5.3. burst mode tracking example wit h repeat count set to 4 .................. 82 figure 5.4. adc0 equivalent i nput circuits ............ .............. ............... ........... ......... 83 figure 5.5. adc window compar e example: right-justified ? single-ended data ............... ........................................................ ......... 94 figure 5.6. adc window com pare example: left-justified ? single-ended data ............... ........................................................ ......... 94 figure 5.7. adc0 multiplexer bl ock diagram ............ ................................. ............. 95 figure 5.8. temperature sensor transfer function ............. ............... ........... ......... 97 figure 5.9. temperature sensor error with 1-point calibration ? (v ref = 1.68 v) ........... ............................................................... ........... 98 figure 5.10. voltage re ference functional blo ck diagram .............. ..................... 100 figure 6.1. comparator 0 func tional block diagram .............. ............ .................. 103 figure 6.2. comparator 1 func tional block diagram .............. ............ .................. 104 figure 6.3. comparator hysteresis plot ................. .............. ............... .................. 105 figure 7.1. cpn multiplexer blo ck diagram ............ .............. ............... .................. 112 figure 8.1. cip-51 block diagram ................... ............................................. ......... 115 figure 9.1. si102x/3x memory map ............... ............................................... ......... 124 figure 9.2. flash program memory map ............ .......................................... ......... 125 figure 9.3. address memory m ap for instruction fetches ....... ............ .................. 126 figure 10.1. multiplexed confi guration example ....... ................................. ........... 135 figure 10.2. non-multiplexed c onfiguration example ............. ............ .................. 136 figure 10.3. emif operat ing modes ........... ................................................. ......... 136 figure 10.4. non-multiplexed 16- bit movx timing ..... ................................. ......... 140 figure 10.5. non-multiplexed 8-bit movx without bank sele ct timing ................ 141
si102x/3x 14 rev. 0.3 figure 10.6. non-multiplexed 8-bit movx with bank select timing .......... ........... 142 figure 10.7. multiplexed 16-bit movx timing ........... ................................. ........... 143 figure 10.8. multiplexed 8-bit movx without bank select ti ming ............. ........... 144 figure 10.9. multiplexed 8-bit movx with bank select timing ............................. 145 figure 11.1. dma0 block diagram ............................................................... ......... 148 figure 12.1. crc0 block diagram ............................................................... ......... 161 figure 12.2. bit reverse register ................... ............................................. ......... 168 figure 13.1. polynomial re presentation ............ .......................................... ......... 169 figure 14.1. aes peripher al block diagram ...... .......................................... ......... 177 figure 14.2. key inversion data flow ............. ............................................. ......... 180 figure 14.3. aes block ci pher data flow .......... .......................................... ......... 186 figure 14.4. cipher block chaini ng mode ................... ................................. ......... 191 figure 14.5. cbc encryption data flow ................. .............. ............... .................. 192 figure 14.6. cbc decryption data flow ............ .......................................... ......... 196 figure 14.7. counter mode ................ ........................................................... ......... 199 figure 14.8. counter mode data flow ............ ............................................. ......... 200 figure 16.1. sfr page sta ck ................... .................................................. ........... 218 figure 16.2. sfr page sta ck while using sfr page 0x0 ? to access smb0adr .......... .................................................. ........... 219 figure 16.3. sfr page stack afte r spi0 interrupt occurs ...... ............ ........... ....... 220 figure 16.4. sfr page stack upon pca interrupt occurring ? during a spi0 isr ............ ........................................................ ......... 221 figure 16.5. sfr page stack u pon return from pca interrupt ............... ........... 222 figure 16.6. sfr page stack u pon return from spi0 interrupt ............... ........... 223 figure 18.1. flash security exam ple ........... ................................................. ......... 253 figure 19.1. si102x/3x power dist ribution ................ ................................. ........... 265 figure 19.2. clock tree di stribution ............ ................................................. ......... 266 figure 20.1. step down dc-dc buck converter block diagram ............... ........... 276 figure 22.1. reset sources ........ .................................................................. ......... 285 figure 22.2. power-on reset ti ming diagram ......... ................................. ........... 286 figure 23.1. clocking sources bl ock diagram ............ ................................. ......... 293 figure 23.2. 25 mhz external cr ystal example ......... ................................. ........... 295 figure 24.1. smartclock block di agram ............ ................................................. 302 figure 24.2. interpreting oscillation robustness (duty cycle) test results ......... 310 figure 25.1. pulse counter block diagram ........ .......................................... ......... 319 figure 25.2. mode examples ...... .................................................................. ......... 320 figure 25.3. reed switch configurations ........... .......................................... ......... 321 figure 25.4. debounce timing ........ ............................................................. ......... 325 figure 25.5. flutter exam ple ............. ........................................................... ......... 327 figure 26.1. lcd segment driver block diagram ................................................. 341 figure 26.2. lcd data register to lcd pin mapping ...... ............................ ......... 343 figure 26.3. contrast control mo de 1 ................ .......................................... ......... 345 figure 26.4. contrast control mo de 2 ................ .......................................... ......... 346 figure 26.5. contrast control mo de 3 ................ .......................................... ......... 346 figure 26.6. contrast control mo de 4 ................ .......................................... ......... 347
rev. 0.3 15 si102x/3x figure 27.1. port i/o f unctional block diagram ............... ............................ ......... 358 figure 27.2. port i/o cell block diagram ........ ............................................. ......... 359 figure 27.3. crossbar priority decoder with no pins skipped ............ .................. 363 figure 27.4. crossbar priority decoder with crystal pins skipped ............ ........... 364 figure 28.1. smbus block diagram ............................................................. ......... 388 figure 28.2. typical smbus confi guration ................ ................................. ........... 389 figure 28.3. smbus transaction ..... ............................................................. ......... 390 figure 28.4. typical smbus scl generation .............. ................................. ......... 392 figure 28.5. typical master wr ite sequence .............. ................................. ......... 401 figure 28.6. typical ma ster read sequence ....... ................................................. 402 figure 28.7. typical sl ave write sequence .. ............................................... ......... 403 figure 28.8. typical slave read sequence ................ ................................. ......... 404 figure 29.1. uart0 block diagram ............................................................. ......... 409 figure 29.2. uart0 baud rate logic ................ .......................................... ......... 410 figure 29.3. uart interconnect di agram ............ ................................................. 411 figure 29.4. 8-bit uart timing diagram ........... .......................................... ......... 411 figure 29.5. 9-bit uart timing diagram ........... .......................................... ......... 412 figure 29.6. uart multi-proc essor mode interconne ct diagram ......... ................ 413 figure 30.1. spi block di agram ............... .................................................. ........... 418 figure 30.2. multiple-master mode connection diagram ........ ............ .................. 421 figure 30.3. 3-wire single master and 3-wire single slave mode ? connection diagram ............. .................................................. ........... 421 figure 30.4. 4-wire single master mode and 4-wire slave mode ? connection diagram ............. .................................................. ........... 421 figure 30.5. master mode data/ clock timing ............. ................................. ......... 423 figure 30.6. slave mode data/clock timing (ckpha = 0) .. ............... .................. 423 figure 30.7. slave mode data/clock timing (ckpha = 1) .. ............... .................. 424 figure 30.8. spi master timing (ckpha = 0) .... .......................................... ......... 428 figure 30.9. spi master timing (ckpha = 1) .... .......................................... ......... 428 figure 30.10. spi slave timing (c kpha = 0) ............. ................................. ......... 429 figure 30.11. spi slave timing (c kpha = 1) ............. ................................. ......... 429 figure 31.1. spi block di agram ............... .................................................. ........... 431 figure 31.2. master mode data/ clock timing ............. ................................. ......... 434 figure 31.3. spi master timing (ckpha = 0) .... .......................................... ......... 441 figure 32.1. state machi ne diagram ........... ................................................. ......... 445 figure 32.2. tx timing . ................................................................................ ......... 448 figure 32.3. rx timi ng .................. ............................................................... ......... 449 figure 32.4. frequency deviation .... ............... ............................................. ......... 452 figure 32.5. sensitivit y at 1% per vs. carrier frequency of fset ........... .............. 454 figure 32.6. fsk vs. gfsk spectrums .............. .......................................... ......... 456 figure 32.7. direct synchronous mode example ........ ................................. ......... 459 figure 32.8. direct asynchronous mode example ...... ................................. ......... 459 figure 32.9. microcontroll er connections ........... .......................................... ......... 460 figure 32.10. pll synthesizer bl ock diagram ............ ................................. ......... 462 figure 32.11. fifo thresholds .. .................................................................. ......... 465
si102x/3x 16 rev. 0.3 figure 32.12. packet struct ure ................. .................................................. ........... 466 figure 32.13. multiple packets in tx packet handler .......... ............... .................. 467 figure 32.14. required rx pa cket structure with packet h andler disabled ........ 467 figure 32.15. multiple packets in rx packet ha ndler .......... ............... .................. 468 figure 32.16. multiple packets in rx with crc or header error ........ .................. 468 figure 32.17. operation of data whitening, manchester encoding, ? and crc ................. ............................................................... ......... 470 figure 32.18. manchester coding example ......... ................................................. 470 figure 32.19. header ....... ............................................................................. ......... 472 figure 32.20. por glitch parameters ......... ................................................. ......... 473 figure 32.21. general pu rpose adc architecture ................................................ 476 figure 32.22. temperatur e ranges using adc8 .. ................................................ 478 figure 32.23. wut interrupt and wut operation ....... ................................. ......... 481 figure 32.24. low duty c ycle mode ........... ................................................. ......... 482 figure 32.25. rssi value vs. input power ......... .......................................... ......... 484 figure 32.26. si1024 split rf tx/rx direct-tie ? reference design?schematic ............... ............................... ......... 485 figure 32.27. si1020 switch ma tching reference design?sc hematic ....... ......... 486 figure 33.1. t0 mode 0 bl ock diagram .............. .......................................... ......... 494 figure 33.2. t0 mode 2 bl ock diagram .............. .......................................... ......... 495 figure 33.3. t0 mode 3 bl ock diagram .............. .............. ............................ ......... 496 figure 33.4. timer 2 16-bit mode block diagram ....... ................................. ......... 501 figure 33.5. timer 2 8-bit mode block diagram ....... ................................. ........... 502 figure 33.6. timer 2 capture mode block diagram ................ ............ .................. 503 figure 33.7. timer 3 16-bit mode block diagram ....... ................................. ......... 507 figure 33.8. timer 3 8-bit mode block diagram ....... ................................. ........... 508 figure 33.9. timer 3 capture mode block diagram ................ ............ .................. 509 figure 34.1. pca block diagram ... ............................................................... ......... 513 figure 34.2. pca counter/timer block diagram ......... ................................. ......... 515 figure 34.3. pca interrupt block diagram ................ ................................. ........... 516 figure 34.4. pca capture mode dia gram ............ ................................................. 518 figure 34.5. pca software time r mode diagram ....... ................................. ......... 519 figure 34.6. pca high-speed out put mode diagram ... ............................... ......... 520 figure 34.7. pca frequen cy output mode .......... ................................................. 521 figure 34.8. pca 8-bit pwm mode diagram ......... .............. ............... .................. 522 figure 34.9. pca 9, 10 and 11-bi t pwm mode diagram .......... ................. ........... 523 figure 34.10. pca 16-bit pwm mode ................ .......................................... ......... 524 figure 34.11. pca module 5 wi th watchdog timer enabled .... ................. ........... 525 figure 35.1. typical c2 pin shar ing ................ ............................................. ......... 536
rev. 0.3 17 si102x/3x list of tables table 2.1. product select ion guide ................. ............................................. ........... 36 table 3.1. pin definitions for t he si102x/3x ............ .............. ............... ........... ......... 37 table 3.2. lga-85 package dimensions ........... .......................................... ........... 46 table 3.3. lga-85 land patte rn dimensions ......... .............. ............... ........... ......... 48 table 4.1. absolute maximum rati ngs ................... .............. ............... ........... ......... 50 table 4.2. global electrical char acteristics ............ .............. ............... ........... ......... 51 table 4.3. digital supply curr ent at vbat pi n with dc-dc ? converter enabled ............... ........................................................ ........... 51 table 4.4. digital supply curr ent with dc-dc converter dis abled ............ ............. 52 table 4.5. port i/ o dc electrical char acteristics ......... ................................. ........... 57 table 4.6. reset electric al characteristics ...... ............................................. ........... 60 table 4.7. power managem ent electrical specifications .... ............................ ......... 61 table 4.8. flash electrical char acteristics ...... ............................................. ........... 61 table 4.9. internal precision o scillator electrical characteri stics ........... ................ 61 table 4.10. internal low-power oscillator electrical characte ristics ......... ............. 61 table 4.11. smartclock characteri stics ........... .......................................... ........... 62 table 4.12. adc0 electrical char acteristics ........... .............. ............... ........... ......... 62 table 4.13. temperature sensor electrical characteristics .... ............ ........... ......... 63 table 4.14. voltage reference elec trical characteristics ....... ............ ........... ......... 64 table 4.15. iref0 electrical char acteri stics .......... .............. ............... ........... ......... 65 table 4.16. comparator electrical characteristics .... ................................. ............. 66 table 4.17. vreg0 electric al characteristics .... .......................................... ........... 67 table 4.18. lcd0 el ectrical characteristics .. ............................................... ........... 68 table 4.19. pc0 electrical characteristics ......... .......................................... ........... 68 table 4.20. dc0 (buck c onverter) electrical c haracteristics ........... .............. ......... 69 table 4.21. dc characteri stics ............... ........................................................ ......... 70 table 4.22. synthesizer ac elec trical characteristi cs .............. ................. ............. 71 table 4.23. receiver ac electric al characteristics ... ................................. ............. 72 table 4.24. transmitter ac electr ical characteristics .......... ............... ........... ......... 73 table 4.25. auxiliary block specifications .............. .............. ............... ........... ......... 74 table 4.26. digital io sp ecifications (nirq) .... ............................................. ........... 75 table 4.27. gpio specificati ons (gpio_0, gpio_1, and gpio _2) ........... ............. 75 table 4.28. absolute maximum ratings ........ ............................................... ........... 76 table 5.1. representative conversi on times and ener gy consumption ? for the sar adc with 1.65 v high-speed vref .......... .............. ........... 85 table 8.1. cip-51 instruction se t summary .............. ................................. ........... 117 table 10.1. emif pinout .. ............................................................................. ......... 132 table 10.2. ac parameters for external memory interface ..... ............ .................. 146 table 12.1. example 16-bit crc ou tputs ............ ................................................. 162 table 12.2. example 32-bit crc ou tputs ............ .............. ................................... 164 table 14.1. extended key output byte order .... .......................................... ......... 183 table 14.2. 192-bit key dm a usage .................. .......................................... ......... 184 table 14.3. 256-bit key dm a usage .................. .......................................... ......... 184
si102x/3x 18 rev. 0.3 table 15.1. encoder input and output data sizes ................................................ 208 table 15.2. manchester encoding ............ .................................................. ........... 209 table 15.3. manchester decoding ................... ............................................. ......... 210 table 15.4. three-out-of- six encoding nibble ....... .............. ............... .................. 211 table 15.5. three-out-of- six decoding .............. .......................................... ......... 212 table 16.1. sfr map (0xc 0?0xff) ............ ................................................. ......... 228 table 16.2. sfr map (0x80?0xbf) .. ............... ............................................. ......... 229 table 16.3. special functi on registers .............. .......................................... ......... 230 table 17.1. interrupt summ ary ................. .................................................. ........... 240 table 18.1. flash security summar y ................. .......................................... ......... 254 table 19.1. power modes .. ........................................................................... ......... 264 table 20.1. ipeak inductor current limit settings ..... ................................. ........... 277 table 23.1. recommended xfcn se ttings for crystal mode ... ................. ........... 295 table 23.2. recommended xfcn settings for rc and c modes ................ ......... 296 table 24.1. smartclock internal registers ............. ................................. ........... 303 table 24.2. smartclock load c apacitance settings .............. ................. ........... 309 table 24.3. smartclock bias setti ngs ............. .......................................... ......... 310 table 25.1. pull-up resistor current ........... ................................................. ......... 322 table 25.2. sample rate duty-cycl e multiplier ......... ................ ................. ........... 322 table 25.3. pull-up duty-cycle mult iplier ........... .......................................... ......... 322 table 25.4. average pull-up cu rrent (sample rate = 250 s) . ................. ........... 323 table 25.5. average pull-up cu rrent (sample rate = 500 s) . ................. ........... 323 table 25.6. average pull- up current (sample rate = 1 ms) ................. .............. 323 table 25.7. average pull-up cu rrent (sample rate = 2 ms) .. ............ .................. 323 table 26.1. bit configurations to select contrast control modes ........ .................. 345 table 27.1. port i/o a ssignment for analog functions ...... ................................... 360 table 27.2. port i/o a ssignment for digital functions ...... ............................ ......... 361 table 27.3. port i/o assignmen t for external digital event ? capture functions ............. ........................................................ ......... 361 table 28.1. smbus clock source selection .............. ................................. ........... 392 table 28.2. minimum sda setup and hold times ...... ................................. ......... 393 table 28.3. sources for hardwa re changes to smb0cn ......... ................. ........... 397 table 28.4. hardware address recognition ex amples (ehack = 1) ................... 398 table 28.5. smbus status decodi ng with hardware ack generation ? disabled (ehack = 0) ......... ............................................................... 405 table 28.6. smbus status decodi ng with hardware ack generation ? enabled (ehack = 1) ........ ........................................................ ......... 407 table 29.1. timer settings for standard baud rates ? using the internal 24.5 mhz oscillator ......... ............................ ......... 416 table 29.2. timer settings for standard baud rates ? using an external 22.1184 mh z oscillator .... ............................ ......... 416 table 30.1. spi slave timing para meters ......... .......................................... ......... 430 table 31.1. spi timing parameters ............................................................. ......... 441 table 32.1. ezradiopro operatin g modes ............... ................................. ......... 444 table 32.2. ezradiopro operat ing modes response time ... ................. ........... 445
rev. 0.3 19 si102x/3x table 32.3. frequency band selecti on ................ ................................................. 450 table 32.4. packet handler registers ......... ................................................. ......... 469 table 32.5. minimum receiver se ttling time ............ ................................. ........... 471 table 32.6. por parameters ..... .................................................................. ......... 474 table 32.7. temperature sensor range .............. ................................................. 477 table 32.8. antenna diversity control ......... ................................................. ......... 483 table 32.9. ezradiopro internal register descriptions ........ ............ .................. 488 table 33.1. timer 0 running modes ............... ............................................. ......... 493 table 34.1. pca timebase input op tions ............ ................................................. 514 table 34.2. pca0cpm and pca0 pwm bit settings for pca ? capture/compare modules ... .................................................. ........... 516 table 34.3. watchdog timer timeout intervals1 ......... ................................. ......... 526
si102x/3x 20 rev. 0.3 list of registers sfr definition 5.1. adc0cn : adc0 control ........... .......................................... ........... 86 sfr definition 5.2. adc0cf: adc0 configuration ........ ................................. ............. 87 sfr definition 5.3. adc0 ac: adc0 accumulator configuratio n ................. ................ 88 sfr definition 5.4. adc0pwr: adc0 burst mode power-up time ............... ............. 89 sfr definition 5.5. adc0tk: adc0 burst mode track time ....... ............ ........... ......... 90 sfr definition 5.6. adc0h: adc0 data word high byte ......... ............... ........... ......... 91 sfr definition 5.7. adc0l: adc0 data word low byte ....... ............................ ........... 91 sfr definition 5.8. adc0gth: adc0 greater-than high byte ... ............ ........... ......... 92 sfr definition 5.9. adc0gtl: adc0 greater-than low byte .... ............ ........... ......... 92 sfr definition 5.10. adc0lth: adc0 less-than high byte ...... ............ ........... ......... 93 sfr definition 5.11. adc0ltl: ad c0 less-than low byte ........ ............ ........... ......... 93 sfr definition 5.12. adc0 mx: adc0 input channel select .... ........................... ......... 96 sfr definition 5.13. toffh: temperature sensor offset high by te .............. ............. 99 sfr definition 5.14. toffl : temperature sensor offset low byte ............ ................ 99 sfr definition 5.15. ref0cn: volt age reference control .......... ............ .................. 102 sfr definition 6.1. cpt0cn: comparator 0 control ................. ............... .................. 106 sfr definition 6.2. cpt0 md: comparator 0 mode selection .. .................................. 107 sfr definition 6.3. cpt1cn: comparator 1 control ................. ............... .................. 108 sfr definition 6.4. cpt1 md: comparator 1 mode selection .. .................................. 109 sfr definition 7.1. iref 0cn: current reference control .... ............................ ......... 110 sfr definition 7.2. iref0cf: cu rrent reference configuration .. ............ .................. 111 sfr definition 7.3. cpt0 mx: comparator0 input channel sele ct ............... .............. 113 sfr definition 7.4. cpt1 mx: comparator1 input channel sele ct ............... .............. 114 sfr definition 8.1. dpl: data po inter low byte ......... .............. ............... .................. 121 sfr definition 8.2. dph: data pointer high byte . ............................................. ......... 121 sfr definition 8.3. sp: sta ck pointer ................. ............................................... ......... 122 sfr definition 8.4. acc: accumulator ........ ............................................................... 122 sfr definition 8.5. b: b r egister ............... ........................................................ ......... 122 sfr definition 8.6. psw: program status word ..... .......................................... ......... 123 sfr definition 9.1. psban k: program space bank select .... ................................... 127 sfr definition 10.1. emi0 cn: external memory interface co ntrol .............. .............. 133 sfr definition 10.2. emi0 cf: external memory configuration .................................. 134 sfr definition 10.3. emi0 tc: external memory timing contro l .................. .............. 139 sfr definition 11.1. dma0en: dm a0 channel enable ............... ............ .................. 151 sfr definition 11.2. dma0int: dm a0 full-length interrupt ........ ............ .................. 152 sfr definition 11.3. dma0mint: dm a0 mid-point interrupt ....... ............ .................. 153 sfr definition 11.4. dma0 busy: dma0 busy ......... ................................................. 154 sfr definition 11.5. dma0sel: dma0 channel select for confi guration ................. 155 sfr definition 11.6. dma0nmd: dma channel mode .................. ................. ........... 156 sfr definition 11.7. dma0ncf: dma channel configuration ....... ................. ........... 157 sfr definition 11.8. dma0nbah: memory base address high byte .......... .............. 158 sfr definition 11.9. dm a0nbal: memory base address low byte ........... .............. 158 sfr definition 11.10. dma0naoh: memory address offset high byte ......... ........... 159
rev. 0.3 21 si102x/3x sfr definition 11.11. dm a0naol: memory address offset low byte ....... .............. 159 sfr definition 11.12. dma0 nszh: transfer size high byte .. ................................... 160 sfr definition 11.13. dma0nszl: memory transfer size low byte ............. ........... 160 sfr definition 12.1. crc0cn : crc0 control ........ .......................................... ......... 165 sfr definition 12.2. crc0in: crc0 data input ............ ................................. ........... 166 sfr definition 12.3. crc0da t: crc0 data output ............. ............................ ......... 166 sfr definition 12.4. crc0auto: crc0 automatic control ........ ............ .................. 167 sfr definition 12.5. crc0cnt: crc0 automatic flash sector count .......... ........... 167 sfr definition 12.6. crc0flip: crc0 bit flip .............. ................................. ........... 168 sfr definition 13.1. crc1cn : crc1 control ........ .......................................... ......... 173 sfr definition 13.2. crc1in: crc1 data in ............. .............. ............... .................. 174 sfr definition 13.3. crc1poll: crc1 polynomial lsb ............ ............ .................. 174 sfr definition 13.4. crc1polh: crc1 polynomial msb ............ ................. ........... 174 sfr definition 13.5. crc1outl: c rc1 output lsb ...... ................................. ......... 175 sfr definition 13.6. crc1outh: crc1 output msb .... ................................. ......... 175 sfr definition 14.1. aes0 bcfg: aes block configur ation ................. ..................... 203 sfr definition 14.2. aes0 dcfg: aes data configuration .... ................................... 204 sfr definition 14.3. aes0bi n: aes block input ..... .......................................... ......... 205 sfr definition 14.4. aes0xi n: aes xor input ...... .......................................... ......... 206 sfr definition 14.5. aes0ki n: aes key input ....... .......................................... ......... 206 sfr definition 14.6. aes0yout: aes y output ........... ................ ................. ........... 207 sfr definition 15.1. enc0cn: enco der decoder 0 control ........ ............ .................. 215 sfr definition 15.2. enc0l: enc0 data low byte .......................................... ......... 216 sfr definition 15.3. enc0m: enc0 data middle byte .. ................................. ........... 216 sfr definition 15.4. enc0h: enc0 data high byte ...... ................................. ........... 216 sfr definition 16.1. sfrpgcn: sf r page control ...... ................................. ........... 224 sfr definition 16.2. sfrpage: sfr page ............ .......................................... ......... 225 sfr definition 16.3. sfrnext: sfr ne xt ............. .......................................... ......... 226 sfr definition 16.4. sfrlast: sfr last ............ ............................................. ......... 227 sfr definition 17.1. ie: in terrupt enable .............. ............................................. ......... 242 sfr definition 17.2. ip: inte rrupt priority ............ ............................................... ......... 243 sfr definition 17.3. eie1 : extended interrupt enable 1 ......... ................................... 244 sfr definition 17.4. eip1 : extended interrupt priority 1 ....... ............................ ......... 245 sfr definition 17.5. eie2 : extended interrupt enable 2 ......... ................................... 246 sfr definition 17.6. eip2 : extended interrupt priority 2 ....... ............................ ......... 247 sfr definition 17.7. it01cf: int0 /int1 configuration .... ................................. ......... 249 sfr definition 18.1. deviceid: devi ce identification .... ................................. ........... 255 sfr definition 18.2. revid: revision identification .............. ............................ ......... 256 sfr definition 18.3. psctl: prog ram store r/w control ................................ ......... 260 sfr definition 18.4. flk ey: flash lock and key ..... ................................................. 261 sfr definition 18.5. flscl: flash scale ............. ............................................. ......... 262 sfr definition 18.6. flwr: flash wr ite only ............. .............. ............... .................. 262 sfr definition 18.7. frbcn: flash read buffer control .......... ............... .................. 263 sfr definition 19.1. pclk act: peripheral active clock enable .......... ..................... 267 sfr definition 19.2. pclken: peri pheral clock enable .. ................................. ......... 268
si102x/3x 22 rev. 0.3 sfr definition 19.3. clkmode: clo ck mode ................ ................................. ........... 269 sfr definition 19.4. pmu0cf: power management unit configuration ..................... 272 sfr definition 19.5. pmu0fl: po wer management unit flag ....... ................. ........... 273 sfr definition 19.6. pmu0md: po wer management unit mode .... ................. ........... 274 sfr definition 19.7. pcon: powe r management control register ................ ........... 275 sfr definition 20.1. dc0cn: dc-dc converter control ............. ............ .................. 280 sfr definition 20.2. dc0cf: dc- dc converter configuration ................ .................. 281 sfr definition 20.3. dc0md: dc-dc converter mode ................ ............ .................. 282 sfr definition 20.4. dc0rdy: dc -dc converter ready indicator ................ ........... 283 sfr definition 21.1. reg0cn: vo ltage regulator control .......... ............ .................. 284 sfr definition 22.1. vdm0cn: v dd supply monitor control ...... ............ .................. 289 sfr definition 22.2. rstsrc : reset source ......... .......................................... ......... 292 sfr definition 23.1. clksel: clock select ............ .......................................... ......... 298 sfr definition 23.2. oscicn: inte rnal oscillator control ......... ............... .................. 299 sfr definition 23.3. oscicl: intern al oscillator calibration .... ............... .................. 300 sfr definition 23.4. oscx cn: external oscillator control ................. .............. ......... 301 sfr definition 24.1. rtc0key: smartclock lock and key ........ ................. ........... 305 sfr definition 24.2. rtc0adr: smartclock address .. ................................. ......... 305 sfr definition 24.3. rtc0dat: sm artclock data ........ ................................. ......... 306 internal register definition 24. 4. rtc0cn: smartclock control ............................. 313 internal register definition 24.5. rtc0xcn: smartclock oscillator control ........... 314 internal register definiti on 24.6. rtc0xcf: smartclock ? oscillator configurat ion .............. ................. ........... 315 internal register definition 24. 7 . rtc0cf: smartclock confi guration ......... ........... 316 internal register definition 24.8. capturen: smartclock ti mer capture .. ........... 317 internal register definition 24. 9. alarm0bn: smartclock alarm 0 ? match value ...... ............................................. ......... 317 internal register definition 24.10 . alarm1bn: smartclock alarm 1 ? match value ........... .............. ............... .................. 318 internal register definition 24.11 . alarm2bn: smartclock alarm 2 ? match value ...... ............................................. ......... 318 sfr definition 25.1. pc0md: pc0 mode configuration ............... ............ .................. 328 sfr definition 25.2. pc0pcf: pc 0 mode pull-up configuration .. ................. ........... 329 sfr definition 25.3. pc0t h: pc0 threshold configuration .... ................................... 330 sfr definition 25.4. pc0sta t: pc0 status ........... .......................................... ......... 331 sfr definition 25.5. pc0dch: pc0 debounce configurat ion high ........... ................ 332 sfr definition 25.6. pc0dcl: pc0 debounce configurat ion low ............ ................ 333 sfr definition 25.7. pc0ctr0h: pc0 counter 0 high (msb) ...... ................. ........... 334 sfr definition 25.8. pc0ctr0m: pc0 counter 0 middle ................................. ......... 334 sfr definition 25.9. pc0c tr0l: pc0 counter 0 low (lsb) ......... ................. ........... 334 sfr definition 25.10. pc0ctr1h: pc0 counter 1 high (msb) .... ................. ........... 335 sfr definition 25.11. pc0ctr1m: pc0 counter 1 middle ............................... ......... 335 sfr definition 25.12. pc 0ctr1l: pc0 counter 1 low (lsb) .............. ..................... 335 sfr definition 25.13. pc0cmp0h: pc0 comparator 0 high (msb) ............... ........... 336 sfr definition 25.14. pc0cmp0m: pc0 comparator 0 middle ..... ................. ........... 336
rev. 0.3 23 si102x/3x sfr definition 25.15. pc0cmp0l: pc0 comparator 0 low (lsb) ................. ........... 336 sfr definition 25.16. pc0cmp1h: pc0 comparator 1 high (msb) ............... ........... 337 sfr definition 25.17. pc0cmp1m: pc0 comparator 1 middle ..... ................. ........... 337 sfr definition 25.18. pc0cmp1l: pc0 comparator 1 low (lsb) ................. ........... 337 sfr definition 25.19. pc0hist: pc0 history ......... .......................................... ......... 338 sfr definition 25.20. pc0int 0: pc0 interrupt 0 ..... .......................................... ......... 339 sfr definition 25.21. pc0int 1: pc0 interrupt 1 ..... .......................................... ......... 340 sfr definition 26.1. lcd0dn : lcd0 data .............. .......................................... ......... 342 sfr definition 26.2. lcd0cn: lcd0 control register .. ................................. ........... 344 sfr definition 26.3. lcd0cntrst : lcd0 contrast adjustment ............ .................. 348 sfr definition 26.4. lcd0 mscn: lcd0 master control ........ ................................... 349 sfr definition 26.5. lcd0mscf: l cd0 master configuration .... ............ .................. 350 sfr definition 26.6. lcd0pw r: lcd0 power ........ .......................................... ......... 350 sfr definition 26.7. lcd0 vbmcn: lcd0 vbat monitor contro l ............... .............. 351 sfr definition 26.8. lcd0clkdivh: lcd0 refr esh rate prescaler high byte ........ 352 sfr definition 26.9. lcd0clkdiv l: lcd refresh rate presca ler low byte ........... 352 sfr definition 26.10. lcd0 blink: lcd0 blink mask ................................................ 353 sfr definition 26.11. lcd0 togr: lcd0 toggle rate .......... ................................... 354 sfr definition 26.12. lcd0 cf: lcd0 configuration ................................................. 355 sfr definition 26.13. lc d0chpcn: lcd0 charge pump cont rol .............. .............. 355 sfr definition 26.14. lc d0chpcf: lcd0 charge pump co nfiguration .... .............. 356 sfr definition 26.15. lc d0chpmd: lcd0 charge pump mode ............ .................. 356 sfr definition 26.16. lcd0 bufcn: lcd0 buf fer co ntrol ........... ............ .................. 356 sfr definition 26.17. lcd0 bufcf: lcd0 buffer configuratio n ................. .............. 357 sfr definition 26.18. lcd0 bufmd: lcd0 buffer mode ........ ................................... 357 sfr definition 26.19. lc d0vbmcf: lcd0 vbat monitor c onfiguration .... .............. 357 sfr definition 27.1. xbr0: port i/o crossbar register 0 ..... ............................ ......... 365 sfr definition 27.2. xbr1: port i/o crossbar register 1 ..... ............................ ......... 366 sfr definition 27.3. xbr2: port i/o crossbar register 2 ..... ............................ ......... 367 sfr definition 27.4. p0mask: port 0 mask register ...... ................................. ........... 368 sfr definition 27.5. p0mat: port0 match register ....... ................................. ........... 368 sfr definition 27.6. p1mask: port 1 mask register ...... ................................. ........... 369 sfr definition 27.7. p1mat: port1 match register ....... ................................. ........... 369 sfr definition 27.8. p0: port0 ....... .................................................................. ........... 371 sfr definition 27.9. p0skip: port0 skip .............. ............................................. ......... 371 sfr definition 27.10. p0mdin: port 0 input mode ............ ................................. ......... 372 sfr definition 27.11. p0md out: port0 output mode ................. ............ .................. 372 sfr definition 27.12. p0drv: port0 drive strength .................... ............ .................. 373 sfr definition 27.13. p1: po rt1 ............ ............................................................. ......... 373 sfr definition 27.14. p1skip: port1 skip ............ ............................................. ......... 374 sfr definition 27.15. p1mdin: port 1 input mode ............ ................................. ......... 374 sfr definition 27.16. p1md out: port1 output mode ................. ............ .................. 375 sfr definition 27.17. p1drv: port1 drive strength .................... ............ ........... ....... 375 sfr definition 27.18. p2: po rt2 ............ ............................................................. ......... 376 sfr definition 27.19. p2skip: port2 skip ............ ............................................. ......... 376
si102x/3x 24 rev. 0.3 sfr definition 27.20. p2mdin: port 2 input mode ............ ................................. ......... 377 sfr definition 27.21. p2md out: port2 output mode ................. ............ .................. 377 sfr definition 27.22. p2drv: port2 drive strength .................... ............ .................. 378 sfr definition 27.23. p3: po rt3 ............ ............................................................. ......... 378 sfr definition 27.24. p3mdin: port 3 input mode ............ ................................. ......... 379 sfr definition 27.25. p3md out: port3 output mode ................. ............ .................. 379 sfr definition 27.26. p3drv: port3 drive strength .................... ............ .................. 380 sfr definition 27.27. p4: po rt4 ............ ............................................................. ......... 380 sfr definition 27.28. p4mdin: port 4 input mode ............ ................................. ......... 381 sfr definition 27.29. p4md out: port4 output mode ................. ............ .................. 381 sfr definition 27.30. p4drv: port4 drive strength .................... ............ .................. 382 sfr definition 27.31. p5: po rt5 ............ ............................................................. ......... 382 sfr definition 27.32. p5mdin: port 5 input mode ............ ................................. ......... 383 sfr definition 27.33. p5md out: port5 output mode ................. ............ .................. 383 sfr definition 27.34. p5drv: port5 drive strength .................... ............ .................. 384 sfr definition 27.35. p6: po rt6 ............ ............................................................. ......... 384 sfr definition 27.36. p6mdin: port 6 input mode ............ ................................. ......... 385 sfr definition 27.37. p6md out: port6 output mode ................. ............ .................. 385 sfr definition 27.38. p6drv: port6 drive strength .................... ............ ........... ....... 386 sfr definition 27.39. p7: po rt7 ............ ............................................................. ......... 386 sfr definition 27.40. p7md out: port7 output mode ................. ............ .................. 387 sfr definition 27.41. p7drv: port7 drive strength .................... ............ .................. 387 sfr definition 28.1. smb0cf: smbu s clock/configuration ........ ............ .................. 394 sfr definition 28.2. smb0cn: smbu s control .............. ................................. ........... 396 sfr definition 28.3. smb0 adr: smbus slave address ......... ................................... 398 sfr definition 28.4. smb0adm: smbus slave address mask .... ............ .................. 399 sfr definition 28.5. smb0dat: smbu s data ................ ................................. ........... 400 sfr definition 29.1. scon0: serial port 0 control ..... .............. ............... .................. 414 sfr definition 29.2. sbuf0: seri al (uart0) port data buffer . ............... .................. 415 sfr definition 30.1. spi0cfg: spi 0 configuration ....... ................................. ........... 425 sfr definition 30.2. spi0cn : spi0 control ............ .......................................... ......... 426 sfr definition 30.3. spi0ckr: spi 0 clock rate ........... ................................. ........... 427 sfr definition 30.4. spi0dat: spi0 data ........... ............................................. ......... 427 sfr definition 31.1. spi1cfg: spi 1 configuration ....... ................................. ........... 438 sfr definition 31.2. spi1cn : spi1 control ............ .......................................... ......... 439 sfr definition 31.3. spi1ckr: spi 1 clock rate ........... ................................. ........... 440 sfr definition 31.4. spi1dat: spi1 data ........... ............................................. ......... 440 sfr definition 33.1. ckcon: clock contro l ........... .......................................... ......... 492 sfr definition 33.2. tcon: timer c ontrol .............. .......................................... ......... 497 sfr definition 33.3. tmod: timer m ode ................ .......................................... ......... 498 sfr definition 33.4. tl0: timer 0 low byte ......... ............................................. ......... 499 sfr definition 33.5. tl1: timer 1 low byte ......... ............................................. ......... 499 sfr definition 33.6. th0: timer 0 high byte .............. .............. ............... .................. 500 sfr definition 33.7. th1: timer 1 high byte .............. .............. ............... .................. 500 sfr definition 33.8. tmr2cn: timer 2 control ............. ................................. ........... 504
rev. 0.3 25 si102x/3x sfr definition 33.9. tmr2rll: ti mer 2 reload register low byte ............... ........... 505 sfr definition 33.10. tmr2 rlh: timer 2 reload register high byte . ..................... 505 sfr definition 33.11. tmr2l: timer 2 low byte .... .......................................... ......... 506 sfr definition 33.12. tmr2h timer 2 high byte ........... ................................. ........... 506 sfr definition 33.13. tmr3 cn: timer 3 control .... .......................................... ......... 510 sfr definition 33.14. tmr3 rll: timer 3 reload re gister low byte ... ..................... 511 sfr definition 33.15. tmr3 rlh: timer 3 reload register high byte . ..................... 511 sfr definition 33.16. tmr3l: timer 3 low byte .... .......................................... ......... 512 sfr definition 33.17. tmr3h timer 3 high byte ........... ................................. ........... 512 sfr definition 34.1. pca0cn : pca control ........... .......................................... ......... 527 sfr definition 34.2. pca0md: pca mo de ............. .......................................... ......... 528 sfr definition 34.3. pca0pwm: pca pwm configuration ......... ............ .................. 529 sfr definition 34.4. pca0cpmn : pca capture/compare mode .. ................. ........... 530 sfr definition 34.5. pca 0l: pca counter/timer low byte ................. ..................... 531 sfr definition 34.6. pca0h: pca counter/timer high byte ....... ............ .................. 531 sfr definition 34.7. pca0cpln: pca capture module low byte . ................. ........... 532 sfr definition 34.8. pca0cphn: pca capture module high byte ................ ........... 532 c2 register definition 35.1. c2ad d: c2 address ....... .............. ............... .................. 533 c2 register definition 35.2. devi ceid: c2 device id .............. ............... .................. 534 c2 register definition 35.3. revi d: c2 revision id ............... ................................... 534 c2 register definition 35.4. fp ctl: c2 flash programming cont rol ............. ........... 535 c2 register definition 35.5. fp dat: c2 flash programming data ................. ........... 535
si102x/3x 26 rev. 0.3 1. system overview si102x/3x devices are fully integrated mixed-signal system-on-a-chip mcus. highlighted features are listed below. refer to ta b l e 2.1 for specific product feature selection and part ordering numbers. ? 240-960 mhz ezradiopro(r) transceiver ? power efficient on-chip dc-dc buck converter ? high-speed pipelined 8051-compatible microcontroller core (up to 25 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? true 10-bit 300 ksps, or 12-bit 75 ksps single-ended adc with 16 external analog inputs and 4 internal input s such as various power supply voltages and the temperature sensor ? 6-bit programmable current reference ? precision programmable 24.5 mhz internal oscillator with spread sp ectrum technology ? 128 kb, 64 kb, 32 kb, or 16 kb of on-chip flash memory ? 8448 or 4352 bytes of on-chip ram ? 128 segment lcd driver ? smbus/i 2 c, enhanced uart, and two enhanced spi serial interfaces implemented in hardware ? four general-purpose 16-bit timers ? programmable counter/timer array (pca) with six capture/compare modules and watchdog timer function ? hardware aes, dma, and pulse counter ? on-chip power-on reset, v dd monitor, and temperature sensor ? two on-chip voltage comparators ? 53-port i/o with on-chip power-on reset, v dd monitor, watchdog timer, and clock oscillator, the si102x/3x devices are truly stand-alone system-on-a-chip solutions. the fl ash memory can be reprogrammed even in-circuit, pro - viding non-volatile data storage, and also allowing fi eld up grades of the 8051 firmware. user software has complete control of all peripherals, and may individua lly shut down any or all peripherals for power sav - ings. the on-chip silicon labs 2-wire (c2) development interface allow s non-intrusive (uses no on-chi p resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digita l peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions , allowing in-system debugging with - out occupying package pins. each device is specified for 1.8 to 3.8 v operation over the industrial temperature range (?40 to +85 c). th e po rt i/o and rst pins are tolerant of inpu t signals up to vio + 2.0 v. the si102x/3x devices are avail - able in an 85-pin lga package that is lead-free and rohs-compliant. see ta b l e 2.1 for ordering informa - tion. block diagrams are included in figure 1.1 and figure 1.2 . the transceiver's extremely low re c e ive sensitivity (?121 dbm) coup led with industry leading +13 or +20 dbm output power ensures extended range and improv e d link performance. built-in antenna diversity and support for frequency hopping can be used to fu rther extend range and enhance performance. the advanced radio features including continuous frequ ency coverage from 240?960 mhz in 156 hz or 312 hz steps allow precise tuning control. additional system features such as an automatic wake-up timer, low battery detector, 64 byte tx/rx fifos, automatic packet handling, and preamble detection reduce overall current consumption.
rev. 0.3 27 si102x/3x the transceivers digital receive architecture fe atures a high-performance adc and dsp-based modem which performs demodulation, filter ing, and packet handling for increa sed flexibility and performance. the direct digital transmit modulation and automatic pa po wer ramping ensure precise transmit modulation and reduced spectral spreading, ensuring compliance with global regulations including fcc, etsi, arib, and 802.15.4d.
si102x/3x 28 rev. 0.3 figure 1.1. si102x block diagram figure 1.2. si103x block diagram port 0-1 drivers digital peripherals uart timers 0/1/2/3 pca/ wdt smbus priority crossbar decoder p0.0...p1.7 p2.4...p2.7 p3.0...p6.7 crossbar control port i/o configuration cip-51 8051 controller core 128/64/32/16 kbyte isp flash program memory 256 byte sram sfr bus 8192/4096 byte xram spi 0 analog peripherals comparators + - vbat vbat dcout+ xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset/pmu reset c2d c2ck/rst wake 12-bit 75ksps adc a m u x temp sensor external vref internal vref vdd xtal2 low power 20 mhz oscillator vref gnd cp0, cp0a + - cp1, cp1a enhanced smartclock oscillator xtal3 xtal4 dc/dc buck converter dcen dcin- vreg digital power crc engine lcd charge pump aes engine dma cap p7.0/c2d 32 encoder gnd vdd vreg analog power port 2 drivers port 3-6 drivers port 7 driver 4 16 rf xcvr (240-960 mhz, +20/+13 dbm) 30 mhz pa lna agc digital modem delta sigma modulator digital logic mixer pga adc tx rxp rxn xout xin lcd (4x32) emif pulse counter ezradiopro spi 1 vco port 0-1 drivers digital peripherals uart timers 0/1/2/3 pca/ wdt smbus priority crossbar decoder p0.0...p1.7 p2.4...p2.7 p3.0...p6.7 crossbar control port i/o configuration cip-51 8051 controller core 128/64/32/16 kbyte isp flash program memory 256 byte sram sfr bus 8192/4096 byte xram spi 0 analog peripherals comparators + - vbat vbat dcout+ xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset/pmu reset c2d c2ck/rst wake 12-bit 75ksps adc a m u x temp sensor external vref internal vref vdd xtal2 low power 20 mhz oscillator vref gnd cp0, cp0a + - cp1, cp1a enhanced smartclock oscillator xtal3 xtal4 dc/dc ?buck? converter dcen dcin- vreg digital power crc engine lcd charge pump aes engine dma cap p7.0/c2d 32 encoder gnd vdd vreg analog power port 2 drivers port 3-6 drivers port 7 driver 4 16 rf xcvr (240-960 mhz, +20/+13 dbm) 30 mhz pa lna agc digital modem delta sigma modulator digital logic mixer pga adc tx rxp rxn xout xin emif pulse counter ezradiopro spi 1 vco
rev. 0.3 29 si102x/3x 1.1. typical connection diagram the application shown in figure 1.7 is designed for a system with a tx/r x direct-tie configuration without the use of a tx/rx switch. most lowe r power applications will us e this configuration. a complete direct-tie reference design is available from silic on laboratories app lications support. for applications seeking improved performance in the pr esen ce of multipath fadi ng, antenna diversity can be used. antenna diversity support is integrated in to the ezradiopro transceiver and can improve the system link budget by 8?10 db in the presence of these fading conditions, resulting in substantial range increases. a complete antenna diversity reference desi gn is available from silicon laboratories applica - tions support. figure 1.3. si102x/3x rx/tx direct-tie application example figure 1.4. si102x/3x antenna diversity application example x1 30mhz supply voltage 100n c7 100p c8 c1 l1 l3 l2 c6 c3 c2 1u vdd_rf rxn tx rfp gpio0 gpio1 vr_dig nirq sdn xout gpio2 xin c9 1u l5 c5 c4 l4 l6 si1020/1/2/3 si1030/1/2/3 vdd_mcu px.x 0.1 uf vdd_dig 0.1 uf supply voltage 100 n c7 100 p c8 c1 l1 l3 l2 c6 c3 c2 1 u rxn tx rxp l4 c4 c5 tr & ant-div switch 1 3 2 6 4 5 x1 30 mhz vdd_rf gpio0 gpio1 vr_dig nirq sdn xout gpio2 xin c9 1u si102x si103x vdd_mcu px.x 0.1 uf vdd_dig 0.1 uf
si102x/3x 30 rev. 0.3 1.2. cip-51? microcontroller core 1.2.1. fully 8051 compatible the si102x/3x family utilizes silicon labs' propriet ary cip-51 microcontr oller core. the cip-51 is fully com - patible with the mcs-51? instruction set; standard 803x/8 05x a ssemblers and compilers can be used to develop software. the cip-51 core offers all the peripherals included with a standard 8052. 1.2.2. improved throughput the cip-51 employs a pipelined architecture that grea tly incr eases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all inst ructions except for mul and div take 12 or 24 system clock cycles to execute with a ma ximum system clock of 12-to-24 mhz. by contrast, the cip-51 core exe - cutes 70% of its instructions in one or two system clock cy cles , with only four inst ructions taking more than four system clock cycles. the cip-51 has a total of 109 instructions. the table below shows the total number of instructions that require each execution time. with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. 1.2.3. additional features the si102x/3x soc family includes several key enhancements to the cip-51 core and peripherals to im pr ove performance and ease of use in end applications. the extended interrupt handler provides multiple interrupt sources into the cip-51 allowing numerous ana - log and digital peripherals to interrupt the controller. an in te rrupt driven system requires less intervention by the mcu, giving it more effective throughput. the extra interrupt sources are very useful when building multi-tasking, real-time systems. eight reset sources are available: power-on reset circuitry (por), an on-chip v dd monitor (forces reset when power supply voltage drops below safe leve ls), a watchdog timer, a missing clock detector, smartclock oscillator fail or alarm, a voltage level det ection from comparator0, a forced software reset, an external reset pin, and an illegal flash access prot ection circuit. each reset s ource except for the por, reset input pin, or flash error may be disabled by the user in software. the wdt may be permanently dis - abled in software after a power- on reset during mc u initialization. the internal oscillator factory calibra ted to 24.5 mh z and is accurate to 2% over the full temperature and supply range. the internal oscillator period c an also be adjusted by user fi rmware. an ad ditional 20 mhz low pow er oscillator is also availabl e which facilitates low-po wer operation. an extern al oscillator drive cir - cuit is included, allowing an external crystal, cerami c re sonator, capacitor, rc, or cmos clock source to generate the system clock. if desired, the system cloc k source may be switched on-the-fly between both internal and external oscillator circ uits. an external oscilla tor can also be extremely useful in low power applications, allowing the mcu to run from a slow (pow er saving) source, while pe riodically switching to the fast (up to 25 mhz) internal oscillator as needed. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1
rev. 0.3 31 si102x/3x 1.3. port input/output digital and analog resources are available through 53 i/o pins. port pins are organized as eight byte-wide ports. port pins can be defined as digital or analog i/o. digital i/o pins can be assigned to one of the inter - nal digital resources or used as general purpose i/o (g pio). an alo g i/o pins are used by the internal ana - log resources. p7.0 can be used as gpio and is shar ed with the c2 interface data signal (c2d). see section ?35. c2 interface? on page 533 for more details. the designer has complete control over which digital and a nalog functions are assigned to individual port pins. this resource assignment flexib ility is achieved through the use of a priority crossbar decoder. see section ?27. port input/output? on page 358 for more information on the crossbar. for port i/os configured as push-pu ll o u tputs, current is sourced from th e vio, viorf, or vbat supply pin. port i/os used for analog functions c an operate up to the supply voltage. see section ?27. port input/out - put? on page 358 for more information on port i/o operating mo des a nd the electrical specifications chap - ter for detailed electrical specifications. figure 1.5. port i/o functional block diagram xbr0, xbr1, xbr2, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 port match p0mask, p0mat p1mask, p1mat uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 7 pca 4 cp0 cp1 outputs spi0 spi1 4 (port latches) p0 (p6.0-p6.7) 8 8 p6 p7 (p7.0) 1 pnmdout, pnmdin registers to analog peripherals (adc0, cp0, and cp1 inputs, vref, iref0, agnd) to lcd external interrupts ex0 and ex1 p1 i/o cells p1.0 p1.7 p2 i/o cells p2.0 p2.7 p3 i/o cells p3.0 p3.7 p4 i/o cells p4.0 p4.7 p5 i/o cells p5.0 p5.7 p6 i/o cells p6.0 p6.7 p7 p7.0 8 8 8 8 8 8 8 1 to emif
si102x/3x 32 rev. 0.3 1.4. serial ports the si102x/3x family includes an smbus/i 2 c interface, a full-duplex uart with enhanced baud rate con - figuration, and two enhanced spi interfaces. each of th e se rial buses is fully implemented in hardware and makes extensive use of the cip-51's interrupts, thus requiring very little cpu intervention. 1.5. programmable counter array an on-chip programmable counter/timer array (pca) is included in addition to the four 16-bit general pur - pose counter/timers. the pca consists of a dedicate d 16 -b it counter/timer time base with six programma - ble capture/compare modules. the pca clock is derived fr om one of six sources: the system clock divided by 12, the system clock divided by 4, timer 0 overflow s, an external clock input (eci), the system clock, or the external oscillator clock source divided by 8. each capture/compare module can be configured to oper ate in a va rie ty of modes: edge-triggered capture, software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. addi - tionally, capture/ comp are module 5 offers watchdog timer (wdt ) capabilities. following a system reset, module 5 is configured and enabled in wdt mode. the pca capture/compare module i/o and external clock input may be routed to port i/o via the digital crossbar. figure 1.6. pca block diagram capture/ compare module 1 capture/ compare module 0 capture/ compare module 2 cex1 eci crossbar cex2 cex0 port i/o 16 -bit counter/timer pca clock mux / capture/ compare module 4 capture/ compare module 3 capture/ compare module 5 / wdt cex4 cex5 cex3 8 / /12 0 sysclk sysclk 4 timer overflow eci sysclk external clock
rev. 0.3 33 si102x/3x 1.6. sar adc with 16-bit auto-avera ging accumulator and autonomous low power burst mode the adc0 on si102x/3x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive -app roximation-register (sar) adc with integrated track-and-hold and prog rammable window detector. adc0 also has an autono - mous low power burst mode which can automatically enable adc0, capture and accumulate samples, the n place adc0 in a low power shutdown mode without cpu intervention. it also has a 16-bit accumulator that can automatically oversample and average the adc results. see section ?5.4. 12-bit mode? on page 84 for more details on usin g the adc in 12-bit mode. the adc is fully configurable under software control vi a s pecial function registers. the adc0 operates in single-ended mode and may be configured to measur e various different signals using the analog multi - plexer described in section ?5.7. adc0 analog multiplexer? on page 95 . the voltage reference for the adc is selected as described in section ?5.9. voltage and ground reference options? on page 100 . figure 1.7. adc0 functional block diagram adc0cf amp0gn ad0tm ad08be ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10/12-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int bursten ad0en timer 0 overflow timer 2 overflow timer 3 overflow start conversion 000 ad0busy (w) vdd adc0lth ad0wint 001 010 011 100 cnvstr input window compare logic adc0ltl adc0gth adc0gtl adc0l ain+ from amux0 burst mode logic adc0tk adc0pwr 16-bit accumulator
si102x/3x 34 rev. 0.3 figure 1.8. adc0 multiplexer block diagram 1.7. programmable cu rrent reference (iref0) si102x/3x devices include an on-chi p programmable current reference (sou rce or sink) with two output cur - rent settings: low power mode and high current mode. the maximum current output in low power mode is 63 a (1 a steps) and the maximum current ou tput in hig h current mode is 504 a (8 a steps). 1.8. comparators si102x/3x devices include two on-chi p programmable voltage comparators: comparator 0 (cpt0) which is shown in figure 1.9 ; comparator 1 (cpt1) which is shown in figure 1.10 . the two comparators operate identically but may differ in their ability to be us ed as reset or wake-up sources. see section ?22. reset sources? on page 285 and the section ?19. power management? on page 264 for details on reset sources and low power mode wake-up sources, respec tively . the comparator offers programmable response time a nd hyster esis, an analog input multiplexer, and two outputs that are optionally available at the port pins : a synchronous ?latched? output (cp0, cp1), or an asynchronous ?raw? output (cp0a, cp1a). the asyn chronous cp0a signal is available even when the system clock is not active. this allows the comparator to operate and generate an output when the device is in some low power modes. the comparator inputs may be connected to po rt i/o pin s or to other internal signals. adc0 temp sensor amux vbat adc0mx ad0mx4 ad0mx3 ad0mx2 ad0mx1 am0mx0 ain+ p0.0 p2.6* *p1.7-p2. 6 only available as inputs on 32- pin packages digital supply vdd/dc+ programmable attenuator gain = 0. 5 or 1
rev. 0.3 35 si102x/3x figure 1.9. comparator 0 functional block diagram figure 1.10. comparator 1 functional block diagram vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp0 + px.x cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 rising-edge cp0 falling-edge cp0 interrupt px.x px.x px.x cp0 - (asynchronous) analog input multiplexer vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp1 + px.x cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 cpt0md cp1rie cp1fie cp1md1 cp1md0 cp1 cp1a cp1 rising-edge cp1 falling-edge cp1 interrupt px.x px.x px.x cp1 - (asynchronous) analog input multiplexer
si102x/3x 36 rev. 0.3 2. ordering information all packages are lead -free (rohs compliant). table 2.1. product selection guide ordering part number mips (peak) flash memory (kb) ram (bytes) tx output power (dbm) lcd segments (4-mux) digital port i/os aes 128, 192, 256 encryption smartclock real time clock smbus/i 2 c uart enhanced spi timers (16-bit) pca channels 10/12-bit 300/75 ksps adc channels with internal vref and temp sensor analog comparators package si1020-a-gm 25 128 8448 20 128 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1021-a-gm 25 64 8448 20 128 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1022-a-gm 25 32 8448 20 128 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1023-a-gm 25 16 4352 20 128 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1024-a-gm 25 128 8448 13 128 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1025-a-gm 25 64 8448 13 128 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1026-a-gm 25 32 8448 13 128 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) SI1027-A-GM 25 16 4352 13 128 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1030-a-gm 25 128 8448 20 ? 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1031-a-gm 25 64 8448 20 ? 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1032-a-gm 25 32 8448 20 ? 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1033-a-gm 25 16 4352 20 ? 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1034-a-gm 25 128 8448 13 ? 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1035-a-gm 25 64 8448 13 ? 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1036-a-gm 25 32 8448 13 ? 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8) si1037-a-gm 25 16 4352 13 ? 53 ? ? 1 1 2 4 6 16 2 lga-85 (6x8)
rev. 0.3 37 si102x/3x 3. pinout and p ackage definitions table 3.1. pin definitions for the si102x/3x name pin number type description vbat a43 p in battery supply voltage. must be 1.8 to 3.8 v. vbatdc a44 p in dc0 input voltage. must be 1.8 to 3.8 v. vdc a46 p in p out alternate power supply voltage. must be 1.8 to 3.6 v. this supply volt age must always be ? vbat. software may select this supply voltage to power the digital logic. positive output of the dc-dc converter. a 1 uf to 10 uf ceramic cap a citor is required on this pin when using the dc-dc converter. this pin can supply power to external devices when the dc-dc converter is enabled. gnddc a45 p in dc-dc converter return current path . this pin is t ypically tied to the ground plane. gnd d2 g required ground. gnd d6 g required ground. gnd b16 g required ground. gnd b17 g required ground. gnd a32 g required ground. gnd b28 g required ground. ind b27 p in dc-dc inductor pin. this pin requires a 560 nh inductor to vdc if the dc- d c converter is used. vio b26 p in i/o power supply for p0.0?p1.4 and p2.4?p7.0 pins. this supply voltage must always be ? vbat. viorf b29 p in i/o power supply for p1.5?p2.3 pi ns. this supply v oltage must always be ? vbat rst / c2ck a47 d i/o d i/o device reset. open-drain output of internal por or v dd monitor. an external source can initiate a system reset by driving this pin low for at least 15 s. a 1 k? to 5 k ? pullup to v dd is recom - mended. see reset sources section for a complete description. clock signal for the c2 debug interface. p7.0/ c2d a48 d i/o d i/o port 7.0. this pin can only be used a s gpio. the crossbar cannot route signals to this pin and it cannot be configured as an analog input. see port i/o section for a complete description. bi-directional data signal for the c2 debug interface.
si102x/3x 38 rev. 0.3 vlcd a29 p i/o lcd power supply. this pin requires a 10 f capacitor to stabilize the charge pump. p0.0 v ref a42 d i/o or a in a in a out port 0.0. see port i/o section for a co mplete description. external v ref input. internal v ref output. external v ref decoupling capacitors are recommended. see adc0 section for details. p0.1 agnd a41 d i/o or a in g port 0.1. see port i/o section for a co mplete description. optional analog ground. see adc0 section for details. p0.2 xtal1 a40 d i/o or a in a in port 0.2. see port i/o section for a co mplete description. external clock input. this pin is th e ex ternal oscillator return for a crystal or resonator. see oscillator section. p0.3 xtal2 a39 d i/o or a in a out d in a in port 0.3. see port i/o section for a co mplete description. external clock output. this pin is the excitation driver for an exter nal cryst al or resonator. external clock input. this pin is the extern al clock input in exter - nal cmos clock mode. external clock input. this pin is the extern al clock input in capaci - tor or rc oscillator configurations. see oscillator section for complete det ails. p0.4 tx a38 d i/o or a in d out port 0.4. see port i/o section for a co mplete description. uart tx pin. see port i/o section. p0.5 rx a37 d i/o or a in d in port 0.5. see port i/o section for a co mplete description. uart rx pin. see port i/o section. p0.6 cnvstr a36 d i/o or a in d in port 0.6. see port i/o section for a co mplete description. external convert start input for adc0. see adc0 section for a comp lete de scription. table 3.1. pin definitions for the si102x/3x (continued) name pin number type description
rev. 0.3 39 si102x/3x p0.7 iref0 a35 d i/o or a in a out port 0.7. see port i/o section for a co mplete description. iref0 output. see iref sectio n for c omplete description. p1.0 pc0 a34 d i/o or a in d i/o port 1.0. see port i/o section fo r a co mplete description. may also be used as sck for spi0. pulse counter 0. p1.1 pc1 a33 d i/o or a in d i/o port 1.1. see port i/o section for a co mplete description. may also be used as miso for spi0. pulse counter 1. p1.2 xtal3 a31 d i/o or a in a in port 1.2. see port i/o section for a co mplete description. may also be used as mosi for spi0. smartclock oscillator crystal input. p1.3 xtal4 a30 d i/o or a in a out port 1.3. see port i/o section for a co mplete description. may also be used as nss for spi0. smartclock oscillator crystal output. p1.4 a28 d i/o or a in port 1.4. see port i/o section for a co mplete description. p1.5 a27 d i/o or a in port 1.5. see port i/o section for a co mplete description. p1.6 a26 d i/o or a in port 1.6. see port i/o section for a co mplete description. p1.7 d7 d i/o or a in port 1.7. see port i/o section for a co mplete description. p2.4 com0 a12 d i/o or a in a o port 2.4. see port i/o section for a co mplete description. lcd common pin 0 (b ackplane driver) p2.5 com1 b10 d i/o or a in a o port 2.5. see port i/o section for a co mplete description. lcd common pin 1 (b ackplane driver) p2.6 com2 a11 d i/o or a in a o port 2.6. see port i/o section for a co mplete description. lcd common pin 2 (b ackplane driver) table 3.1. pin definitions for the si102x/3x (continued) name pin number type description
si102x/3x 40 rev. 0.3 p2.7 com2 a10 d i/o or a in a o port 2.7. see port i/o section for a co mplete description. lcd common pin 3 (b ackplane driver) p3.0 lcd0 a9 d i/o or a in a o port 3.0. see port i/o section for a co mplete description. lcd segment pin 0 p3.1 lcd1 a8 d i/o or a in a o port 3.1. see port i/o section for a co mplete description. lcd segment pin 1 p3.2 lcd2 a7 d i/o or a in a o port 3.2. see port i/o section for a co mplete description. lcd segment pin 2 p3.3 lcd3 a6 d i/o or a in a o port 3.3. see port i/o section for a co mplete description. lcd segment pin 3 p3.4 lcd4 a5 d i/o or a in a o port 3.4. see port i/o section for a co mplete description. lcd segment pin 4 p3.5 lcd5 a4 d i/o or a in a o port 3.5. see port i/o section for a co mplete description. lcd segment pin 5 p3.6 lcd6 a3 d i/o or a in a o port 3.6. see port i/o section for a co mplete description. lcd segment pin 6 p3.7 lcd7 a2 d i/o or a in a o port 3.7. see port i/o section for a co mplete description. lcd segment pin 7 p4.0 lcd8 a1 d i/o or a in a o port 4.0. see port i/o section for a co mplete description. lcd segment pin 8 table 3.1. pin definitions for the si102x/3x (continued) name pin number type description
rev. 0.3 41 si102x/3x p4.1 lcd9 b25 d i/o or a in a o port 4.1. see port i/o section for a co mplete description. lcd segment pin 9 p4.2 lcd10 b24 d i/o or a in a o port 4.2. see port i/o section for a co mplete description. lcd segment pin 10 p4.3 lcd11 b23 d i/o or a in a o port 4.3. see port i/o section for a co mplete description. lcd segment pin 11 p4.4 lcd12 d4/d8 d i/o or a in a o port 4.4. see port i/o section for a co mplete description. lcd segment pin 12 p4.5 lcd13 b22 d i/o or a in a o port 4.5. see port i/o section for a co mplete description. lcd segment pin 13 p4.6 lcd14 b21 d i/o or a in a o port 4.6. see port i/o section for a co mplete description. lcd segment pin 14 p4.7 lcd15 b20 d i/o or a in a o port 4.7. see port i/o section for a co mplete description. lcd segment pin 15 p5.0 lcd16 b19 d i/o or a in a o port 5.0. see port i/o section for a co mplete description. lcd segment pin 16 p5.1 lcd17 b18 d i/o or a in a o port 5.1. see port i/o section for a co mplete description. lcd segment pin 17 p5.2 lcd18 b15 d i/o or a in a o port 5.2. see port i/o section for a co mplete description. lcd segment pin 18 table 3.1. pin definitions for the si102x/3x (continued) name pin number type description
si102x/3x 42 rev. 0.3 p5.3 lcd19 b14 d i/o or a in a o port 5.3. see port i/o section for a co mplete description. lcd segment pin 19 p5.4 lcd20 b13 d i/o or a in a o port 5.4. see port i/o section for a co mplete description. lcd segment pin 20 p5.5 lcd21 b12 d i/o or a in a o port 5.5. see port i/o section for a co mplete description. lcd segment pin 21 p5.6 lcd22 b9 d i/o or a in a o port 5.6. see port i/o section for a co mplete description. lcd segment pin 22 p5.7 lcd23 b8 d i/o or a in a o port 5.7. see port i/o section for a co mplete description. lcd segment pin 23 p6.0 lcd24 b7 d i/o or a in a o port 6.0. see port i/o section for a co mplete description. lcd segment pin 24 p6.1 lcd25 b6 d i/o or a in a o port 6.1. see port i/o section for a co mplete description. lcd segment pin 25 p6.2 lcd26 b5 d i/o or a in a o port 6.2. see port i/o section for a co mplete description. lcd segment pin 26 p6.3 lcd27 b4 d i/o or a in a o port 6.3. see port i/o section for a co mplete description. lcd segment pin 27 p6.4 lcd28 b3 d i/o or a in a o port 6.4. see port i/o section for a co mplete description. lcd segment pin 28 table 3.1. pin definitions for the si102x/3x (continued) name pin number type description
rev. 0.3 43 si102x/3x p6.5 lcd29 b2 d i/o or a in a o port 6.5. see port i/o section for a co mplete description. lcd segment pin 29 p6.6 lcd30 b1 d i/o or a in a o port 6.6. see port i/o section for a co mplete description. lcd segment pin 30 p6.7 lcd31 d1/d5 d i/o or a in a o port 6.7. see port i/o section for a co mplete description. lcd segment pin 31 vdd_rf a17 p in +1.8 to +3.6 v supply voltage input to all analog +1.7 v regulators. the recommended vd d s upply voltage is +3.3 v tx a18 a o transmit output pin. the pa output is an open-drain connection so the l-c matc h must supply vdd (+3.3 vdc nominal) to this pin. rxp a19 a i differential rf input pins of th e l na. see application schematic for example matching network. rxn a20 a i nc a16 ? no connect. not connected internally to any circuitry. ant_a a21 d o extra antenna or tr switch control to be used if more gpio are re qu ired. pin is a hardwired version of gpio setting 11000, antenna 2 and can be manually controlled by the antdiv[2:0] bits in register 08h. see register description of 08h. gpio_0 a22 d i/o general purpose digital i/o that may be configured through the re gisters to perform various functions including: microcontroller clock output, fifo status, por, wake-up timer, low battery detect, t/r switch, antdiversity control, etc. see the spi gpio configuration registers, addre ss 0bh, 0ch, and 0dh for more information. gpio_1 a23 d i/o gpio_2 a24 d i/o vr_dig d3 p out regulated output voltage of the digital 1.7 v regulator. a 1 f de co upling capacitor is required. vdd_dig a25 p in +1.8 to +3.6 v supply voltage input to the digital +1.7 v ? regulator. the recommended vdd supply voltage is +3.3 v. nirq b11 d o general microcontroller interrupt s t atus output. when the ezra - diopro transceiver exhibits anyone of the interrupt events, the nirq pin will be set low . please see the control logic registers section for more information on the interrupt events. the micro - controller can then determine the state of the interrupt by reading a cor r esponding spi interrupt stat us registers, address 03h and 04h. no external resistor pull-up is required, but it may be desir - able if multiple interrupt lines are connected. table 3.1. pin definitions for the si102x/3x (continued) name pin number type description
si102x/3x 44 rev. 0.3 xout a13 d i or a i/o crystal oscillator outp ut/external reference input. connect to an exter nal 30 mhz crystal or to an external source. if using an exter - nal source with no crystal, then dc coupling with a nominal 0.8 vdc level is recommended with a minimum amplitude of 70 0 mvpp. xin a14 d o or a i/o crystal oscillator input. co n nect to an external 30 mhz crystal or leav e floating when driving with an external source on xout. sdn a15 d i shutdown input pin. sdn should be low in all modes except shut - down mode. when sdn is high, th e radio will be completely shut down, and the contents of the registers will be lost. table 3.1. pin definitions for the si102x/3x (continued) name pin number type description
rev. 0.3 45 si102x/3x figure 3.1. lga-85 pinout diagram (top view) d1 d2 d4 d3 d6 d5 d8 d7 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a48a47a46a45a44a43a42a41a40a39 a38 a37 a36 a35 a34 a33 a32 a31 a30 a29 a28 a27 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 b11 b10 b8 b7 b6 b5 b4 b3 b2 b1 b29b28b27b26b25b24b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b9 si1020-a-gm top view gnd xin xout nirq sdn nc vdd_rf tx rxp rxn ant_a gpio_0 gpio_1 gpio_2 p5.5/lcd21 p1.6/int01/adc10 p5.4/lcd20 p5.3/lcd19 p5.2/lcd18 p5.1/lcd17 p5.0/lcd16 p4.7/lcd15 p4.6/lcd14 p4.5/lcd13 p2.4/com0 p2.5/com1 p2.6/com2 p5.6/lcd22 p2.7/com3 p5.7/lcd23 p3.0/lcd0 p6.0/lcd24 p3.1/lcd1 p6.1/lcd25 p6.2/lcd26 p6.3/lcd27 p6.4/lcd28 p6.5/lcd29 p6.6/lcd30 p4.0/lcd8 p3.7/lcd7 p3.6/lcd6 p3.5/lcd5 p3.4/lcd4 p3.3/lcd3 p3.2/lcd2 p6.7/lcd31 p7.0/c2d rstb/c2ck viorf vdc gnd gnddc ind vbatdc vio vbat p4.1/lcd9 p0.0/vref/adc0 p4.2/lcd10 p0.1/agnd/adc1 p4.3/lcd11 p0.2/xtal1/adc2 p0.3/xtal2/adc3 vdd_dig p1.5/int01/adc9 p1.4/adc8 p0.5/rx/adc5 p0.6/cnvstr/adc6 p0.7/iref/adc7 p1.0/pc0 p1.1/pc1 p1.2/xtal3 p1.3/xtal4 vlcd p0.4/tx/adc4 p4.4/lcd12 vr_dig p1.7/adc11 gnd gnd gnd
si102x/3x 46 rev. 0.3 3.1. lga-85 package specifications 3.1.1. package drawing figure 3.2. lga-85 package drawing table 3.2. lga-85 package dimensions dimension min nom max a 0.74 0.84 0.94 b 0.25 0.30 0.35 d 6.00 bsc. d1 ? 2.40 ? d2 ? 5.50 ? d3 ? 3.00 ? e 0.50 bsc. e 8.00 bsc. notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimen sioning and tolerancing per ansi y14.5m-1994. 3. recomme nd ed card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ? (bxb) pi n a 1 id d2 e3 e2 d3 d1 e1 (3. 385) e a d e 85x bxb ddd cab
rev. 0.3 47 si102x/3x e1 ? 5.60 ? e2 ? 5.00 ? e3 ? 7.50 ? l1 ? 0.10 ? aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 table 3.2. lga-85 package dimensions (continued) dimension min nom max notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si102x/3x 48 rev. 0.3 3.1.2. land pattern figure 3.3. lga-85 land pattern table 3.3. lga-85 land pattern dimensions symbol max (mm) c1 5.50 c2 7.50 e 0.50 f 0.35 p1 2.40 p2 5.60 notes: general 1. a ll feature sizes shown are at maximum material c ondition (mmc) and a card fabrication tolerance of 0.05mm is assumed. 2. dimen sioning and tolerancing is per t he ansi y14.5m-1994 specification. 3. this la nd pattern design is based on the ipc-7351 guidelines. solder mask design 4. a ll metal pads are to be non-solder mask def ined (n smd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro-polished stencil w ith trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness s hould be 0. 125mm (5 mils) . 7. the r atio of stencil aperture to land pad size should be 1:1 f or all perimeter pins. 8. a 2x3 array of 0.72x1.45mm openings on 1.77 mm pitch should be used for the center ground pad. card as sembly 9. a no-clean, type-3 solder paste is recommended. 10. the r ecommended card reflow profile is per t he jedec/ipc j-std-020 specification for small b ody components. ? c1 c2 p1 p2 (3.385) detai l "a" (f x f) f x f
rev. 0.3 49 si102x/3x 3.1.3. soldering guidelines 3.1.3.1. solder mask design all metal pads are to be non-solder mask defined (n smd). clearance between the solder mask and the metal pad is to be 60 ? m min imum, all the way around the pad. 3. 1.3.2. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. a 2x3 array of 0.72x1.45 mm openings on 1.77 mm pitch should be used for the center ground pad. opening size may be reduced as needed to adjust ratio of solder on center ground pad to solder of signal pins. excessive solder on center pad may cause opens on signal pins. 3.1.3.3. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per t he jedec/ipc j-std-020 spec ification for small body components (>245 c for >20 seconds at peak).
si102x/3x 50 rev. 0.3 4. electrical characteristics throughout the mcu electrical characteristics chapter: ? ?vdd? refers to the vbat or vbatdc supply voltage. ? ?vio? refers to the vio or viorf supply voltage. 4.1. absolute m aximum specifications table 4.1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any port i/o pin or rst with respect to gnd ?0.3 ? vio + 2 v voltage on vdd with respect to gnd ?0.3 ? 4.0 v maximum total current through vdd or gnd ?? 500ma maximum current through rst or any port pin ?? 100ma maximum total current through all port pins ?? 200ma note: stresses above those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the devices at those or any other condit ions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
rev. 0.3 51 si102x/3x 4.2. mcu electri cal characteristics table 4.2. global electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units supply voltage (v dd ) 1.8 3.8 v mini mum ram data ? retention voltage 1 not in sleep mode in sleep mode ? ? 1.4 0.3 ? 0. 5 v sysclk (system clock) 2 0?25mhz t sysh (sysclk high time) 18 ? ? ns t sysl (sysclk low time) 18 ? ? ns specified operating ? temperature range ?40 ? +85 c table 4.3. digital supply current at vbat pin with dc-dc converter enabled ?40 to +85 c, vbat = 3.6v, vdc = 1.9v, 24.5 mhz system clock unless otherwise specified. parameter conditions min typ max units digital supply current?cpu active ( normal mode, fetching instructions from flash, no external load) i bat 1,2,3 v bat = 3.0 v ?4.5? ma v bat = 3.3 v ?4.3 ? ma v bat = 3.6 v ?4.2? ma digita l supply current?cpu inactive (sleep mode, sourcing current to external device) i bat 1 sourcing 9 ma to external device ?6.5? ma sourcing 19 ma to external device ?13? ma notes: 1. based on device characterization data; not production tested. 2. dig ital supply current depends upon the particular code being executed. the values in this table are obtained with the cpu executing a mix of instructions in two loops: djnz r1 , $, followed by a loop that accesses an sfr, and moves data around using the cpu (between accumulator and b-register). the supply current will vary slightly based on the physical location of this code in flash. as descr ibed in the flash memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to minimize flash accesses and power consumption. 3. includ es oscillator and regulator supply current.
si102x/3x 52 rev. 0.3 table 4.4. digital supply current with dc-dc converter disabled ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units digital supply current - active mode, no clock gating (pc lkact=0x0f) (cpu active, fetching instructions from flash) i dd 3, 4 v dd = 1.8?3.8 v, f = 24.5 mhz (includes precision oscillator current) ?4 .96.2 ma v dd = 1.8?3.8 v, f = 20 mhz (includes low power oscillator current) ?3.9 ? ma v dd = 1.8 v, f = 1 mhz v dd = 3.8 v, f = 1 mhz (includes external oscillator/gpio current) ? ? 175 190 ? ? a a v dd = 1.8?3.8 v, f = 32.768 khz (includes smar tclock oscillator current) ?85? a i dd frequency ? sensitivity 1, 3 v dd = 1.8?3.8 v, t = 25 c ? 183 ? a/mhz digital supply current - acti v e mode, all peripharal clocks disabled (pclkact=0x00) (cpu active, fetching instructions from flash) i dd 3, 4 v dd = 1.8?3.8 v, f = 24.5 mhz (includes precision oscillator current) ?3 .9 -- ma v dd = 1.8?3.8 v, f = 20 mhz (includes low power oscillator current) ?3.1? ma v dd = 1.8 v, f = 1 mhz v dd = 3.8 v, f = 1 mhz (includes external oscillator/gpio current) ? ? 165 180 ? ? a a i dd frequency ? sensitivity 1, 3 v dd = 1.8?3.8 v, t = 25 c ? tbd ? a/mhz digit a l supply current?idle mode ? (cpu inactive, not fetching instructions from flash) i dd 4 v dd = 1.8?3.8 v, f = 24.5 mhz (includes precision oscillator current) ?3 .5? ma v dd = 1.8?3.8 v, f = 20 mhz (includes low power oscillator current) ?2.6? ma v dd = 1.8 v, f = 1 mhz v dd = 3.8 v, f = 1 mhz (includes external oscillator/gpio current) ? ? 340 360 ? ? a a v dd = 1.8?3.8 v, f = 32.768 khz (includes smar tclock oscillator current) ? 230 5 ?a i dd frequency sensitivity 1 v dd = 1.8?3.8 v, t = 25 c ? 135 ? a/mhz
rev. 0.3 53 si102x/3x digital supply current? low power idle mode, all peripheral clocks enabled (pclken = 0x0f) (cpu inactive, not fetching instructions from flash) i dd 4, 6 v dd = 1.8?3.8 v, f = 24.5 mhz (includes precision oscillator current) ?1 .51.9 ma v dd = 1.8?3.8 v, f = 20 mhz (includes low power oscillator current) ?1.07? ma v dd = 1.8 v, f = 1 mhz v dd = 3.8 v, f = 1 mhz (includes external oscillator/gpio current) ? ? 270 280 ? ? a a v dd = 1.8?3.8 v, f = 32.768 khz (includes smar tclock oscillator current) ? 232 5 ?a i dd frequency sensitivity 1 v dd = 1.8?3.8 v, t = 25 c ? 47 5 ?a/mhz digital supply current? low power idle mode, a ll peripheral clocks disabled (pclken = 0x00) ? (cpu inactive, not fetching instructions from flash) i dd 4, 7 v dd = 1.8?3.8 v, f = 24.5 mhz (includes precision oscillator current) ? 620 tbd a v dd = 1.8?3.8 v, f = 20 mhz (includes low power oscillator current) ? 340 ? a v dd = 1.8 v, f = 1 mhz v dd = 3.8 v, f = 1 mhz (includes external oscillator/gpio current) ? ? tbd tbd ? ? a a i dd frequency sensitivity 1 v dd = 1.8?3.8 v, t = 25 c ? 11 5 ?a/mhz digital supply current?suspend mode digital supply current ? (suspend mode) v dd = 1.8 v v dd = 3.8 v ? ? 77 84 ? ? a table 4.4. digital supply current with dc-dc converter disabled (continued) ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units
si102x/3x 54 rev. 0.3 digital supply current?sleep mode (lcd enabled, rtc enabled) digital supply current ? (sleep mode, smartclock running, internal lfo, lcd contrast mode 1, charge pump disabled, 60 hz refresh rate, driving 32 seg- ment pins w/ no load) 1.8 v, t = 25 c, static lcd 3.0 v, t = 25 c, static lcd 3.8 v, t = 25 c, static lcd ? ? ? 0.4 0.6 0.8 ? ? ? a 1.8 v, t = 25 c, 2-mux lcd 3.0 v, t = 25 c, 2-mux lcd 3.8 v, t = 25 c, 2-mux lcd ? ? ? 0.9 1.1 1.3 ? ? ? a 1.8 v, t = 25 c, 4-mux lcd 3.0 v, t = 25 c, 4-mux lcd 3.8 v, t = 25 c, 4-mux lcd ? ? ? 1.2 1.4 1.6 ? ? ? a digital supply current ? (sleep mode, smartclock running, 32.768 khz crys- tal, lcd contrast mode 1, charge pump disabled, 60 hz refresh rate, driving 32 segment pins w/ no load) 1.8 v, t = 25 c, static lcd 3.0 v, t = 25 c, static lcd 3.8 v, t = 25 c, static lcd ? ? ? 0.8 1.1 1.4 ? ? ? a 1.8 v, t = 25 c, 2-mux lcd 3.0 v, t = 25 c, 2-mux lcd 3.8 v, t = 25 c, 2-mux lcd ? ? ? 1.2 1.7 2.0 ? ? ? a 1.8 v, t = 25 c, 4-mux lcd 3.0 v, t = 25 c, 4-mux lcd 3.8 v, t = 25 c, 4-mux lcd ? ? ? 1.4 1.8 2.1 ? ? ? a digital supply current ? (sleep mode, smartclock running, internal lfo, lcd contrast mode 3 (2.7 v), charge pump enabled, 60 hz refresh rate, driving 32 segment pins w/ no load) 1.8 v, t = 25 c, static lcd 1.8 v, t = 25 c, 2-mux lcd 1.8 v, t = 25 c, 3-mux lcd 1.8 v, t = 25 c, 4-mux lcd ? ? ? ? 1.2 1.6 1.8 2.0 ? ? ? ? a digital supply current ? (sleep mode, smartclock running, 32.768 khz crys- tal, lcd contrast mode 3 (2.7 v), charge pump enabled, 60 hz refresh rate, driving 32 segment pins w/ no load) 1.8 v, t = 25 c, static lcd 1.8 v, t = 25 c, 2-mux lcd 1.8 v, t = 25 c, 3-mux lcd 1.8 v, t = 25 c, 4-mux lcd ? ? ? ? 1.3 1.8 1.8 2.0 ? ? ? ? a table 4.4. digital supply current with dc-dc converter disabled (continued) ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units
rev. 0.3 55 si102x/3x digital supply current?sleep mode (lcd disabled, rtc enabled) digital supply current ? (sleep mode, smartclock running, 32.768 khz crystal) 1.8 v, t = 25 c 3.0 v, t = 25 c 3.8 v, t = 25 c 1.8 v, t = 85 c 3.0 v, t = 85 c 3.8 v, t = 85 c (includes smartclock oscillator and v bat supply monitor) ? ? ? ? ? ? 0.40 0.60 0.70 1.56 2.38 2.79 ? ? ? ? ? ? a digital supply current ? (sleep mode, smartclock running, internal lfo) 1.8 v, t = 25 c 3.0 v, t = 25 c 3.8 v, t = 25 c 1.8 v, t = 85 c 3.0 v, t = 85 c 3.8 v, t = 85 c (includes smartclock oscillator and v bat supply monitor) ? ? ? ? ? ? 0.20 0.30 0.40 1.30 2.06 2.41 ? ? ? ? ? ? a digital supply current?sleep mode (lcd disabled, rtc disabled) digital supply current ? (sleep mode) 1.8 v, t = 25 c 3.0 v, t = 25 c 3.8 v, t = 25 c 1.8 v, t = 85 c 3.0 v, t = 85 c 3.8 v, t = 85 c (includes por supply monitor) ? ? ? ? ? ? 0.05 0.07 0.11 1.13 1.83 2.25 ? ? ? ? ? ? a digital supply current (sleep mode, vbat supply monitor disabled) 1.8 v, t = 25 c 3.0 v, t = 25 c 3.8 v, t = 25 c 1.8 v, t = 85 c 3.0 v, t = 85 c 3.8 v, t = 85 c ? ? ? ? ? ? 0.01 0.02 0.03 tbd tbd tbd ? ? ? ? ? ? a notes: 1. based on device characterization data; not production tested. 2. sysclk m u st be at least 32 khz to enable debugging. 3. acti ve current measure using typical code loop - digi t al supply current depends upon the particular code being executed. digital supply current depends on the particular code bei ng executed. the values in this table are obtained with the cpu executing a mix of instructions in two loops: djnz r1, $, followed by a loop that accesses an sfr, and moves data around using th e cpu (between accumulator and b-register). the supply current will vary slightly based on the physical loca tion of this code in flash. as described in the flash memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to minimize flash accesses and power consumption. 4. includ es oscillator and regulator supply current. 5. usin g smartclock osillator with external 32.768 khz cm os clock. does not inclu de crystal bias current. 6. low -power idle mode current measured with clkm ode = 0x0 4, pcon = 0x01, and pclken = 0x0f. 7. low-power idle mode current measured with clkm ode = 0x0 4, pcon = 0x01, and pclken = 0x00. table 4.4. digital supply current with dc-dc converter disabled (continued) ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units
si102x/3x 56 rev. 0.3 figure 4.1. frequency sensitivity (external cmos clock, 25 c) 0 1 2 3 4 5 6 7 0 5 10 15 20 25 30 i dd (ma) frequency (mhz) active idle lp idle (pclken=0x00) lp idle (pclken=0x0f)
rev. 0.3 57 si102x/3x table 4.5. port i/o dc electrical characteristics v io = 1.8 to 3.8 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage high drive strength, pndrv.n = 1 ioh = ?3 ma, port i/o push-pull ioh = ?10 a, port i/o push-pull ioh = ?10 ma, port i/o push-pull low drive strength, pndrv.n = 0 ioh = ?1 ma, port i/o push-pull ioh = ?10 a, port i/o push-pull ioh = ?3 ma, port i/o push-pull v io ? 0.7 v io ? 0.1 v io ? 0.7 v io ? 0.1 ? ? ? see chart ? ? see chart ? ? ? ? ? v output low voltage high drive strength, pndrv.n = 1 i ol = 8.5 ma i ol = 10 a i ol = 25 ma low drive strength, pndrv.n = 0 i ol = 1.4 ma i ol = 10 a i ol = 4 ma ? ? ? ? ? ? ? ? see chart ? ? see chart 0.6 0.1 ? 0.6 0.1 ? v input high voltage v dd = 2.0 to 3.8 v v io ? 0.6 ?? v v dd = 1.8 to 2.0 v 0.7 x v io ?? v input low voltage v dd = 2.0 to 3.8 v ? ? 0.6 v v dd = 1.8 to 2.0 v ?? 0.3 x v io v input leakage ? current w e ak pullup off weak pullup on, v in = 0 v, v dd = 1.8 v weak pullup on, vin = 0 v, v dd = 3.8 v ? ? ? ? 4 20 1 ? 35 a
si102x/3x 58 rev. 0.3 figure 4.2. typical voh curves, 1.8?3.8 v typical voh (high drive mode) 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 0 5 10 15 20 25 30 35 40 45 50 load current (ma) voltage vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v typical voh (low drive mode) 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 0123456789101112131415 load current (ma) voltage vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v
rev. 0.3 59 si102x/3x figure 4.3. typical vol curves, 1.8?3.8 v typical vol (high drive mode) 0 0.3 0.6 0.9 1.2 1.5 1.8 -80 -70 -60 -50 -40 -30 -20 -10 0 load current (ma) voltage vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v typical vol (low drive mode) 0 0.3 0.6 0.9 1.2 1.5 1.8 -10-9-8-7-6-5-4-3-2-1 0 load current (ma) voltage vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v
si102x/3x 60 rev. 0.3 table 4.6. reset electrical characteristics v dd = 1.8 to 3.8 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units rst output low voltage i ol = 1.4 ma, ??0.6 v rst input high voltage v dd = 2.0 to 3.8 v v dd ? 0.6 ?? v v dd = 1.8 to 2.0 v 0.7 x v dd ?? v rst input low voltage v dd = 2.0 to 3.8 v ??0.6 v v dd = 1.8 to 2.0 v ?? 0.3 x v dd v rst input pullup current rst = 0.0 v, vdd = 1. 8 v rst = 0.0 v, vdd = 3. 8 v ? ? 4 20 ? 35 a vdd m o nitor threshold (v rst ) early warning reset trigger ( a ll power modes except sleep) 1.8 1.7 1.85 1.75 1. 9 1. 8 v vbat ramp time for power on vbat ramp from 0?1.8 v ?? 3 ms por mo nitor threshold (v por ) brownout condition (vdd falling) recovery from brownout (vdd rising) 0.45 ? 0.7 1.75 1.0 ? v missing clock detector ? timeout time from last system clock rising edge to reset initiation 100 650 1000 s m i nimum system clock w/ missing clock detector enabled system clock frequency which triggers a mis s ing clock detector timeout ? 7 10 khz reset t i me delay delay between release of any reset sou r ce and code execution at location 0x0000 ?10? s minimum rst low time to generate a system reset 15 ? ? s digital/analog monitor turn-on time ? 300 ? ns digital mo nitor supply ? current ?14? a ana l og monitor supply ? current ?14? a
rev. 0.3 61 si102x/3x table 4.7. power management electrical specifications v dd = 1.8 to 3.8 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units idle mode wake-up time 2 ? 3 sysclks suspend mode wake-up time clkdiv = 0x00 ? 400 ? ns low power or precision osc. sleep mode wake-up time ? 2 ? s table 4.8. flash electrical characteristics v dd = 1.8 to 3.8 v, ?40 to +85 c unless otherwise specified., parameter conditions min typ max units flash size si1020/24/30/34 131072 ? ? bytes si1021/25/31/35 65536 ? ? bytes si1022/26/32/36 32768 ? ? bytes si1023/27/33/37 16384 ? ? bytes endurance 20 k 100k ? er ase/w rite cycles erase cycle time 28 32 36 ms w r ite cycle time 57 64 71 s table 4.9. internal precision oscillator electrical characteristics v dd = 1.8 to 3.8 v; t a = ?40 to +85 c unless otherwise specified; us ing factory-calibrated settings. parameter conditions min typ max units oscillator frequency ?40 to +85 c, v dd = 1.8?3.8 v 24 24.5 25 mhz os cillator supply current ? (from v dd ) 25 c; includes bias current of 50 a typical ?300*? a *note: does not include clock divider or clock tree supply current. table 4.10. internal low-power oscillator electrical characteristics v dd = 1.8 to 3.8 v; t a = ?40 to +85 c unless otherwise specified; us ing factory-calibrated settings. parameter conditions min typ max units oscillator frequency ?40 to +85 c, v dd = 1.8?3.8 v 18 20 22 mhz os cillator supply current ? (from v dd ) 25 c no separate bias current re qu ired ?100*? a *note: does not include clock divider or clock tree supply current.
si102x/3x 62 rev. 0.3 table 4.11. smartclock characteristics v dd = 1.8 to 3.8 v; t a = ?40 to +85 c unless otherwise specified; us ing factory-calibrated settings. parameter conditions min typ max units oscillator frequency (lfo) 13.1 16.4 19.7 khz table 4.12. adc0 electrical characteristics v dd = 1.8 to 3.8 v, vref = 1.65 v (refsl[1:0] = 11), ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 12-bit mode 10-bit mode 12 10 bits integral nonlinearity 12-bit mode 1 10-bit mode ? ? 1 0.5 3 1 lsb differential nonlinearity (guaranteed monotonic) 12-bit mode 1 10-bit mode ? ? 0.8 0.5 2 1 lsb offset error 12-bit mode 10-bit mode ? ? <1 <1 3 3 lsb full scale error 12-bit mode 2 10-bit mode ? ? 1 1 4 2.5 lsb dynamic performance (10 khz sine-wave single-ended input, 1 db below full scale, maximum sampling rate) signal-to-noise plus distortion 3 12-bit mode 10-bit mode 62 54 65 58 ? ? db signal-to-distortion 3 12-bit mode 10-bit mode ? ? 76 73 ? ? db spurious-free dynamic range 3 12-bit mode 10-bit mode ? ? 82 75 ? ? db conversion rate sar conversion clock normal power mode low power mode ? ? ? ? 8.33 4.4 mhz conversion time in sar clocks 10-bit mode 8-bit mode 13 11 ? ? ? ? clocks track/hold acquisition time initial acquisition subsequent acquisitions (dc in put, bur st mode) 1.5 1.1 ? ? ? ? us throughput rate 12-bit mode 10-bit mode ? ? ? ? 75 300 ksps 1. inl and dnl specifications for 12-bit mode do not include the first or last four adc codes. 2. the maximum code in 12-bit mode is 0xfffc. the full scale error is referenced from the maximum code. 3. performance in 8-bit mode is similar to 10-bit mode.
rev. 0.3 63 si102x/3x analog inputs adc input voltage range single ended (ain+ ? gnd) 0 ? vref v absolute pin voltage with respect to g nd sing le ended 0 ? vdd v sampling capacitance 1x gain 0.5x gain ? 16 13 ? pf input multiplexer impedance ? 5 ? k? power specifications power supply current ? (v dd supplied to adc0) normal power mode: conversion mode (300 ksps) tracking mode (0 ksps) low power mode: conversion mode (150 ksps) tracking mode (0 ksps) ? ? ? ? 650 740 370 400 ? ? ? ? a power supply rejection internal high speed vref external vref ? ? 67 74 ? ? db table 4.13. temperature sensor electrical characteristics v dd = 1.8 to 3.8 v, ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units linearity ? 1 ? c slope ? 3.40 ? mv/c slope error* ? 40 ? v/c offset temp = 25 c ? 1025 ? mv offset error* temp = 25 c ? 18 ? mv temperature sensor turn-on ti m e ? 1.7 ? s supply current ? 35 ? a *note: represents one standard deviation from the mean. table 4.12. adc0 electrical characteristics (continued) v dd = 1.8 to 3.8 v, vref = 1.65 v (refsl[1:0] = 11), ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units 1. inl and dnl specifications for 12-bit mode do not include the first or last four adc codes. 2. the maximum code in 12-bit mode is 0xfffc. the full scale error is referenced from the maximum code. 3. performance in 8-bit mode is similar to 10-bit mode.
si102x/3x 64 rev. 0.3 table 4.14. voltage reference electrical characteristics v dd = 1.8 to 3.8 v, ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units internal high-speed reference (refsl[1:0] = 11) output voltage ?40 to +85 c, v dd = 1.8?3.8 v 1.62 1.65 1.68 v vref turn-on time ? ? 1.5 s supply current normal power mode low power mode ? ? 260 140 ? ? a external reference (ref sl[1 :0 ] = 00, refoe = 0) input voltage range 0 ? v dd v input current sample rate = 300 ksps; vref = 3.0 v ? 5. 25 ? a
rev. 0.3 65 si102x/3x table 4.15. iref0 electrical characteristics v dd = 1.8 to 3.8 v, ? 40 to +85 c, unless otherwise specified. parameter conditions min typ max units static performance resolution 6 bits output compliance range low power mode, source high current mode, source low power mode, sink high current mode, sink 0 0 0.3 0.8 ? ? ? ? v dd ? 0.4 v dd ? 0.8 v dd v dd v integral nonlinearity ? <0.2 1.0 lsb differential nonlinearity ? <0.2 1.0 lsb offset error ? <0.1 0.5 lsb full scale error low power mode, source ? ? 5 % high current mode, source ? ? 6 % low power mode, sink ? ? 8 % high current mode, sink ? ? 8 % absolute current error low power mode so ur cing 20 a ? <1 3 % dynamic performance output settling time to 1/2 lsb ? 300 ? ns startup time ? 1 ? s power consumption net power supply current ? (v dd supplied to iref0 minus any output source current) low power mode, source iref0dat = 000001 ? 10 ? a iref0dat = 111111 ? 10 ? a high current mode, source iref0dat = 000001 ? 10 ? a iref0dat = 111111 ? 10 ? a low power mode, sink iref0dat = 000001 ? 1 ? a iref0dat = 111111 ? 11 ? a high current mode, sink iref0dat = 000001 ? 12 ? a iref0dat = 111111 ? 81 ? a note: refer to ?7.1. pwm enhanced mode? on page 110 for information on how to improve iref0 resolution.
si102x/3x 66 rev. 0.3 table 4.16. comparator electrical characteristics v dd = 1.8 to 3.8 v, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units response time: mode 0, v dd = 2.4 v, v cm * = 1.2 v cp0+ ? cp0? = 100 mv ? 120 ? ns cp0+ ? cp0? = ?100 mv ? 110 ? ns response time: mode 1, v dd = 2.4 v, v cm * = 1.2 v cp0+ ? cp0? = 100 mv ? 180 ? ns cp0+ ? cp0? = ?100 mv ? 220 ? ns response time: mode 2, v dd = 2.4 v, v cm * = 1.2 v cp0+ ? cp0? = 100 mv ? 350 ? ns cp0+ ? cp0? = ?100 mv ? 600 ? ns response time: mode 3, v dd = 2.4 v, v cm * = 1.2 v cp0+ ? cp0? = 100 mv ? 1240 ? ns cp0+ ? cp0? = ?100 mv ? 3200 ? ns common-mode rejection ratio ? 1.5 ? mv/v inverting or non- inverting input vo ltage range ?0.25 ? v dd + 0.25 v input capacitance ? 12 ? pf input bias current ? 1 ? na input offset voltage ?10 ? +10 mv power supply power supply rejection ? 0.1 ? mv/v power-up time vdd = 3.8 v ? 0.6 ? s vdd = 3.0 v ? 1.0 ? s vdd = 2.4 v ? 1.8 ? s vdd = 1.8 v ? 10 ? s supply current at dc mode 0 ? 23 ? a mode 1 ? 8.8 ? a mode 2 ? 2.6 ? a mode 3 ? 0.4 ? a *note: vcm is the common-mode voltage on cp0+ and cp0?.
rev. 0.3 67 si102x/3x hysteresis mode 0 hysteresis 1 (cpnhyp/n1?0 = 00) ? 0 ? mv hysteresis 2 (cpnhyp/n1?0 = 01) ? 8.5 ? mv hysteresis 3 (cpnhyp/n1?0 = 10) ? 17 ? mv hysteresis 4 (cpnhyp/n1?0 = 11) ? 34 ? mv mode 1 hysteresis 1 (cpnhyp/n1?0 = 00) ? 0 ? mv hysteresis 2 (cpnhyp/n1?0 = 01) ? 6.5 ? mv hysteresis 3 (cpnhyp/n1?0 = 10) ? 13 ? mv hysteresis 4 (cpnhyp/n1?0 = 11) ? 26 ? mv mode 2 hysteresis 1 (cpnhyp/n1?0 = 00) ? 0 1 mv hysteresis 2 (cpnhyp/n1?0 = 01) 2 5 10 mv hysteresis 3 (cpnhyp/n1?0 = 10) 5 10 20 mv hysteresis 4 (cpnhyp/n1?0 = 11) 12 20 30 mv mode 3 hysteresis 1 (cpnhyp/n1?0 = 00) ? 0 ? mv hysteresis 2 (cpnhyp/n1?0 = 01) ? 4.5 ? mv hysteresis 3 (cpnhyp/n1?0 = 10) ? 9 ? mv hysteresis 4 (cpnhyp/n1?0 = 11) ? 17 ? mv table 4.17. vreg0 electrical characteristics v dd = 1.8 to 3.8 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units input voltage range 1.8 ? 3.8 v bias current normal, idle, suspend, or stop mode ? 20 ? a table 4.16. comparator electrical characteristics (continued) v dd = 1.8 to 3.8 v, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units *note: vcm is the common-mode voltage on cp0+ and cp0?.
si102x/3x 68 rev. 0.3 table 4.18. lcd0 electrical characteristics v dd = 1.8 to 3.8 v; t a = ?40 to +85 c unless otherwise specified; us ing factory-calibrated settings. parameter conditions min typ max units charge pump output voltage error ? 30 ? mv lcd clock frequency 16 ? 33 khz table 4.19. pc0 electrical characteristics v dd = 1.8 to 3.8 v; t a = ?40 to +85 c unless otherwise specified; us ing factory-calibrated settings. parameter conditions min typ max units supply current (25 c, 2 ms sample rate) 1.8 v 2. 2 v 3. 0 v 3.8 v ? ? ? ? 145 175 235 285 ? ? ? ? na
rev. 0.3 69 si102x/3x table 4.20. dc0 (buck converter) electrical characteristics v dd = 1.8 to 3.8 v; t a = ?40 to +85 c unless otherwise specified; us ing fa ctory-calibrated settings. parameter condition min typ max units input voltage range 1.8 ? 3.8 v input supply to output ? voltage differential ? (for regulation) 0.45 ? ? v output voltage range programmable from 1.8 to 3.5 v 1.8 1.9 3.5 v output power v dc = 1.8 to 3.0 v. v bat ? v dc + 0.5. ? ? 250 mw output load current ? ? 85 ma inductor value 1 0.47 0.56 0.68 h inductor current rating for load currents less than 50 ma for load currents greater than 50 ma 450 550 ? ? ? ? ma output capacitor value 2 1 2.2 10 f input capacitor 2 ? 4.7 ? f output load current ? (based on output power s p ecification) target output = 1.8 to 3.0 v 3 target output = 3.1 v 3 target output = 3.3 v 3 target output = 3.5 v 4 ? ? ? ? ? ? ? ? ? ? 85 3 70 3 50 3 10 4 ma load regulation output = 1.9 v; load current up-to 85 ma; supply range = 2.4?3.8 v ? 0.03 ? mv/ma maximum dc load current du ri ng startup ? ? 5 ma switching clock frequency 1.9 2.9 3.8 mhz notes: 1. re commended: inductor similar to nlv32t-r56j-pf (0.56 h ) 2. recommended: x7r or x5r ceramic capacitors with lo w esr. example: murata grm21br71c225k with esr < 10 m? ( @ frequency > 1 mhz) 3. v bat ? v dc + 0.5. auto-bypass enabled (dc0md.2 = 1). 4. v bat = 3.8v. auto-bypass disabled (dc0md.2 = 0).
si102x/3x 70 rev. 0.3 4.3. ezradiopro ? peripheral electrical characteristics table 4.21. dc characteristics 1 parameter symbol conditions min typ max units supply voltage ra ng e v dd_rf 1.8 3.0 3.6 v power saving modes i shutdown rc oscillator, main digital regulator, and low power digital regulator off ? 15 50 na i standby low power digital regulator on (register values retained) and main digital regulator, and rc oscillator off ? 450 800 na i sleep rc oscillator and low power digital regulator on (register values retain ed) and main digital regulator off ? 1 ? a i sensor- lbd main digital regulator and low battery detector on, crystal oscillator an d all other blocks off 2 ? 1 ? a i sensor-ts main digital regula tor and temperature sensor on, crystal oscillator an d all other blocks off 2 ? 1 ? a i ready crystal oscillator and main digital regulator on, all other blocks off. crystal oscillator buffer disabled ? 800 ? a tune mode current i tune synthesizer and regulators enabled ? 8.5 ? ma rx mode current i rx ? 18.5 ? ma tx mode current ? si1020/21/22/23/30/ 31/3 2 /33 i tx_+20 txpow[2:0] = 111 (+20 dbm) using silicon labs? reference design. tx cur r ent consumption is dependent on match and board layout. ? 85 ? ma tx mode current ? si1024/25/26/27/34/ 35/3 6 /37 i tx_+13 txpow[2:0] = 110 (+13 dbm) using silicon labs? reference design. tx cur r ent consumption is dependent on match and board layout. ? 30 ? ma i tx_+1 txpow[2:0] = 010 (+1 dbm) using silicon labs? reference design. tx cur r ent consumption is dependent on match and board layout. ? 17 ? ma notes: 1. all specification guaranteed by pr odu ction test unless otherwise noted. production test conditions and max limits are listed in the "production test conditions" section on page 77 . 2. guara nteed by qualification. quali fication test conditions are listed in the "production test conditions" section on page 77 .
rev. 0.3 71 si102x/3x table 4.22. synthesizer ac electrical characteristics 1 parameter symbol conditions min typ max units synthesizer frequency ? range f syn 240 ? 960 mhz synthesizer frequency ? resolution 2 f res-lb low band, 240?480 mhz ? 156.25 ? hz f res-hb high band, 480?960 mhz ? 312.5 ? hz reference frequency in put le vel 2 f ref_lv when using external reference signal driving xout pin, instead of using crystal. measured peak- to-peak (v pp ) 0.7 ? 1.6 v synthesizer settling time 2 t lock measured from exiting ready mode with xosc running to any frequency. including vco calibration. ? 200 ? s residual fm 2 ? f rms integrated over ? 250 khz band - width (500 hz lower bound of in te gration) ? 2 4 khz rms phase noise 2 l ? (f m ) ? f = 10 khz ? ?80 ? dbc/hz ? f = 100 khz ? ?90 ? dbc/hz ? f = 1 mhz ? ?115 ? dbc/hz ? f = 10 mhz ? ?130 ? dbc/hz notes: 1. all specification guaranteed by produ ctio n test unless otherwise noted. production test conditions and max limits are listed in the "production test conditions" section on page 77 . 2. guaranteed by qualification. qualificat ion test conditions are listed in t he "production test conditions" section on page 77 .
si102x/3x 72 rev. 0.3 table 4.23. receiver ac electrical characteristics 1 parameter symbol conditions min typ max units rx frequence range f rx 240 ? 960 mhz rx sensitivity 2 p rx_2 (ber < 0.1%) (2 kbps, gfsk, bt = 0.5, ? f = ? 5 khz) 3 ? ?121 ? dbm p rx_40 (ber < 0.1%) (40 kbps, gfsk, bt = 0.5, ? f = ? 20 khz) 3 ? ?108 ? dbm p rx_100 (ber < 0.1%) (100 kbps, gfsk, bt = 0.5, ? f = ? 50 khz) 3 ? ?104 ? dbm p rx_125 (ber < 0.1%) (125 kbps, gfsk, bt = 0.5, ? f = ? 62.5 khz) ? ?101 ? dbm p rx_ook (ber < 0.1%) (4.8 kbps, 350 khz bw, ook) 3 ? ?110 ? dbm (ber < 0.1%) (40 kbps, 400 khz bw, ook) 3 ? ?102 ? dbm rx channel bandwidth 3 bw 2.6 ? 620 khz ber variation vs power leve l 3 p rx_res up to +5 dbm input level ? 0 0.1 ppm lna input impedance 3 (unmatched?measured differentially across rx input pins) r in-rx 915 mhz ? 51?60j ? ? 868 mhz ? 54?63j ? 433 mhz ? 89?110j ? 315 mhz ? 107?137j ? rssi resolution res rssi ? 0.5 ? db ? 1-ch of fset selectivity 3 c/i 1-ch desired ref signal 3 db above sensitivity, ber < 0.1%. interferer and desired modulated with 40 kbps ? f = 20 khz gfsk with bt = 0.5, cha nnel spacing = 150 khz ? ?31 ? db ? 2-ch offset selectivity 3 c/i 2-ch ? ?35 ? db ? ? 3-ch offset selectivity 3 c/i 3-ch ? ?40 ? db blocking at 1 mhz offset 3 1m block desired ref signal 3 db above sensitivity . interferer and desired modulated with 40 kbps ? f = 20 khz gfsk with bt = 0.5 ? ?52 ? db blocking at 4 mhz offset 3 4m block ? ?56 ? db blocking at 8 mhz offset 3 8m block ? ?63 ? db image rejection 3 im rej rejection at the image frequency. if=937 khz ? ?30 ? db spurious emissions 3 p ob_rx1 measured at rx pins ? ? ?54 dbm notes: 1. all specification guaranteed by pr odu ction test unless otherwise noted. production test conditions and max limits are listed in the "production test conditions" section on page 77 . 2. re ceive sensitivity at multiples of 30 mhz may b e degraded. if channels with a multiple of 30 mhz are required it is recommended to shift the crystal frequency. contact silicon labs applications support for recommendations. 3. guara nteed by qualification. q uali fication test conditions are listed in the "production test conditions" section on page 77 .
rev. 0.3 73 si102x/3x table 4.24. transmitter ac electrical characteristics 1 parameter symbol conditions min typ max units tx frequency range f tx 240 ? 960 mhz fsk data rate 2 dr fsk 0.123 ? 256 kbps ook data rate 2 dr ook 0.123 ? 40 kbps modulation deviation ? f1 860?960 mhz 0.625 320 khz ? f2 240?860 mhz 0.625 160 khz modulation deviation resolution 2 ? f res ? 0.625 ? khz output power range? si1 020 /21/22/23/30/31/32/33 3 p tx +1 ? +20 dbm output power range? si1 024 /25/26/27/34/35/36/37 3 p tx ?4 ? +13 dbm tx rf output steps 2 ' p rf_out controlled by txpow[2:0] ? 3 ? db tx rf output level 2 variation vs. temperature ' p rf_temp ?40 to +85 q c ? 2 ? db tx rf output level variation vs. frequency 2 ' p rf_freq measured across any one frequency band ? 1 ? db transmit modulation filtering 2 b*t gaussian filtering band - with time product ? 0.5 ? spurious emissions 2 p ob-tx1 p out = 11 dbm, fr equencies <1 ghz ? ? ?54 dbm p ob-tx2 1?12.75 ghz, excluding harmonics ? ? ?54 dbm harmonics 2 p 2harm using reference design tx matching network and filter with max output power. har - monics reduce linearly with ou tp ut power. ? ? ?42 dbm p 3harm ? ? ?42 dbm notes: 1. all specification guara nteed by production test unless otherwise noted. production test conditions and max limits are listed in the "production test conditions" section on page 77. 2. gu aranteed by qualification. qu alification test conditions are listed in the "production test conditions" section on page 77. 3. output power is dependent on matching component s, boa rd layout, and is measured at the pin.
si102x/3x 74 rev. 0.3 table 4.25. auxiliary block specifications 1 parameter symbol conditions min typ max units temperature sensor ? accuracy 2 ts a after calibrated via sen - sor offset register t v offs[7:0] ? 0.5 ? c temperature sensor ? sensitivity 2 ts s ? 5 ? mv/c low battery detector ? resolution 2 lbd res ? 50 ? mv low battery detector ? conversion time 2 lbd ct ? 250 ? s microcontroller clock ? output frequency f mc configurable to 30 mhz, 15 mhz, 10 mhz, 4 mhz, 3 mhz, 2 mhz, 1 mhz, or 3 2 .768 khz 32.768k ? 30m hz general purpose adc re so lution 2 adc enb ? 8 ? bit general purpose adc bit ? resolution 2 adc res ? 4 ? mv/bit temp sensor & general purp ose adc con version time 2 adc ct ? 305 ? s 30 mhz xtal start-up time t 30m using xtal and board layout in reference design. start-up time will vary with xtal type and board layout. ? 600 ? s 30 mhz xtal cap ? resolution 2 30m res see ?32.5.8. crystal oscillator? on page 464 for the total load capaci - tance calculation ? 97 ? ff 32 khz xtal start-up time 2 t 32k ? 6 ? sec 32 khz accuracy using internal rc oscillator 2 32krc res ? 1000 ? ppm 32 khz rc oscillator start- up t 32krc ? 500 ? s por reset time t por current consumption during por time is 200 a typical ? 9.5 ? ms software reset time 2 t soft ? 250 ? s notes: 1. all specification guaranteed by produ ctio n test unless otherwise noted. pr oduction test conditions and max limits are listed in the "production test conditions" section on page 77 . 2. guara nteed by qualification. qu alificatio n test conditions are listed in the "production test conditions" section on page 77 .
rev. 0.3 75 si102x/3x table 4.26. digital io specifications (nirq) parameter symbol conditions min typ max units rise time t rise 0.1 x v dd_rf to 0.9 x v dd_rf , c l = 5 pf ? ? 8 ns fall time t fall 0.9 x v dd_rf to 0.1 x v dd_rf, c l = 5 pf ? ? 8 ns input capacitance c in ? ? 1 pf logic high level inpu t voltage v ih v dd_rf ? 0.6 ? ? v logic low level in pu t voltage v il ? 0.6 v input current i in 0 = hh ? ? 8 ns fall time t fall 0.9 x v dd_rf to 0.1 x v dd_rf, c l = 10 pf, drv<1:0> = hh ? ? 8 ns input capacitance c in ? ? 1 pf logic high level input vol tage v ih v dd_rf ? 0.6 ? v logic low level input vo l tage v il ? ? 0.6 v input current i in 0 = ll 0.1 0.5 0.8 ma i omaxlh drv<1:0> = lh 0.9 2.3 3.5 ma i omaxhl drv<1:0> = hl 1.5 3.1 4.8 ma i omaxhh drv<1:0> = hh 1.8 3.6 5.4 ma logic high level out - put voltage v oh i oh < i omax source, v dd_rf = 1.8 v v dd_rf ? 0.6 ? ? v logic low level out - put voltage v ol i ol < i omax sink, v dd_rf = 1.8 v ? ? 0.6 v note: all specifications guaranteed by qualif ication. qualification test condition s are listed in the "production test conditions" section on page 77.
si102x/3x 76 rev. 0.3 table 4.28. absolute maximum ratings parameter value unit v dd_rf to gnd ?0.3, +3.6 v instantaneous v rf-peak to gnd on tx output pin ?0.3, +8.0 v sustained v rf-peak to gnd on tx output pin ?0.3, +6.5 v voltage on digital control inputs ?0.3, v dd_rf + 0.3 v voltage on analog inputs ?0.3, v dd_rf + 0.3 v rx input power +10 dbm operating ambient temperature range t a ?40 to +85 ? c thermal impedance ? ja 30 ? c/w junction temperature t j +125 ? c storage temperature range t stg ?55 to +125 ? c note: stresses beyond those listed under ?absolute maxi mum ratings? may cause permanent damage to the device. these are stress ratings only and functional oper ation of the device at or beyond these ratings in the operational sections of the specifications is not implie d. exposure to absolute maximum rating conditions for extended periods may affect device reliability. power am plifier may be damaged if switched on without proper load or termination connected. tx matching network design will influence tx vrf-peak on tx output pin. caution: esd sensitive device.
rev. 0.3 77 si102x/3x 4.4. definition of test conditi ons for the ezradiopro peripheral production test conditions: ? t a = +25 c ? v dd = +3.3 vdc ? sensitivity measured at 919 mhz ? tx output power measured at 915 mhz ? external reference signal (xout) = 1.0 v pp at 30 mhz, centered around 0.8 vdc ? production test schematic (unless noted otherwise) ? all rf input and output levels referred to the pins of the si102x/3x (not the rf module) qualification test conditions: ? t a = ?40 to +85 c ? v dd_rf = +1.8 to +3.6 vdc ? using reference design or production test schematic ? all rf input and output levels referred to the pins of the si102x/3x (not the rf module)
si102x/3x 78 rev. 0.3 5. sar adc with 16-bit auto -averaging accumulator and autonomous low power burst mode the adc0 on si102x/3x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive -app roximation-register (sar) adc with integrated track-and-hold and prog rammable window detector. adc0 also has an autono - mous low power burst mode which can automatically enable adc0, capture and accumulate samples, the n place adc0 in a low power shutdown mode without cpu intervention. it also has a 16-bit accumulator that can automatically oversample and average the adc results. see section 5.4 for more details on using the adc in 12-bit mode. the adc is fully configurable under software control vi a s pecial function registers. the adc0 operates in single-ended mode and may be configured to measure various different signals using the analog multi - plexer described in ?5.7. adc0 analog multiplexer? on page 95 . the voltage reference for the adc is selected as described in ?5.9. voltage and ground reference options? on page 100 . figure 5.1. adc0 functional block diagram 5.1. output code formatting the registers adc0h and adc0l contain the high and low bytes of the output conversion code from the adc at the completion of each conversion. data can be right-justified or left-justified, depending on the setting of the ad0sjst[2:0]. when the repeat count is set to 1, conversion codes are represented as 10- bit unsigned integers. inputs are measured from 0 to vref x 1023/1024. example c ode s are shown below for both right-justified and left-justified data. unused bits in the adc0h and adc0l registers are set to 0. adc0cf amp0gn ad0tm ad08be ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10/12-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int bursten ad0en timer 0 overflow timer 2 overflow timer 3 overflow start conversion 000 ad0busy (w) vdd adc0lth ad0wint 001 010 011 100 cnvstr input window compare logic adc0ltl adc0gth adc0gtl adc0l ain+ from amux0 burst mode logic adc0tk adc0pwr 16-bit accumulator
rev. 0.3 79 si102x/3x when the repeat count is greater than 1, the output conversion code represents the accumulated result of the conversions performed and is updated after the last co nversion in the series is finished. sets of 4, 8, 16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. the repeat count can be selected using the ad0rpt bits in the adc0ac register. when a repeat count higher than 1, the adc output must be right-justified (ad0sjst = 0xx); unused bits in the adc0h and adc0l reg isters are set to 0. the example below shows the ri ght-justified result for various input voltages and repeat counts. notice that accumulating 2 n samples is equivalent to left-shifting by n bit positions when all samples returned from the adc have the same value. the ad0sjst bits can be used to format the contents of the 16-bit accumulator. the accumulated result can be shif ted right by 1, 2, or 3 bit positions. base d on the principles of oversampling and averaging, the effective adc resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4. the example below shows how to increase the effective adc resolution by 1, 2, and 3 bits to obtain an effective adc resolution of 11-bit, 12-bit, or 13-bit respectively wi thout cpu intervention. input voltage right-justified adc0h:adc0l (ad0sjst = 000) lef t -justified adc0h:adc0l (ad0sjst = 100) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 input voltage repeat count = 4 repeat count = 16 repeat count = 64 v ref x 1023/1024 0x0ffc 0x3ff0 0xffc0 v ref x 512/1024 0x0800 0x2000 0x8000 v ref x 511/1024 0x07fc 0x1ff0 0x7fc0 0 0x0000 0x0000 0x0000 input voltage repeat count = 4 shift right = 1 11-bit result repeat count = 16 shift right = 2 12-bit result repeat count = 64 shift right = 3 13-bit result v ref x 1023/1024 0x07f7 0x0ffc 0x1ff8 v ref x 512/1024 0x0400 0x0800 0x1000 v ref x 511/1024 0x03fe 0x04fc 0x0ff8 0 0x0000 0x0000 0x0000
si102x/3x 80 rev. 0.3 5.2. modes of operation adc0 has a maximum conversion speed of 300 ksps in 10-bit mode. the ad c0 conversion clock (sar - clk) is a divided version of the system clock when bu rst mod e is disabled (bursten = 0), or a divided version of the low power o scillator when burst mode is enabled (bursen = 1). the clock divide value is determined by the ad0sc bits in the adc0cf register. 5.2.1. starting a conversion a conversion can be initiated in one of five ways, dep end ing on the programmed states of the adc0 start of conversion mode bits (ad0cm2 ? 0) in register adc0cn. conversions may be initiated by one of the fol - lowing: 1. writing a 1 to the ad0busy bit of register adc0cn 2 . a timer 0 overflow (i.e., timed continuous conversions) 3. a timer 2 overflow 4. a timer 3 overflow 5. a rising edge on the cnvstr input signal (pin p0.6) writing a 1 to ad0busy provides software contro l of adc0 wher eby conversions are performed "on- demand". during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0bu sy triggers an interrupt (when enabl ed) and sets the adc0 interrupt flag (ad0int). when polling for adc conversion comple tions, the adc0 interrupt flag (ad0int) should be used. converted data is available in the adc0 data registers, adc0h:adc0l, wh en bit ad0int is logic 1. when t i mer 2 or timer 3 overflows are used as the conversion so ur ce, low byte overflows are used if timer 2/3 is in 8-bit mode; high byte overflows are used if timer 2/3 is in 16-bit mode. see ?33. timers? on page 491 for timer configuration. important note about using cnvstr: th e cnvstr input pin also functions as port pin p0.6. when the cnvstr input is used as the adc0 conversion source, port pin p0.6 should be skipped by the digital crossbar. to configure the crossbar to skip p0.6, set to 1 bit 6 in register p0skip. see ?27. port input/out - put? on page 358 for details on port i/o configuration. 5.2.2. tracking modes each adc0 conversion must be preceded by a minimum tr acking time in order for the converted result to be accurate. the minimum tracking time is given in ta b l e 4.12 . the ad0tm bit in register adc0cn con - trols the adc0 track-and-hold mode. in its default st ate whe n burst mode is dis abled, the adc0 input is continuously tracked, except w hen a conversion is in progress. when the ad0tm bit is logic 1, adc0 op e rates in low-power track-and-hold mode. in this mode, each conversion is preceded by a tracking period of 3 sar clocks (after the start-of-conversion signa l). wh en the cnvstr signal is used to initiate conversions in low-power tracking mode, adc0 tra cks only when cnvstr is low; conversion begins on the rising edge of cnvstr (see figure 5.2 ). tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. low-power track- an d- hold mode is also useful when amux settings are frequently changed, due to the settling time requirements described in ?5.2.4. settling time require - ments? on page 83 .
rev. 0.3 81 si102x/3x figure 5.2. 10-bit adc track and conversion example timing (bursten = 0) write '1' to ad0busy, timer 0, timer 2, timer 1, timer 3 overflow (ad0cm[2:0]=000, 001,010 011, 101) ad0tm=1 track convert low power mode ad0tm=0 track or convert convert track low power or convert sar clocks sar clocks b. adc0 timing for internal trigger source 123456789 cnvstr (ad0cm[2:0]=100) ad0tm=1 a. adc0 timing for external trigger source sar clocks track or convert convert track ad0tm=0 track convert low power mode low power or convert 10 11 12 13 14 123456789 10 11 12 13 14 123456789 10 11 12 13 14 15 16 17
si102x/3x 82 rev. 0.3 5.2.3. burst mode burst mode is a power saving feature that allows adc0 to remain in a low power state between conver - sions. when burst mode is enabled, adc0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or 6 4 using an internal burst mode clock (approximately 20 mhz), then re-enters a low power state. since the bur s t mode clock is independent of the system clock, adc0 can perform multiple conversions then enter a low power state within a single system clock cycle, even if the system clock is slow (e.g. 32.768 khz), or suspended. burst mode is enabled by setting bursten to logic 1. when in burst mode, ad0en controls the adc0 id le po wer state (i.e. the state adc0 enters when not tracking or performing conversions). if ad0en is set to logic 0, adc0 is powered down after each burst. if ad0en is set to logic 1, adc0 remain s e nab led after each burst. on each convert start signal, adc0 is awak ened from its idle power state. if adc0 is powered down, it will automatically power up and wait th e programmable po wer-up time controlled by the ad0pwr bits. otherwise, adc0 will start tracking and converting immediately. figure 5.3 shows an exam - ple of burst mode operation with a slow system clock an d a re peat count of 4. when burst mode is enabled, a single conv ert st art will initiate a numb er of conversions e qual to th e repeat count. when burst mode is disabled, a convert start is required to initiate each conversion. in both modes, the adc0 end of conversion interrupt flag (ad0int) will be set after ?repea t count? conversions have been accumulated. similarl y, the window comparator will not compare the result to the greater-than and less-than registers until ?repeat count? conversions have been accumulated. in burst mode, tracking is determ ine d by the settings in ad0pwr and ad0tk. the default settings for these registers will work in most applications without modification; howeve r, settling time requirements may need adjustment in some applications. refer to ?5.2.4. settling time requirements? on page 83 for more details. notes: ? setting ad0tm to 1 will insert an additional 3 sar clocks of trac king before each conversion, regardless of the settings of ad0pwr and ad0tk. ? when using burst mode, care must be taken to issue a convert start signal no faster than once every four sysclk periods. this includes external convert start signals. figure 5.3. burst mode tracking example with repeat count set to 4 convert start ad0tm = 1 ad0en = 0 powered down powered down system clock t 3 c power-up and track t c t c t c power-up and track t c.. ad0tm = 0 ad0en = 0 powered down powered down c power-up and track t c t c t c power-up and track t c.. ad0pwr t = tracking set by ad0tk t3 = tracking set by ad0tm (3 sar clocks) c = converting ad0tk t 3 t 3 t 3
rev. 0.3 83 si102x/3x 5.2.4. settling time requirements a minimum amount of tracking time is required before each conversion can be performed, to allow the sampling capacitor voltage to settle. this tracking time is determined by the amux0 resistance, the adc0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. note that in low-power tracking mode, three sar clocks ar e used for tracking at the start of every conversion. for many applications, t hese three sar clocks will meet the minimum tracking time requirements, and higher values for the ex ternal source impedance will increase the required tracking time. figure 5.4 shows the equivalent adc0 input circuit. the re qu ired adc0 settling time for a given settling accuracy (sa) may be approximated by equation . when measuring the temperature sensor output or v dd with respect to gnd, r total reduces to r mux . see ta b l e 4.12 for adc0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the r equired settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the ad c resolution in bits (10). figure 5.4. adc0 equivalent input circuits 5.2.5. gain setting the adc has gain settings of 1x and 0.5x. in 1x mo de, th e full scale reading of the adc is determined directly by v ref . in 0.5x mode, the full-scale reading of the adc occurs when the input voltage is v ref x 2. the 0.5x gain setting can be useful to obtain a higher input voltage range when using a small v ref volt - age, or to measure input vo lt a ges that are between v ref and v dd . gain settings for the adc are con - trolled by the amp0gn bit in register adc0cf. t 2 n sa ------ - ?? ?? r total c sample ? ln = r mux c sample rc input = r mux * c sample mux select p0.x note: the value of csample depends on the pga gain. see table 4.12 for details.
si102x/3x 84 rev. 0.3 5.3. 8-bit mode setting the adc08be bit in register adc0cf to 1 will put the adc in 8-bit mode.in 8-bit mode, only the 8 msbs of data are converted, allowing the conversi on to b e completed in two fewer sar clock cycles than a 10-bit conversion. this can result in an overall lower power consumption since the system can spend more time in a low power mode. the two lsbs of a conversion are always 00 in this mode, and the adc0l register will always read back 0x00. 5.4. 12-bit mode si102x/3x devices have an enhanced sar converter that provides 12-bit resolution while retaining the 10- and 8-bit operating modes of the other devices in t he family. when configured for 12-bit conversions, the adc performs four 10-bit conversions using four differen t reference voltages and combines the results into a single 12-bit value. unlike simple averaging techniques , this method provides true 12-bit resolution of ac or dc input signals without depending on noise to pr ovide dithering. the converter also employs a hard - ware dynamic element matching algor i thm that reconfigures the larges t elements of the internal dac for each of the four 10-bit conversions to cancel the any matching errors, enabling the converter to achieve 12-bit linearity performance to go along with its 12 -bit resolution. for best performance, the low power oscillator should be selected as the system cloc k source while taking 12-bit adc measurements. the 12-bit mode is enabled by setting the ad012be bit ( a dc0ac.7) to logic 1 and configuring burst mode for four conversions as described in section 5.2.3 . the conversion can be initiated using any of the meth - ods described in section 5.2.1 , and the 12-bit result will appear in the adc 0 h and adc0l registers. since the 12-bit result is for m ed from a combination of four 10-bit results, the maximum output value is 4 x (1023) = 409 2, rather than the max value of (2^12 ? 1) = 4095 that is produced by a traditional 12-bit converter. to further increase resolution, the burst mode repeat value may be configured to any multiple of four conver - sions. for example, if a repeat va lue of 16 is selected, t he adc0 output will be a 14 -bit number (s um of four 12-bit numbers) with 13 effective bits of resolution.
rev. 0.3 85 si102x/3x 5.5. low power mode the sar converter provides a low power mode that a llows a significant reduct ion in operating current when operating at low sar clock frequencies. low power mode is enabled by setting the ad0lpm bit (adc0pwr.7) to 1. in general, low power mode is recommended when operating with sar conversion clock frequency at 4 mhz or less. see the electrical characteristics chapter for details on power consump - tion and the maximum clock frequencies allowed in each mode. setting the low power mode bit reduces the bias currents in both the sar converter and in the high-speed voltage reference. table 5.1. representative conversion times and energy consumption for the sar adc with 1.65 v high-s peed vref normal power mode low power mode 8 bit 10 bit 12 bit 8 bit 10 bit 12 bit highest nominal sar clock f r equency 8.17 mhz (24.5/3) 8.17 mhz (24.5/3) 6.67 mhz (20.0/3) 4.08 mhz (24.5/6) 4.08 mhz (24.5/6) 4.00 mhz (20.0/5) total number of co nve rsion clocks required 11 13 52 (13 x 4) 11 13 52 (13*4) total tracking time (min) 1.5 s 1.5 s 4.8 s (1 .5 +3 x 1.1) 1.5 s 1.5 s 4.8 s (1.5+3 x 1.1) total time for one conv ers ion 2.85 s 3.09 s 12.6 s 4.19 s 4.68 s 17.8 s adc throughput 351 ksps 323 ksps 79 ksps 238 ksps 214 ksps 56 ksps energy per conv ers ion 8.2 nj 8.9 nj 36.5 nj 6.5 nj 7.3 nj 27.7 nj note: this table assumes that the 24.5 mhz precision oscillator is used for 8- and 10-bit modes, and the 20 mhz low po wer oscillator is used for 12-bit mode. the values in the table assume that the oscillators run at their nominal frequencies. the maximum sar clock values given in ta b l e 4.12 allow for maximum oscillation frequencies of 25.0 mhz and 22 mhz for the precision a nd low-power oscillators, respectively, when using the given sar clock divider values. energy calculatio ns are for the adc subsystem only and do not include cpu current.
si102x/3x 86 rev. 0.3 sfr page = all pages; sfr address = 0xe8; bit-addressable ; sfr definition 5.1. adc0cn: adc0 control bit 7 6 5 4 3 2 1 0 name ad0en bursten ad0int ad0busy ad0wint adc0cm[2:0] type r/w r/w r/w w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ad0en adc0 enable. 0: adc0 disabled (low-power shutdown). 1: adc0 enabled (active and re ady for da ta conversions). 6 bursten adc0 burst mode enable. 0: adc0 burst mode disabled. 1: adc0 burst mo de enabled. 5 ad0int adc0 conversion complete interrupt flag. set by hardware upon completion of a data conversion (bursten=0), or a burst o f conversions (bursten=1). can trigger an interrupt. must be cleared by soft - ware. 4 ad0busy adc0 busy. writing 1 to this bit initiates an adc conversion when adc0cm[2:0] = 000. 3 ad0wint adc0 window compare interrupt flag. set by hardware when the contents of adc0h:adc0l fall within the window speci - fied by adc0gth:adc0gtl and adc0lth:adc0ltl. can trigger an interrupt. must be cleared by software. 2:0 adc0cm[2:0] adc0 start of conversion mode select. specifies the adc0 start of conversion source. 000: adc0 conversion initiat ed on write of 1 to ad0busy. 001: adc0 conversion initiated on overflow of timer 0. 010: adc0 conversion initiated on overflow of timer 2. 011: adc0 conversion initiated on overflow of timer 3. 1xx: adc0 conversion initiated on rising edge of cnvstr.
rev. 0.3 87 si102x/3x sfr page = 0x0; sfr address = 0xbc sfr definition 5.2. adc0cf: adc0 configuration bit 7 6 5 4 3 2 1 0 name ad0sc[4:0] ad08be ad0tm amp0gn type r/w r/w r/w r/w reset 1 1 1 1 1 0 0 0 bit name function 7:3 ad0sc[4:0] adc0 sar conversion clock divider. sar conversion clock is derived from fclk by the following equation, where ad0sc refe rs to the 5-bit value held in bits ad0sc[4:0]. sar conversion clock requirements are given in ta b l e 4.12 . bursten = 0: fclk is the current system clock. bursten = 1: fclk is the 20 mhz low power oscillator, independent of the s ystem clock. 2 ad 08be adc0 8-bit mode enable. 0: adc0 operates in 10-bit mode (normal operation). 1: adc0 operates in 8-bit mode. 1 ad0tm adc0 track mode. selects between normal or delayed tracking modes. 0: normal track mode: when adc0 is enabled, conversion begins immediately fol - lowing the start-of-conversion signal. 1: delayed track mode: when adc0 is e nab led, conversion begins 3 sar clock cycles following the start-of-conversion signal. the adc is allowed to track during this time. 0 amp0gn adc0 gain control. 0: the on-chip pga gain is 0.5. 1: the on-chip pga gain is 1. * *round the result up. or ad0sc fclk clk sar -------------------- 1? = clk sar fclk ad 0 sc 1+ ---------------------------- =
si102x/3x 88 rev. 0.3 sfr page = 0x0; sfr address = 0xba sfr definition 5.3. adc0ac: adc0 accumu lator configuration bit 7 6 5 4 3 2 1 0 name ad012be ad0ae ad0sjst[2:0] ad0rpt[2:0] type r/w w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ad012be adc0 12-bit mode enable. enables 12-bit mode. 0: 12-bit mode disabled. 1: 12-bit mode enabled. 6 ad0ae adc0 accumulate enable. enables multiple conversions to be accumulated when burst mode is disabled. 0: adc0h:adc0l contain the result of the latest conversion when burst mode is d i sabled. 1: adc0h:adc0l contain the accumulated conversion results when burst mode is disabled . software must write 0x00 00 to adc0h:adc0l to clear the accumu - lated result. this bit is write-only. always reads 0b. 5:3 ad0sjst[2:0] adc0 accumulator shift and justify. specifies the format of data read from adc0h:adc0l. 000: right justified. no shif ting applied. 001: right justified. shifted right by 1 bit. 010: right justified. shifted right by 2 bits. 011: right justified. shifted right by 3 bits. 100: left justified. no shifting applied. all remaining bit combinations are reserved. 2:0 ad0rpt[2:0] adc0 repeat count. selects the number of conversions to per form and accumulate in burst mode. this bit field must be set to 000 if burst mode is disabled. 000: perform and accumulate 1 conversion. 001: perform and accumulate 4 conversions. 010: perform and accumulate 8 conversions. 011: perform and accumulate 16 conversions. 100: perform and accumulate 32 conversions. 101: perform and accumulate 64 conversions. all remaining bit combinations are reserved.
rev. 0.3 89 si102x/3x sfr page = 0xf; sfr address = 0xba sfr definition 5.4. adc0pwr: adc0 burst mode power-up time bit 7 6 5 4 3 2 1 0 name ad0lpm ad0pwr[3:0] type r/w r r r r/w reset 00001111 bit name function 7 ad0lpm adc0 low power mode enable. enables low power mode operation. 0: low power mode disabled. 1: low power mode enabled. 6:4 unused read = 0000b; write = don?t care. 3:0 ad0pwr[3:0] adc0 burst mode power-up time. sets the time delay required for adc0 to power up from a low power state. for bursten = 0: adc0 power state controlled by ad0en. for bursten = 1 and ad0en = 1: adc0 remains enabled and does not enter a low power state after all co nv ersions are complete. ? conversions can begin immediately following the start-of-conversion signal. for bursten = 1 and ad0en = 0: adc0 enters a low power state after all conversions are complete. ? conversions can begin a programmed delay after the start-of-conversion signal. the adc0 burst mode power-up time is programmed according to the following e qua tion: note: setting ad0pwr to 0x04 provides a typical tracking time of 2 us for the first sample ta ken after the start of conversion. or ad0pwr tstartup 400 ns ---------------------- 1? = tstartup ad0pwr 1+ ?? 400 ns =
si102x/3x 90 rev. 0.3 sfr page = 0xf; sfr address = 0xbb sfr definition 5.5. adc0tk: adc0 burst mode track time bit 7 6 5 4 3 2 1 0 name ad0tk[5:0] type r r r/w reset 0 0011110 bit name function 7 reserved read = 0b; write = must write 0b. 6 unused read = 0b; write = don?t care. 5:0 ad0tk[5:0] adc0 burst mode track time. sets the time delay between consecutiv e co nversions performed in burst mode. the adc0 burst mode track time is programmed according to the following equa - tion: notes: 1. if ad0tm is set to 1, an additional 3 sar clock cycles of track time will be inserted prior to starting the conversion. 2. th e burst mode track delay is not inserted prior to the fi rst conve rsion. the required tracking time for the first conversion should be met by the burst mode power-up time. or ad0tk 63 ttrack 50 ns ---------------- - 1? ?? ?? ?= ttrack 64 ad0tk ? ?? 50 ns =
rev. 0.3 91 si102x/3x sfr page = 0x0; sfr address = 0xbe sfr page = 0x0; sfr address = 0xbd; 5.6. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user-pro - grammed limits, and notifies the system when a desired co ndition is detec t ed. this is especially effective in an interrupt-driven system, saving code space and cpu ba ndwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison valu es. the window detector flag can be programmed to indicate when mea - sured data is inside or outside of the user-program med limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. sfr definition 5.6. adc0h: adc0 data word high byte bit 7 6 5 4 3 2 1 0 name adc0[15:8] type r/w reset 00000000 bit name description read write 7:0 adc0[15:8] adc0 data word high byte. most significant byte of the 16 -b it adc0 accumulator formatted according to the settings in ad0sjst[2:0]. set the most significant byte of th e 16- bit adc0 accumulator to the value written. note: if accumulator shifting is enabled, the most significant bits of the value read will be zeros. this register should not be written when the sync bit is set to 1. sfr definition 5.7. adc0l: adc0 data word low byte bit 7 6 5 4 3 2 1 0 name adc0[7:0] type r/w reset 00000000 bit name description read write 7:0 adc0[7:0] adc0 data word low byte. least significant byte of the 16 -b it adc0 accumulator formatted according to the settings in ad0sjst[2:0]. set the least significant byte of th e 16- bit adc0 accumulator to the value written. note: if accumulator shifting is enabled, the most significant bi ts of the value read will be the least significant bits of the accumulator high byte. this register should not be written when the sync bit is set to 1.
si102x/3x 92 rev. 0.3 sfr page = 0x0; sfr address = 0xc4 sfr page = 0x0; sfr address = 0xc3 sfr definition 5.8. adc0gth: adc0 greater-than high byte bit 7 6 5 4 3 2 1 0 name ad0gt[15:8] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 ad0gt[15:8] adc0 greater-than high byte. most significant byte of the 16-bit greater-than window compare register. sfr definition 5.9. adc0gtl: adc0 great er-than low byte bit 7 6 5 4 3 2 1 0 name ad0gt[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 ad0gt[7:0] adc0 greater-than low byte. least significant byte of the 16-bit greater-than window compare register. note: in 8-bit mode, this register should be set to 0x00.
rev. 0.3 93 si102x/3x sfr page = 0x0; sfr address = 0xc6 sfr page = 0x0; sfr address = 0xc5 5.6.1. window detector in single-ended mode figure 5.5 shows two example window comparisons for right-justified data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth:adc0gtl = 0x0040 (64d). the input voltage can r ang e from 0 to vref x (1023/1024) with respect to gnd, and is represented by a 10-bit unsigned integer value. in the left example, an ad0wint interrup t will be generated if the adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080). in the ri ght example, and ad 0wint i nterrupt will be generated if the adc0 conversion word is outside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080). figure 5.6 shows an example using left-justi - fied data with the same comparison values. sfr definition 5.10. adc0lth: adc0 l ess-than high byte bit 7 6 5 4 3 2 1 0 name ad0lt[15:8] type r/w reset 00000000 bit name function 7:0 ad0lt[15:8] adc0 less-than high byte. most significant byte of the 16-bit less-than window compare register. sfr definition 5.11. adc0ltl: adc0 less-than low byte bit 7 6 5 4 3 2 1 0 name ad0lt[7:0] type r/w reset 00000000 bit name function 7:0 ad0lt[7:0] adc0 less-than low byte. least significant byte of the 16-bit less- than window compare register. note: in 8-bit mode, this register should be set to 0x00.
si102x/3x 94 rev. 0.3 figure 5.5. adc window compare example: right-justified single-ended data figure 5.6. adc window compare example: left-justified single-ended data 5.6.2. adc0 specifications see ?4. electrical characteristics? on page 50 for a detailed listing of adc0 specifications. 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl
rev. 0.3 95 si102x/3x 5.7. adc0 analog multiplexer adc0 on si102x/3x has an analog multiplexer, referred to as amux0. amux0 selects the positive inputs to the single-ended adc0. any of the following may be selected as the po sit ive input: port i/o pins, the on-chip temperature sensor, the vbat power supply, regulated digital supply voltage (output of vreg0), vdc supply, or the positive input may be connected to gnd. the adc0 input channels are selected in the adc0mx register described in sfr definition 5.12 . figure 5.7. adc0 multiplexer block diagram important note about adc0 input configuration: port pins selected as adc0 inputs should be config - ured as analog inputs, and should be skipped by the dig i tal crossbar. to configure a port pin for analog input, set to 0 the corresponding bit in register pnmd in and disable the digital driver (pnmdout = 0 and port latch = 1). to force the crossbar to skip a port pin, set to 1 the corresponding bit in register pnskip. see section ?27. port input/output? on page 358 for more port i/o configuration details. adc0 temp sensor amux vbat adc0mx ad0mx4 ad0mx3 ad0mx2 ad0mx1 am0mx0 ain+ p0.0 p2.3* *p1.0 ? p1.3 are not available as analog inputs digital supply vdc programmable attenuator gain = 0.5 or 1
si102x/3x 96 rev. 0.3 sfr page = 0x0; sfr address = 0xbb sfr definition 5.12. adc0mx: adc0 input channel select bit 7 6 5 4 3 2 1 0 name ad0mx type r r r r/w r/w r/w r/w r/w reset 00011111 bit name function 7:5 unused read = 000b; write = don?t care. 4:0 ad0mx amux0 positive input selection. selects the positive input channel for adc0. 00000: p0.0 10000: p2.0 00001: p0.1 10001: p2.1 00010: p0.2 10010: p2.2 00011: p0.3 10011: p2.3 00100: p0.4 10100: reserved. 00101: p0.5 10101: reserved. 00110: p0.6 10110: reserved. 00111: p0.7 10111: reserved. 01000: reserved 11000: reserved. 01001: reserved 11001: reserved. 01010: reserved 11010: reserved. 01011: reserved 11011: temperature sensor 01100: p1.4 11100: vbat supply voltage (1.8?3.6 v) 01101: p1.5 01110: p1.6 11101: digital supply voltage (vreg0 output, 1.7 v typical) 01111: p1.7 11110: vbat supply voltage (1.8?3.6 v) 11111: ground
rev. 0.3 97 si102x/3x 5.8. temperature sensor an on-chip temperature sensor is included on the si102x/3x which can be directly accessed via the adc multiplexer in single-ended configuration. to use the adc to measure the temperature sensor, the adc mux channel should select the temperature sensor. the temperature sensor transfer function is shown in figure 5.8 . the output voltage (v temp ) is the positive adc input when th e adc multiplexer is set correctly. the tempe bit in register ref0cn enables/disables the temperature sensor, as described in sfr definition 5.15. ref0cn: voltage reference control . while disabled, the temperature sensor defaults to a high impedance state and any adc meas urement s performed on the se nsor will result in meaningless data. refer to table 4.12 for the slope and offset parameters of the temperature sensor. figure 5.8. temperature sensor transfer function 5.8.1. calibration the uncalibrated temperature sensor output is extrem el y linear and suitable for relative temperature mea - surements (see table 4.13 for linearity specificatio ns). f o r absolute temperat ure measurements, offset and/or gain calibration is recommended. t y pically a 1-point (offset) calibration includes the following steps: 1. control/measure the ambient temperat u r e (this temperature must be known). 2. power the device, and delay for a few seconds to allow for self-heating. 3. perform an adc conversion with the temperature sensor selected as the positive input and gnd selected as the negative input. 4. calculate the offset characteri stics, and store this value in non-volatile memory for use with subsequent temperature sensor measurements. temperature voltage v temp = slope x (temp c offset ( v at 25 celsius) slope ( v / deg c) temp c = 25 + ( - 25) + offset v temp - offset ) / slope
si102x/3x 98 rev. 0.3 figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 c. parame - ters that affect ad c measurement, i n particular the voltage re ference value, will also affect temper - ature measurement. a single-point offset measurement of the temper atur e sensor is performed on each device during produc - tion test. the measurement is performed at 25 c 5 c, using the adc with the internal high speed refer - ence buffer selected as the voltage reference. the direct adc result of the measurement is stored in the sfr re giste rs toffh and toffl, shown in sfr definition 5.13 and sfr definition 5.14 . figure 5.9. temperature sensor error with 1-point calibration (v ref = 1.68 v) -40.00 -20.00 0.00 20.00 40.00 60.00 80.00 temperature (degrees c) error (degrees c) -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00
rev. 0.3 99 si102x/3x sfr page = 0xf; sfr address = 0xbe sfr page = 0xf; sfr address = 0xbd sfr definition 5.13. toffh: temperature sensor offset high byte bit 7 6 5 4 3 2 1 0 name toff[9:2] type rrrrrrrr reset varies varies varies varies varies varies varies varies bit name function 7:0 toff[9:2] temperature sensor offset high bits. most significant bits of the 10-bit temperature sensor offset measurement. sfr definition 5.14. toffl: temperature sens or offset low byte bit 7 6 5 4 3 2 1 0 name toff[1:0] type rr reset variesvaries000000 bit name function 7:6 toff[1:0] temperature sensor offset low bits. least significant bits of the 10-bit temp er ature sensor offset measurement. 5:0 unused read = 0; write = don't care.
si102x/3x 100 rev. 0.3 5.9. voltage and ground reference options the voltage reference mux is configurable to use an externally connected voltage reference, the internal voltage reference, or one of two power supply voltages (see figure 5.10 ). the ground reference mux allows the ground reference for adc0 to be selected between the ground pin (gnd) or a port pin dedi - cated to analog ground (p0.1/agnd). the voltage and ground reference options are config ure d using the ref0cn sfr described on sfr definition 5.15. ref0cn: voltage re fe re nce control . electrical specifications are can be found in the electrical specifications chapter. important note about the v ref and agnd inputs: port pins are used as the external v ref and agnd inputs. when using an external voltage reference or th e internal precision reference, p0.0/vref should be configured as an analog input and skipped by the digi tal crossbar. when using agnd as the ground refer - ence to adc0, p0.1/agnd should be configured as an analog input and skipped by the digital crossbar. refer to section ?27. port input/output? on page 358 for complete port i/o configuration details. the exter - nal reference voltage must be within the range 0 ? v ref ? vdd and the external ground reference must be at the same dc voltage potential as gnd. figure 5.10. voltage reference functional block diagram vref (to adc) adc input mux p0.0/vref r1 vdd external voltage reference circuit gnd temp sensor en 00 01 10 11 ref0cn refsl0 tempe refoe refsl1 refgnd recommended bypass capacitors + 4.7 ? f0 . 1 ? f internal 1.8v regulated digital supply vbat internal 1.65v high speed reference gnd p0.1/agnd 0 1 ground (to adc) refgnd
rev. 0.3 101 si102x/3x 5.10. external voltage reference to use an external voltage reference, refsl[1:0] should be set to 00. bypass capacitors should be added as recommended by the manufacturer of the external voltage reference. if the manufacturer does not pro - vide recommendations, a 4.7uf in parallel with a 0.1uf capacitor is recommended. 5.11. internal voltage reference for applications requiring the maximum number of po rt i/o pins, or very short vref turn-on time, the 1.65 v high-speed reference will be the best internal refere nce option to c h oose. th e high speed internal reference is selected by setting refsl[1:0] to 11. when selected , the high speed intern al reference will be automatically enabled/disabled on an as-needed basis by adc0. for applications with a non-varying power supply voltag e, u s ing the power supply as the voltage reference can provide adc0 with added dynamic range at the cost of reduced power supply noise rejection. to use the 1.8 to 3.6 v power supply voltage (v dd ) or the 1.8 v regulated digital supply voltage as the reference sour ce, refsl[1:0] should be set to 01 or 10, respectively. 5.12. analog ground reference to prevent ground noise generated by switching digi tal logic from affecting sensitive analog measure - ments, a separate analog ground reference option is availa ble. when enabled, the ground reference for adc0 during both the tracking/sampling and the conver sion periods is taken from the p0.1/agnd pin. any external sensors sampled by adc0 should be referenced to the p0.1/agnd pin. this pin should be con - nected to the ground terminal of any external sensors sa mp led by adc0. if an external voltage reference is used, the p0.1/agnd pin should be connected to the ground of the external reference and its associated decoupling capacitor. the separate analog ground reference option is enabled by setting refgnd to 1. note that when sampling the internal temperature sensor, the internal chip ground is always used for the sampling operation, regardless of the setting of the re fgnd bit. similarly, whenever the internal 1.65 v h i gh-speed reference is selected, t he internal chip ground is always used during the conversion period, regardless of the setting of the refgnd bit. 5.13. temperature sensor enable the tempe bit in register ref0cn enables/disables the temperature sensor. while disabled, the temper - ature sensor defaults to a high impedance state a nd a ny adc0 measurements performed on the sensor result in meaningless data. see section ?5.8. temperature sensor? on page 97 for details on temperature sensor characteristics when it is enabled.
si102x/3x 102 rev. 0.3 sfr page = 0x0; sfr address = 0xd1 5.14. voltage reference electrical specifications see ta b l e 4.14 on page 64 for detailed voltage reference electrical specifications. sfr definition 5.15. ref0cn: voltage reference control bit 7 6 5 4 3 2 1 0 name refgnd refsl tempe type r r r/w r/w r/w r/w r r reset 00011000 bit name function 7:6 unused read = 00b; write = don?t care. 5 refgnd analog ground reference. selects the adc0 ground reference. 0: the adc0 ground reference is the gnd pin. 1: the adc0 ground reference is the p0.1/agnd pin. 4:3 refsl voltage reference select. selects the adc0 voltage reference. 00: the adc0 voltage reference is the p0.0/vref pin. 01: the adc0 voltage reference is the vdd pin. 10: the adc0 voltage reference is the internal 1.8 v digital supply voltage. 11: the adc0 voltage reference is the internal 1.65 v high speed voltage reference. 2 tempe temperature sensor enable. enables/disables the internal temperature sensor. 0: temperature sensor disabled. 1: temperature sensor enabled. 1:0 unused read = 00b; write = don?t care.
rev. 0.3 103 si102x/3x 6. comparators si102x/3x devices include two on-chip prog rammable voltage comparators: comparator 0 (cpt0) is show n in figure 6.1 ; comparator 1 (cpt1) is shown in figure 6.2 . the two comparators operate identi - cally, but may differ in their ability to be used as re set or wake-up sources . se e the reset so urces chapter and the power management chapter for details on reset sources and low power mode wake-up sources, respectively. the comparator offers programmable response time a nd hyster esis, an analog input multiplexer, and two outputs that are optionally availabl e at the port pins: a synchronous output (cp0, cp1), or an asynchro - nous output (cp0a, cp1a). the asyn c h ronous cp0a signal is available even when the system clock is not active. this allows the comparator to operate and g enerate an output when the device is in some low power modes. 6.1. comparator inputs each comparator performs an analog comparison of t he voltage levels at its positive (cp0+ or cp1+) and negative (cp0- or cp1-) input. both comparators support multiple port pin inputs multiplexed to their posi - tive and negative comparator inputs using analog in pu t multiple xers. the analog input multiplexers are completely under software control and configured using sfr registers. see ?7.3. comparator0 and comparator1 analog multiplexers? on page 112 for details on how to select and configure comparator inputs. important note about comparator inputs: th e p ort pins selected as comparator inputs should be con - figured as analog inputs and skipped by the crossbar. see "27. port input/output" on page 358 for more details on how to configure port i/o pins as analog in put s. the comparator may also be used to compare the logic level of digital signals, however, port i/o pins configured as digital inputs must be driven to a valid logic state (high or low) to avoid increased power consumption. figure 6.1. comparator 0 functional block diagram vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp0 + px.x cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 rising-edge cp0 falling- edge cp0 interrupt px.x px.x px.x cp0 - (asynchronous) analog input multiplexer
si102x/3x 104 rev. 0.3 6.2. comparator outputs when a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the volta ge at the negative input. when disa bled, the comparator output is a logic 0. the comparator output is synchronized with t he system clock as shown in figure 6.2 . the synchronous output (cp0, cp1) can be polled in software (cpnout bit), used as an interrupt source, or routed to a port pin through the crossbar. the asynchronous comparator output (cp0a, cp1a) is used by the low power mode wakeup logic and reset decision logic. see "19. power management" on page 264 and "22. reset sources" on page 285 for more details on how the asynchronous comparator ou tpu t s are used to make wake-up and reset decisions. the asynchronous comparator output can also be routed directly to a port pin through the crossbar, and is available for use outside the device even if the system clock is stopped. when using a comparator as an interrupt source, comparator interrupts can be generated on rising-edge and/or falling-edge co mparator output transitions. two indepe ndent interrupt flags (cpnrif and cpnfif) allow software to determine which edge caused the comparator interrupt. the comparator rising-edge and falling-edge interrupt flags are set by hardware when a corr esponding edge is detected rega rdless of the interrupt enable state. once set, these bits remain set until cleared by software. the rising-edge and falling-edge interrupts can be in dividu ally enabled using the cpnrie and cpnfie interrupt enable bits in the cptnmd register. in orde r for the cpnrif and/or cpnfif interrupt flags to gen - erate an interrupt request to the cpu, the comparator must be enabled as an interrupt source and global in te rrupts must be enabled. see "17. interrupt handler" on page 238 for additional information. figure 6.2. comparator 1 functional block diagram vdd cpt1cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp1 + px.x cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 cpt1md cp1rie cp1fie cp1md1 cp1md0 cp1 cp1a cp1 rising-edge cp1 falling-edge cp1 interrupt px.x px.x px.x cp1 - (asynchronous) analog input multiplexer
rev. 0.3 105 si102x/3x 6.3. comparator response time comparator response time may be configured in software via the cptnmd registers described on "sfr definition 6.2. cpt0md: comparator 0 mode selection" on page 107 and "sfr definition 6.4. cpt1md: comparator 1 mode selection" on page 109 . four response time settings are available: mode 0 (fastest response time), mode 1, mode 2, and mode 3 (lowest power). selecting a longer response time reduces the comp arator active supply current. the comparators also have low power shutdown state, which is entered any time the compar ator is disabled. compar ator rising edge and fallin g edge response times are typically not equal. see ta b l e 4.16 on page 66 for complete comparator timing and supply current specifi - cations. 6.4. comparator hysterisis the comparators fe ature software-programmable hysterisis that can be used to stabilize the comparator output while a transition is occurr ing on the input. using the cptncn registers, the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going sym - metry of this hysteresis around the threshold vol t age (i.e., the comparator negative input). figure 6.3 shows that when positive hysterisis is enabled, th e comp arator output does not transition from logic 0 to logic 1 until the comparator positive input voltage has exceeded the threshold voltage by an a m ount equal to the programmed hysterisis. it also sh ows that when negative hysterisis is enabled, the comparator output does not transition from logic 1 to logic 0 until the comparator positive input voltage has falle n below the threshold voltage by an amount equal to the programmed hysterisis. the amount of positive hysterisis is determined by th e se ttings of the cpnhyp bits in the cptncn register and the amount of negative hysteresis voltage is de termined by the settings of the cpnhyn bits in the same register. settings of 20 mv, 10 mv, 5 mv, or 0 mv can be programmed for both positive and negative hy steris is. see ?table 4.16. comparator electrical c har acter istics? on page 66 for complete comparator hysterisis specifications. figure 6.3. comparator hysteresis plot positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cpn+ cpn- cpn vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol
si102x/3x 106 rev. 0.3 6.5. comparator register descriptions the sfrs used to enable and configure the comparators are described in the following register descrip - tions. a comparator must be enabled by setting the cpnen bit to logic 1 before it can be used. from an e nab led state, a comparator can be disabled and plac ed in a low power state by clearing the cpnen bit to logic 0. important note about comparator settings: fals e rising and falling edges c an be detected by the com - parator while powering on or if changes are made to th e hystere sis or response time control bits. there - fore, it is recommended t hat the rising-edge and falling-edge flags be explic itl y cleared to logic 0 a short time af ter the comparator is enabled or its mode bits have been changed. the comparator power up time is specified in ta b l e 4.16, ?comparator electrical characteristics,? on page 66 . sfr page= 0x0; sfr address = 0x9b sfr definition 6.1. cpt0cn: comparator 0 control bit 7 6 5 4 3 2 1 0 name cp0en cp0out cp0rif cp0fif cp0hyp[1:0] cp0hyn[1:0] type r/w r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 cp0en comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. 6 cp0out comparator0 output state flag. 0: voltage on cp0+ < cp0 ? . 1: voltage on cp0+ > cp0 ? . 5 cp0rif comparator0 rising-edge flag. must be cleared by software. 0: no comparator0 rising edge has occu rr ed since this flag was last cleared. 1: comparator0 rising edge has occurred. 4 cp0fif comparator0 falling-edge flag. must be cleared by software. 0: no comparator0 falling-e dge has occ urred since this flag was last cleared. 1: comparator0 falling-edge has occurred. 3-2 cp0hyp[1:0] comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1-0 cp0hyn[1:0] comparator0 negative hy st ere sis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv.
rev. 0.3 107 si102x/3x sfr page = 0x0; sfr address = 0x9d sfr definition 6.2. cpt0md: comparator 0 mode selection bit 7 6 5 4 3 2 1 0 name cp0rie cp0fie cp0md[1:0] type r/w r r/w r/w r r r/w reset 1 0 0 0 0 0 1 0 bit name function 7 reserved read = 1b, must write 1b. 6 unused read = 0b, write = don?t care. 5 cp0rie comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. 4 cp0fie comparator0 falling-edge interrupt enable. 0: comparator0 falling-edge interrupt disabled. 1: comparator0 falling-edge interrupt enabled. 3:2 unused read = 00b, write = don?t care. 1:0 cp0md[1:0] comparator0 mode select these bits affect the response time and power consumption for comparator0. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
si102x/3x 108 rev. 0.3 sfr page= 0x0; sfr address = 0x9a sfr definition 6.3. cpt1cn: comparator 1 control bit 7 6 5 4 3 2 1 0 name cp1en cp1out cp1rif cp1fif cp1hyp[1:0] cp1hyn[1:0] type r/w r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 cp1en comparator1 enable bit. 0: comparator1 disabled. 1: comparator1 enabled. 6 cp1out comparator1 output state flag. 0: voltage on cp1+ < cp1 ? . 1: voltage on cp1+ > cp1 ? . 5 cp1rif comparator1 rising-edge flag. must be cleared by software. 0: no comparator1 rising edge has occu rr ed since this flag was last cleared. 1: comparator1 rising edge has occurred. 4 cp1fif comparator1 falling-edge flag. must be cleared by software. 0: no comparator1 falling-e dge has occ urred since this flag was last cleared. 1: comparator1 falling-edge has occurred. 3:2 cp1hyp[1:0] comparator1 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cp1hyn[1:0] comparator1 negative hy st ere sis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv.
rev. 0.3 109 si102x/3x sfr page = 0x0; sfr address = 0x9c sfr definition 6.4. cpt1md: comparator 1 mode selection bit 7 6 5 4 3 2 1 0 name cp1rie cp1fie cp1md[1:0] type r/w r r/w r/w r r r/w reset 1 0 0 0 0 0 1 0 bit name function 7 reserved read = 1b, must write 1b. 6 unused unused. read = 00b, write = don?t care. 5 cp1rie comparator1 rising-edge interrupt enable. 0: comparator1 rising-edge interrupt disabled. 1: comparator1 rising-edge interrupt enabled. 4 cp1fie comparator1 falling-edge interrupt enable. 0: comparator1 falling-edge interrupt disabled. 1: comparator1 falling-edge interrupt enabled. 3:2 unused read = 00b, write = don?t care. 1:0 cp1md[1:0] comparator1 mode select these bits affect the response time and power consumption for comparator1. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
si102x/3x 110 rev. 0.3 7. programmable current reference (iref0) si102x/3x devices include an on-chi p programmable current reference (sou rce or sink) with two output cur - rent settings: low power mode and high current mode. the maximum current output in low power mode is 63 a (1 a steps) and the maximum current output in high current mode is 504 a (8 a steps). the current source/sink is controlled though the iref0c n sp ecial function register. it is enabled by setting the desired output current to a non-zero value. it is di sabled by writing 0x00 to iref0cn. the port i/o pin associated with isrc0 should be configured as an analog input and skipped in the crossbar. see ?port input/output? on page 358 for more details. sfr page = 0x0; sfr address = 0xb9 7.1. pwm enhanced mode the precision of the current reference can be increas ed by fine tuning the iref0 output using a pwm sig - nal generated by the pca. this mode allows the ir ef0da t bits to perform a course adjustment on the iref0 output. any available pca channel can perform a fine adjustment on the iref0 output. when enabled (pwmen = 1), the cex signal selected using the pwmss bit field is internally routed to iref0 to control the on time of a current source having the weight of 2 lsbs. with the two least significant bits of iref0dat set to 00b, applying a 100% duty cycle on the cex signal will be equiva lent to setting the two lsbs of iref0dat to 10b. pwm enhanced mode is enabled and setup using the iref0cf register. sfr definition 7.1. iref0cn: current reference control bit 7 6 5 4 3 2 1 0 name sink mode iref0dat type r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 sink iref0 current sink enable. selects if iref0 is a current source or a current sink. 0: iref0 is a current source. 1: iref0 is a current sink. 6 mdsel iref0 output mode select. selects low power or high current mode. 0: low power mode is selected (step size = 1 a). 1: high current mode is selected (step size = 8 a). 5:0 iref0dat[5:0] iref0 data word. specifies the number of steps required to achieve the desired output current. output current = direction x step size x iref0dat. iref0 is in a low power state wh en i ref0d at is set to 0x00.
rev. 0.3 111 si102x/3x sfr page = 0xf; sfr address = 0xb9 7.2. iref0 specifications see ta b l e 4.15 on page 65 for a detailed listing of iref0 specifications. sfr definition 7.2. iref0cf: current reference configuration bit 7 6 5 4 3 2 1 0 name pwmen pwmss[2:0] type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 pwmen pwm enhanced mode enable. enables the pwm enhanced mode. 0: pwm enhanced mode disabled. 1: pwm enhanced mode enabled. 6:3 unused read = 0000b, write = don?t care. 2:0 pwmss[2:0] pwm source select. selects the pca channel to use fo r th e fine- tuning control signal. 000: cex0 selected as fine-tuning control signal. 001: cex1 selected as fine-tuning control signal. 010: cex2 selected as fine-tuning control signal. 011: cex3 selected as fine-tuning control signal. 100: cex4 selected as fine-tuning control signal. 101: cex5 selected as fine tuning control signal. all other values: reserved.
si102x/3x 112 rev. 0.3 7.3. comparator0 and comparator1 analog multiplexers comparator0 and comparator1 on si102x/3x devices have analog input multiplexers to connect port i/o pins and internal signals the comparator inputs; cp 0+/cp0- are the positive and negative input multiplex - ers for comparator0 and cp1+/cp1- are the positive and negative input multiplexers for comparator1. the comparator input multiplexers directly suppor t cap acitive sensors. when the compare input is selected on the positive or negative multiplexer, any port i/o pin connected to the other multiplexer can be directly connected to a capacitive sensor with no ad ditional external components. the compare signal pro - vides the appropriate reference level for detecting when th e ca pacitive sensor has charged or discharged through the on-chip rsense resistor. the comparator0 ou tput can be routed to timer2 for capturing the capacitor?s charge and discharge time. see section ?33. timers? on page 491 for details. any of the following may be selected as comparator inpu t s: port i/o pins, capacitive touch sense compare, vdd/dc+ supply voltage, regulated digital supply vo ltage (output of vreg0), the vbat supply voltage or ground. the comparator?s supply voltage divided by 2 is also available as an input; the resistors used to divide the voltage only draw current when this setting is selected. the comparator input multiplexers are configured using the cpt0mx and cpt1mx registers described in sfr definition 7.3 and sfr definition 7.4 . figure 7.1. cpn multiplexer block diagram important note about comparator input configuration: port pins selected as comparator inputs should be configured as analog inputs, and should be skipped by the digital crossbar. to configure a port pin for analog input, set to 0 the corresponding bit in register pnmdin and disable the digital driver (pnmdout = 0 and port latch = 1). to force the crossbar to skip a port pin, set to 1 the corresponding bit in register pnskip . see section ?27. port input/output? on page 358 for more port i/o configuration details. cpn- input mux vbat p0.1 vdc + - gnd vbat p0.3 p0.5 p1.5 p1.7 p2.1 p2.3 vbat r r vbat r r cpnout r ? x vbat (1/3 or 2/3) x vbat compare cpn+ input mux digital supply cptnmx cmxnn3 cmxnn2 cmxnn1 cmxnn0 cmxnp3 cmxnp2 cmxnp1 cmxnp0 p0.0 p0.2 p0.4 p0.6 p1.4 p1.6 p2.0 p2.2 vbat r r vbat r r cpnout r ? x vbat (1/3 or 2/3) x vbat cpnout rsense only enabled when compare is selected on cpn+ input mux. cpnout rsense gnd compare only enabled when compare is selected on cpn- input mux.
rev. 0.3 113 si102x/3x sfr page = 0x0; sfr address = 0x9f sfr definition 7.3. cpt0mx: comparator0 input channel select bit 7 6 5 4 3 2 1 0 name cmx0n[3:0] cmx0p[3:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 bit name function 7:4 cmx0n comparator0 negative input selection. selects the negative input channel for comparator0. 0000: p0.1 1000: p2.1 0001: p0.3 1001: p2.3 0010: p0.5 1010: reserved 0011: reserved 1011: reserved 0100: reserved 1100: compare 0101: reserved 1101: vbat divided by 2 0110: p1.5 1110: digital supply voltage 0111: p1.7 1111: ground 3:0 cmx0p comparator0 positive input selection. selects the positive input channel for comparator0. 0000: p0.0 1000: p2.0 0001: p0.2 1001: p2.2 0010: p0.4 1010: reserved 0011: p0.6 1011: reserved 0100: reserved 1100: compare 0101: reserved 1101: vbat divided by 2 0110: p1.4 1110: vbat supply voltage 0111: p1.6 1111: vbat supply voltage
si102x/3x 114 rev. 0.3 sfr page = 0x0; sfr address = 0x9e sfr definition 7.4. cpt1mx: comparator1 input channel select bit 7 6 5 4 3 2 1 0 name cmx1n[3:0] cmx1p[3:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 bit name function 7:4 cmx1n comparator1 negative input selection. selects the negative input channel for comparator1. 0000: p0.1 1000: p2.1 0001: p0.3 1001: p2.3 0010: p0.5 1010: reserved 0011: reserved 1011: reserved 0100: reserved 1100: compare 0101: reserved 1101: vbat divided by 2 0110: p1.5 1110: digital supply voltage 0111: p1.7 1111: ground 3:0 cmx1p comparator1 positive input selection. selects the positive input channel for comparator1. 0000: p0.0 1000: p2.0 0001: p0.2 1001: p2.2 0010: p0.4 1010: reserved 0011: p0.6 1011: reserved 0100: reserved 1100: compare 0101: reserved 1101: vbat divided by 2 0110: p1.4 1110: vbat supply voltage 0111: p1.6 1111: vdc supply voltage
rev. 0.3 115 si102x/3x 8. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft - ware. the mcu family has a superset of all the peri p her als included with a standard 8051. the cip-51 also includes on-chip debug hardware (see description in section 35 ), and interfaces directly with the ana - log and digital subsystems providing a complete data ac qu isitio n or control-system solution in a single inte - grated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional cu stom peripherals and func tions to extend its capability (see figure 8.1 for a block diagram). the cip-51 includes the following features: performance the cip-51 employs a pipelined architecture that grea tly incr eases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all inst ructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core exec ut es 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. figure 8.1. cip-51 block diagram - fully compatible wit h mcs-51 instruction set - 25 mips peak throughput with 25 mhz clock - 0 to 25 mhz clock frequency - extended interrupt handler - reset input - power management modes - on-chip debug logic - program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8
si102x/3x 116 rev. 0.3 with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the to tal number of instructions that require each execu - tion time. programming and debugging support in-system programming of the flash program memory an d co mmunication with on-chip debug support logic is accomplished via the silicon labs 2-wire deve lopment interface (c2). the on-chip debug support logic facilit ates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, a nd reading/writing the conten ts of registers and mem - ory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or ot he r on-chip resources. c2 details can be found in section ?35. c2 interface? on page 533 . the cip-51 is support ed by development tools from silicon labs and third party vendors. silicon labs pro - vides an integrated development environment (ide) in cludin g editor, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via th e c2 interface to provide fast and efficient in-sys - tem device programming and debugging. third party macro assemblers and c compilers are also avail - able. 8.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc - tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 in str uctions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan - dard 8051. 8.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instruction timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most in str uctions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. table 8.1 is the cip-51 instruction set summary, which includes the mn emo nic, number of bytes, and number of clock cycles for each instruction. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1
rev. 0.3 117 si102x/3x table 8.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3
si102x/3x 118 rev. 0.3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 table 8.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles
rev. 0.3 119 si102x/3x anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not eq ua l 3 3/4 cjne @ri, #data, rel compare immediate to indirect and jump if not eq ua l 3 4/5 djnz rn, rel decrement register and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 8.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles
si102x/3x 120 rev. 0.3 notes on registers, operands and addressing modes: rn ?register r0?r7 of the currently selected register bank. @ri ?data ram location addressed indirectly through r0 or r1. rel ?8-bit, signed (twos complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct ?8-bit internal data location?s address. this could be a direct-access data ram location (0x00? 0x7f) or an sfr (0x80?0xff). #data ?8-bit constant #data16 ?16-bit constant bit ?direct-accessed bit in data ram or sfr addr11 ?11-bit destination address used by acall and ajmp. the destination must be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 ?16-bit destination address used by lcall an d ljmp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980.
rev. 0.3 121 si102x/3x 8.2. cip-51 register descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should not be set to logic l. future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default st ate. det ailed descriptions of the remaining sfrs are included in the sections of the data sheet associated with their corresponding sys - tem function. sfr page = all pages; sfr address = 0x82 sfr page = all pages; sfr address = 0x83 sfr definition 8.1. dpl: data pointer low byte bit 7 6 5 4 3 2 1 0 name dpl[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 dpl[7:0] data pointer low. the dpl register is the low byte of the 16 -bit dptr. dptr is used to access indi - rectly addressed flash memory or xram. sfr definition 8.2. dph: data pointer high byte bit 7 6 5 4 3 2 1 0 name dph[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 dph[7:0] data pointer high. the dph register is the high byte of the 16-bit dp tr . dptr is used to access indi - rectly addressed flash memory or xram.
si102x/3x 122 rev. 0.3 sfr page = all pages; sfr address = 0x81 sfr page = all pages; sfr ad dress = 0xe0; bit-addressable sfr page = all pages; sfr ad dr es s = 0xf0; bit-addressable sfr definition 8.3. sp: stack pointer bit 7 6 5 4 3 2 1 0 name sp[7:0] type r/w reset 0 0 0 0 0 1 1 1 bit name function 7:0 sp[7:0] stack pointer. the stack pointer holds the location of the t op of the stack. the stack pointer is incre - mented before every push operation. the sp register defaults to 0x07 after reset. sfr definition 8.4. acc: accumulator bit 7 6 5 4 3 2 1 0 name acc[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 acc[7:0] accumulator. this register is the accumulator for arithmetic operations. sfr definition 8.5. b: b register bit 7 6 5 4 3 2 1 0 name b[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 b[7:0] b register. this register serves as a second accumu la to r for certain arithmetic operations.
rev. 0.3 123 si102x/3x sfr page = all pages; sfr ad dress = 0xd0; bit-addressable sfr definition 8.6. psw: program status word bit 7 6 5 4 3 2 1 0 name cy ac f0 rs[1:0] ov f1 parity type r/w r/w r/w r/w r/w r/w r reset 0 0 0 0 0 0 0 0 bit name function 7 cy carry flag. this bit is set when the last arithmetic oper a tio n resulted in a carry (addition) or a bor - row (subtraction). it is cleared to logi c 0 by a ll other arithmetic operations. 6 ac auxiliary carry flag. this bit is set when the last arithmetic operat ion resulted in a c arry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arith - metic operations. 5 f0 user flag 0. this is a bit-addressable, general purp ose fla g for use under software control. 4:3 rs[1:0] register bank select. these bits select which register bank is used dur ing register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2 ov overflow flag. this bit is set to 1 under the following circumstances: ? an add, addc, or subb instruction causes a sign-change overflow. ? a mul instruction results in an overflow (result is greater than 255). ? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, a ddc, sub b , mul, and div instructions in all other cases. 1 f1 user flag 1. this is a bit-addressable, general purp ose fla g for use under software control. 0 parity parity flag. this bit is set to logic 1 if the sum of the ei gh t b its in the accumulator is odd and cleared if the sum is even.
si102x/3x 124 rev. 0.3 9. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. the memory organization of the si102x/3x device family is shown in figure 9.1 figure 9.1. si102x/3x memory map 9.1. program memory the si1020/24/30/34 devices have a 128 kb program memory space, si1021/25/31/35 devices have a 64 kb program memory space, si1022/26/32/36 devices have a 32 kb program memory space, and si10 23 /27/33/37 devices have a 16 kb program memory space. the devices with 128 kb of program m e mory space implement this as in-system re-programmable flash memory in four 32 kb code banks. a common code bank (bank 0) of 32 kb is always accessible from addresses 0x0000 to 0x7fff. the upper code banks (bank 1, bank 2, and bank 3) are eac h mapped to addresses 0x8000 to 0xffff, depending program/data memory (flash) 128 kb flash (in-system programmable in 1024 byte sectors) 0x00000 0x1ffff (direct and indirect addressing) upper 128 ram (indirect addressing only) special function registers (direct addressing only) data memory (ram) general purpose registers bit addressable lower 128 ram (direct and indirect addressing) internal data address space external data address space xram - 8192 bytes (accessable using movx instruction) 0x0000 0x1fff off-chip xram space (only on 76-pin package) 0x2000 0xffff 2 0 s1020/24/30/34 0x00000 0x0ffff si1021/25/31/35 f 64 kb flash (in-system programmable in 1024 byte sectors) 0x00000 0x07fff si1022/26/32/36 32 kb flash (in-system programmable in 1024 byte sectors) 0x00000 0x03fff si1023/27/33/37 16 kb flash (in-system programmable in 1024 byte sectors) si1020/1/2/4/5/6 si1030/1/2/4/5/6 xram - 4096 bytes (accessable using movx instruction) 0x0000 0x0fff off-chip xram space (only on 76-pin package) 0x1000 0xffff si1023/27/33/37
rev. 0.3 125 si102x/3x on the selection of bits in the psbank register, as described in sfr definition 9.1 . all other devices with 64 kb or less of program memory can be used as non-banked devices. the ifbank bits select which of the upper banks ar e used for code execution, while the cobank bits select the bank to be used for direct writes and reads of the flash memory. the address 0x1ffff (si1020/24/30/34 ), 0xffff (s i1021 /25/31/35), 0x07fff (s i1022/26/32/36), or 0x3fff (si1023/27/33/37) se rves as the security lock byte for th e device. any addresses above the lock byte are reserved. figure 9.2. flash program memory map lock byte 0x00000 flash memory organized in 1024-byte pages flash memory space lock byte page lock byte flash memory space lock byte page 0x0000 0x0fffe 0x0fc00 0x0ffff 0x07fff 0x7ffe 0x07c00 0x07bff 0x0fbff lock byte flash memory space lock byte page 0x0000 0x1fffe 0x1fc00 0x1ffff 0x1fbff si1020/24/30/34 si1021/25/31/35 lock byte 0x00000 flash memory space lock byte page 0x03fff 0x3ffe 0x03c00 0x03bff si1022/26/32/36 si1023/27/33/37
si102x/3x 126 rev. 0.3 figure 9.3. address memory map for instruction fetches bank 0 bank 1 bank 2 bank 3 bank 0 bank 0 bank 0 bank 0 ifbank = 0 ifbank = 1 ifbank = 2 ifbank = 3 internal address 0x 0000 0x7 fff 0x 8000 0 xffff
rev. 0.3 127 si102x/3x sfr page = all pages; sfr address = 0x84 9.1.1. movx instruction and program memory the movx instruction in an 8051 device is typica lly used to access external data memory. on the si102x/3x devices, the movx instruction is normally us ed to read and write on-chip xram, but can be re- configured to write and erase on-chip flash memory sp ace. movc instructions are always used to read flash memory, while movx write instru ctions are used to erase and write flash. this flash access feature provides a mechanism for the si102x/3x to update pr ogram code and use the program memory space for non-volatile data storage. refer to section ?18. flash memory? on page 250 for further details. 9.2. data memory the si102x/3x device family includes 8448 bytes (si1020/21/22/25/26/27/30/31 /35/36/37) or 4352 bytes (si1023/27/33/37) of ram data memory. 256 bytes of th is memory is mapped into the internal ram space sfr definition 9.1. psbank: program space bank select bit 7 6 5 4 3 2 1 0 name cobank[1:0] ifbank[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:6 reserved read = 00b, must write = 00b. 5:4 cobank[1:0] constant operations bank select. these bits select which flash bank is ta r g eted during constant operations (movc and flash movx) involving address 0x8000 to 0xffff. 00: constant operations target bank 0 (n ot e that bank 0 is also mapped between 0x0000 to 0x7fff). 01: constant operations target bank 1. 10: constant operations target bank 2. 11: constant operations target bank 3. 3:2 reserved read = 00b, must write = 00b. 1:0 ifbank[1:0] instruction fetch operations bank select. these bits select which flash bank is used fo r instru ction fetc hes involving address 0x8000 to 0xffff. these bits can only be changed from code in bank 0. 00: instructions fetch from bank 0 (not e th at bank 0 is also mapped between 0x0000 to 0x7fff). 01: instructions fetch from bank 1. 10: instructions fetch from bank 2. 11: instructions fetch from bank 3. note: 1. cobank[1:0] and ifbank[1:0] sho uld not be set to select any bank other than bank 0 (00b) on the si1022/23/26/27/32/33/36/37 devices. 2. cobank[1:0] and ifbank[1:0] sho uld not be set to select bank 2 (10b) or bank 3 (11b) on the si1021/25/31/35 devices.
si102x/3x 128 rev. 0.3 of the 8051. 8192 or 4096 bytes of this memory is on-chip ?external? memory. the data memory map is shown in figure 9.1 for reference. 9.2.1. internal ram there are 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lo we r 128 bytes of data memory are used for general pu rp ose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 thr o ugh 0x1f are addressable as four banks of gene ral purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, ma y eithe r be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by i ndire ct addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or th e sfrs. in str uctions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 9.1 illustrates the data memory or ganization of the si102x /3x. 9.2.1.1. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen - eral-purpose registers. each bank consists of eigh t b y te-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in sfr definition 8.6 ). this allows fast context switching when entering subroutines and inte rr upt service routines. indirect addressing modes use registers r0 and r1 as index registers. 9.2.1.2. bit addressable locations in addition to direct access to data memory organized as bytes, the sixtee n data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x 00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0 x 07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina - tion). the mcs-51? assembly language allows an alternate no t ation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 9.2.1.3. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig - nated using the stack pointer (sp) sfr. the sp will point to the last lo cation used. the next value pushed on the stack is placed at sp+1 and then sp is incremen ted. a reset initializes the stack pointer to location 0x07. therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis - ter (r0) of register bank 1. thus, if mo re than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. 9.2.2. external ram there are 8192 bytes or 4096 bytes of on-chip ram mapped into the external data memory space. all of the s e address locations may be accessed using the external move instruction (movx) and the data pointer (dptr), or using movx indirect addressing mo de (such as @r1) in combination with the emi0cn register. additional off-chip memory or memory-mapped devices may be mapped to the external memory
rev. 0.3 129 si102x/3x address space and accessed using the external memory interface. see section ?10. external data mem - ory interface and on-chip xram? on page 130 for further details.
si102x/3x 130 rev. 0.3 10. external data memory interface and on-chip xram an external memory interface (emif) is available on the si102x/3x devices, which can be used to access off-chip data memories and memory-mapped devices connected to the gpio ports. the external memory space may be accessed using the external move inst ruction (movx) and the data pointer (dptr), or using the movx indirect addressing mode using r0 or r1. if the movx instruction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bi t address is provided by the external memory inter - face control register (emi0cn, shown in sfr definition 10.1 ). note: the movx instruction can also be used for writing to the flash memory. see section ? 18. flash memory ? on page 250 for details. the movx instru ction accesses xram by default. 10.1. accessing xram the xram memory space is accessed using the mo vx instruction. the movx instruction has two forms, both of which use an indirect addressing method. th e first method uses the data pointer, dptr, a 16-bit register which contains the effective address of the xram location to be read from or written to. the sec - ond method uses r0 or r1 in combination with the emi0 cn re gister to generate the effective xram address. examples of both of these methods are given below. 10.1.1. 16-bit movx example the 16-bit form of the movx instructi on acce sses the memory location po inted to by the contents of the dptr register. the following series of instructions reads the value of the byte at address 0x1234 into the accumulator a: mov dptr, #1234h ; load dptr with 16-bit address to read (0x1234) movx a, @dptr ; load contents of 0x1234 into accumulator a ? the above example uses the 16-bit immed i ate mov instruction to set th e contents of dptr. alternately, the dptr can be accessed through the sfr registers dph, which contains the upper 8-bits of dptr, and dpl, which contains the lower 8-bits of dptr. 10.1.2. 8-bit movx example the 8-bit form of the movx instruction uses the content s o f the emi0cn sfr to determine the upper 8-bits of the effective address to be accessed and the contents of r0 or r1 to determine the lower 8-bits of the effective address to be accessed. the following series of instructions read the contents of the byte at address 0x1234 into the accumulator a. mov emi0cn, #12h ; load high byte of address into emi0cn mov r0, #34h ; load low byte of address into r0 (or r1) movx a, @r0 ; load contents of 0x1234 into accumulator a
rev. 0.3 131 si102x/3x 10.2. configuring the ex ternal memory interface configuring the emif consists of five steps: 1. configure the output modes of the associated port p i ns as either push-pull or open-drain (push-pull is most common). the input mode of the associated port pins should be set to digital (reset value). 2. configure port latches to ?park? the emif pins in a dormant state (usually by setting them to logic 1). 3. select multiplexed mode or non-multiplexed mode. 4. select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or off-chip only). 5. set up timing to interface with off-chip memory or peripherals. each of these five steps is explained in detail in th e followin g sections. the po rt selection, multiplexed mode selection, and mode bits are located in the emi0cf register shown in sfr definition . 10.3. port configuration the emif appears on ports 3, 4, 5, and 6 when it is used for off-chip memory access. the emif and the lcd cannot be used simultaneously. when using emif, all pins on ports 3-6 may only be used for emif purposes or as general purpose i/o. the emif pinout is shown in ta b l e 10.1 on page 132 . the emif claims the associated port pins for memory operations only during the execution of an off-chip movx in struction. once the movx inst ruction has completed, control of the port pins reverts to the port latches or to the crossbar settings for those pins. see section ?27. port input/output? on page 358 for more information about the crossbar and po rt ope ra tion and configuration. the port latches should be explic - itly configured to ?park? the emif pins in a dormant state, most commonly by setting them to a logic 1. during the execution of the mov x ins truction, the emif will explicit ly disable the drivers on all port pins that are acting as inputs (data[7:0] during a read operation, for example). the output mode of the port pins (whether the pin is configured as open-drain or push-pull) is unaffected by the emif operation, and remains controlled by the pnmdout registers. in most cases, the output modes of all emif pins should be configured for push-pull mode. the si102x/3x devices support both the multiplexed and non-multiplexed modes.
si102x/3x 132 rev. 0.3 table 10.1. emif pinout multiplexed mode non multiplexed mode signal name port pin s ignal name port pin 8-bit mode 1 16-bit mode 2 8-bit mode 1 16-bit mode 2 rd p3.6 p3.6 rd p3.6 p3.6 wr p3.7 p3.7 wr p3.7 p3.7 ale p3.5 p3.5 d0 p6.0 p6.0 ad0 p6.0 p6.0 d1 p6.1 p6.1 ad1 p6.1 p6.1 d2 p6.2 p6.2 ad2 p6.2 p6.2 d3 p6.3 p6.3 ad3 p6.3 p6.3 d4 p6.4 p6.4 ad4 p6.4 p6.4 d5 p6.5 p6.5 ad5 p6.5 p6.5 d6 p6.6 p6.6 ad6 p6.6 p6.6 d7 p6.7 p6.7 ad7 p6.7 p6.7 a0 p5.0 p5.0 a8 ? p5.0 a1 p5.1 p5.1 a9 ? p5.1 a2 p5.2 p5.2 a10 ? p5.2 a3 p5.3 p5.3 a11 ? p5.3 a4 p5.4 p5.4 a12 ? p5.4 a5 p5.5 p5.5 a13 ? p5.5 a6 p5.6 p5.6 a14 ? p5.6 a7 p5.7 p5.7 a15 ? p5.7 a8 ? p4.0 ??? a 9?p 4 . 1 ? ? ? a10 ? p4.2 ??? a 1 1?p 4 . 3 ? ? ? a12 ? p4.4 ? ? ? a13 ? p4.5 ? ? ? a14 ? p4.6 ? ? ? a15 ? p4.7 required i/o: 11 19 required i/o: 18 26 notes: 1. using 8-bit movx instructi on witho ut bank select. 2. using 16-bit movx instruction.
rev. 0.3 133 si102x/3x sfr page = 0x0; sfr address = 0xaa sfr definition 10.1. emi0cn: external memory interface control bit 7 6 5 4 3 2 1 0 name pgsel[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pgsel[7:0] xram page select bits. the xram page select bits provide the high byte of th e 16 -bit external data memory address when using an 8-bit movx command, ef fectively selecting a 256-byte page of ram. 0x00: 0x0000 to 0x00ff 0x01: 0x0100 to 0x01ff ... 0xfe: 0xfe00 to 0xfeff 0xff: 0xff00 to 0xffff
si102x/3x 134 rev. 0.3 sfr page = 0x0; sfr address = 0xab sfr definition 10.2. emi0cf: external me mory configuration bit 7 6 5 4 3 2 1 0 name emd2 emd[1:0] eale[1:0] type r/w reset 0 0 0 0 0 0 1 1 bit name function 7:5 unused read = 000b; write = don?t care. 4 emd2 emif multiplex mode select bit. 0: emif operates in multiplexed address/data mode 1: emif operates in non-multiplexed mode (separate address and data pins) 3:2 emd[1:0] emif operating m ode select bi t s. 00: internal only: movx accesses on-chip xram on ly . all effective addresses alias to on-chip memory space 01: split mode without bank select: accesses below the 8 kb boundary are directed on-chip. accesses above t he 8 kb boundary are directed off-chip. 8-bit off-chip movx ope ra tions use current contents of the addres s high port latches to resolve the upper address byte. to access off chip space, emi0cn must be set to a page that is not con - tained in the on-chip address space. 10: split mode with bank select: accesses below the 8 kb boundary are directed on- c h ip. accesses above the 8 kb boundary are directed off-chip. 8-bit off-chip movx ope ra tions uses the contents of emi0cn to determine the high-byte of the address. 11: external only: movx access es off-chip xram only. on-chip xram is not visible to the cpu. 1:0 eale[1:0] ale pulse-width select bits. these bits only have an effect when emd2 = 0. 00: ale high and ale low pu lse wid t h = 1 sysclk cycle. 01: ale high and ale low pu lse wid t h = 2 sysclk cycles. 10: ale high and ale low pu lse wid t h = 3 sysclk cycles. 11: ale high and ale low pulse width = 4 sysclk cycles.
rev. 0.3 135 si102x/3x 10.4. multiplexed and n on-multiplexed selection the external memory interface is capable of acting in a multiplexed mode or non-multiplexed mode, depending on the state of the emd2 (emi0cf.4) bit. 10.4.1. mult iplexe d configuration in multiplexed mode, the data bus and the lower 8 bits of the address bus share the same port pins: ad[7:0]. in this mode, an external latch (74hc373 or equivalent logic gate) is used to hold the lower 8 bits of the ram address. the external latch is controlled by the ale (address latch enable) signal, which is driven by the emif logic. an example of a multiplexed configuration is shown in figure 10.1 . in multiplexed mode, the external movx operation can b e broken into two phases delineated by the state of the ale signal. during the first phase, ale is high and the lower 8 bits of the address bus are presented to ad[7:0]. during this phase, the address latch is configured such that the q outputs reflect the states of the d inputs. when ale falls, signa ling the beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch inputs. later in the second phase, the data bus con - trols the state of the ad[7:0] port at the time rd or wr is asserted. see section ?10.6.2. multiplexed mode? on page 143 for more information. figure 10.1. multiplexed configuration example 10.4.2. non-multiplexed configuration in non-multiplexed mode, the data bus and the addre ss bus pins are not shared. an example of a non- multiplexed configuration is shown in figure 10.2 . see section ?10.6.1. non-multiplexed mode? on page 140 for more information about non-multiplexed operation. address/data bus address bus e m i f a[15:8] ad[7:0] wr rd ale 64 k x 8 sram oe we i/o[7:0] 74hc373 g dq a[15:8] a[7:0] ce v dd 8 (optional)
si102x/3x 136 rev. 0.3 figure 10.2. non-multiplexed configuration example 10.5. memory mode selection the external data memory space can be configured in one of four modes, shown in figure 10.3 , based on the emif mode bits in the emi0cf register ( sfr definition 10.2 ). these modes are summarized below. more information about the different modes can be found in section ?10.6. timing? on page 138 . figure 10.3. emif operating modes address bus e m i f a[15:0] 64 k x 8 sram a[15:0] data bus d[7:0] i/o[7:0] v dd 8 wr rd oe we ce (optional) emi0cf[3:2] = 00 0xffff 0x0000 emi0cf[3:2] = 11 0xffff 0x0000 emi0cf[3:2] = 01 0xffff 0x0000 emi0cf[3:2] = 10 on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram off-chip memory (no bank select) on-chip xram 0xffff 0x0000 off-chip memory (bank select) on-chip xram off-chip memory
rev. 0.3 137 si102x/3x 10.5.1. intern al xram only when bits emi0cf[3:2] are set to 00, all movx instructions will target the internal xram space on the device. memory accesses to addresses be yond the populated space will wrap on 8 kb boundaries. as an e x ample, the addresses 0x2000 and 0x4000 both evaluate to address 0x0000 in on-chip xram space. ? 8-bit movx operations use the contents of emi0cn to determine the high-byte of the effective address and r0 or r1 to determine the lo w-byte of the effective address. ? 16-bit movx operations use the contents of the 16-bit dptr to determine the effective address. 10.5.2. split mode without bank select when bit emi0cf.[3:2] are set to 01, the xram memory map is split into two areas, on-chip space and off- chip space. ? effective addresses below the in ternal xram size boundary will access on-chip xram space. ? effective addresses above the internal xram size boundary will access off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on- chip or off-chip. however, in th e ?no bank select? mode, an 8-bi t movx operation will not drive the upper 8-bits a[15:8] of the address bus during an off-chip access. this allows the user to manipulate the upper address bits at will by setting the port state directly via the port latc hes. this behavior is in contrast with ?split mode with bank select? described below. the lower 8-bits of the address bus a[7:0] are driven, determined by r0 or r1. ? 16-bit movx operations use the contents of dptr to determine whether the memory access is on-chip or off-chip, and unlike 8-bit movx operations, the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction. 10.5.3. split mode wi th bank select when emi0cf[3:2] are set to 10, the xram memory map is split into two areas, on-chip space and off- chip space. ? effective addresses below the in ternal xram size boundary will access on-chip xram space. ? effective addresses above the internal xram size boundary will access off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on- chip or off-chip. the upper 8-bits of the address bus a[15:8] are determined by emi0cn, and the lower 8-bits of the address bus a[7:0] are determined by r0 or r1. all 16-bits of the address bus a[15:0] are driven in ?bank select? mode. ? 16-bit movx operations use the contents of dptr to determine whether the memory access is on-chip or off-chip, and the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction. 10.5.4. external only when emi0cf[3:2] are set to 11, all movx operations are dir e cted to off-chip space. on-chip xram is not visible to the cpu. this mode is useful for accessing off-chip memo ry located between 0x0000 and the internal xram size boundary. ? 8-bit movx operations ignore the contents of emi0 cn. the upper address bits a[15:8] are not driven (identical behavior to an off-chip access in ?split mode without bank select? described above). this allows the user to manipulate the up per address bits at will by setting the port state directly. the lower 8-bits of the effective address a[7:0] are determined by the contents of r0 or r1. ? 16-bit movx operations use the contents of dptr to determine the effective address a[15:0]. the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction.
si102x/3x 138 rev. 0.3 10.6. timing the timing parameters of the emif can be configur ed to enable connection to devices having different setup and hold time requirements. the address setup time, address hold time, rd and wr strobe widths, and in multiplexed mode, the width of the ale pulse are all programm able in units of sysclk periods through emi0tc, shown in sfr definition 10.3 , and emi0cf[1:0]. the timing for an off-chip movx instruction can be calculate d by adding 4 sysclk cycles to the timing parameters defined by the emi0tc register. assuming non-multiplexed operation, the minimum execution time for an off-chip xram operat ion is 5 sysclk cyc les (1 sysclk for rd or wr pulse + 4 sysclks). for multiplexed operations , the address latch enable signal will re quire a minimum of 2 additional sys - clk cycles. therefore, the minimum exec ution time f or an off-chip xram operation in multiplexed mode is 7 sysclk cycles (2 for /ale + 1 for rd or wr + 4). the programmable setup and hold times default to the maximum delay settings after a reset. ta b l e 10.2 lists the ac parameters for the emif, and figure 10.4 through figure 10.9 show the timing diagrams for the diff e r ent emif modes and movx operations.
rev. 0.3 139 si102x/3x sfr page = 0x0; sfr address = 0xaf sfr definition 10.3. emi0tc: external me mory ti ming control bit 7 6 5 4 3 2 1 0 name eas[1:0] ewr[3:0] eah[1:0] type r/w r/w r/w reset 1 1 1 1 1 1 1 1 bit name function 7:6 eas[1:0] emif address setup time bits. 00: address setup time = 0 sysclk cycles. 01: address setup time = 1 sysclk cycle. 10: address setup time = 2 sysclk cycles. 11: address setup time = 3 sysclk cycles. 5:2 ewr[3:0] emif wr and rd pulse-width control bits. 0000: wr and rd pulse width = 1 sysclk cycle. 0001: wr and rd pulse width = 2 sysclk cycles. 0010: wr and rd pulse width = 3 sysclk cycles. 0011: wr and rd pulse width = 4 sysclk cycles. 0100: wr and rd pulse width = 5 sysclk cycles. 0101: wr and rd pulse width = 6 sysclk cycles. 0110: wr and rd pulse width = 7 sysclk cycles. 0111: wr and rd pulse width = 8 sysclk cycles. 1000: wr and rd pulse width = 9 sysclk cycles. 1001: wr and rd pulse width = 10 sysclk cycles. 1010: wr and rd pulse width = 11 sysclk cycles. 1011: wr and rd pulse width = 12 sysclk cycles. 1100: wr and rd pulse width = 13 sysclk cycles. 1101: wr and rd pulse width = 14 sysclk cycles. 1110: wr and rd pulse width = 15 sysclk cycles. 1111: wr and rd pulse width = 16 sysclk cycles. 1:0 eah[1:0] emif address hold time bits. 00: address hold time = 0 sysclk cycles. 01: address hold time = 1 sysclk cycle. 10: address hold time = 2 sysclk cycles. 11: address hold time = 3 sysclk cycles.
si102x/3x 140 rev. 0.3 10.6.1. non-multiplexed mode 10.6.1.1. 16-bit movx: emi0 cf[4:2] = 101, 110, or 111 figure 10.4. non-multiplexed 16-bit movx timing emif address (8 msbs) from dph emif address (8 lsbs) from dpl emif write data t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] wr rd emif address (8 msbs) from dph emif address (8 lsbs) from dpl t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] rd wr emif read data nonmuxed 16-bit write nonmuxed 16-bit read p2
rev. 0.3 141 si102x/3x 10.6.1.2. 8-bit movx without bank select: emi0cf[4:2] = 101 or 111 figure 10.5. non-multiplexed 8-bit movx without bank select timing emif address (8 lsbs) from r0 or r1 emif write data t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] wr rd emif address (8 lsbs) from r0 or r1 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] rd wr emif read data nonmuxed 8-bit write without bank select nonmuxed 8-bit read without bank select
si102x/3x 142 rev. 0.3 10.6.1.3. 8-bit mo vx with bank select: emi0cf[4:2] = 110 figure 10.6. non-multiplexed 8-bit movx with bank select timing emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 emif write data t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] wr rd emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] rd wr emif read data nonmuxed 8-bit write with bank select nonmuxed 8-bit read with bank select
rev. 0.3 143 si102x/3x 10.6.2. mult iplexed mode 10.6.2.1. 16-bit movx: emi0 cf[4:2] = 001, 010, or 011 figure 10.7. multiplexed 16-bit movx timing addr[15:8] ad[7:0] t ach t wdh t acw t acs t wds ale wr rd emif address (8 msbs) from dph emif write data emif address (8 lsbs) from dpl t aleh t alel addr[15:8] ad[7:0] t ach t acw t acs ale rd wr emif address (8 msbs) from dph emif address (8 lsbs) from dpl t aleh t alel t rdh t rds emif read data muxed 16-bit write muxed 16-bit read
si102x/3x 144 rev. 0.3 10.6.2.2. 8-bit movx without bank select: emi0cf[4:2] = 001 or 011 figure 10.8. multiplexed 8-bit movx without bank select timing addr[15:8] ad[7:0] t ach t wdh t acw t acs t wds ale wr rd emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel addr[15:8] ad[7:0] t ach t acw t acs ale rd wr emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write without bank select muxed 8-bit read without bank select
rev. 0.3 145 si102x/3x 10.6.2.3. 8-bit mo vx with bank select: emi0cf[4:2] = 010 figure 10.9. multiplexed 8-bit movx with bank select timing addr[15:8] ad[7:0] t ach t wdh t acw t acs t wds ale wr rd emif address (8 msbs) from emi0cn emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel addr[15:8] ad[7:0] t ach t acw t acs ale rd wr emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write with bank select muxed 8-bit read with bank select
si102x/3x 146 rev. 0.3 table 10.2. ac parameters for external memory interface parameter description min* max* units t acs address/control setup time 0 3 x t sysclk ns t acw address/control pulse width 1 x t sysclk 16 x t sysclk ns t ach address/control hold time 0 3 x t sysclk ns t aleh address latch enable high time 1 x t sysclk 4 x t sysclk ns t alel address latch enable low time 1 x t sysclk 4 x t sysclk ns t wds write data setup time 1 x t sysclk 19 x t sysclk ns t wdh write data hold time 0 3 x t sysclk ns t rds read data setup time 20 ns t rdh read data hold time 0 ns *note: t sysclk is equal to one per iod of the device syst em clock (sysclk).
rev. 0.3 147 si102x/3x 11. direct memory access (dma0) an on-chip direct memory access (dma0) is inclu ded on the si102x/3x devi ces. the dma0 subsystem allows autonomous variable-length data transfers between xram and peripheral sfr registers without cpu intervention. during dma0 operation, the cpu is free to perform some other tasks. in order to save total system power consumption, the cpu and flas h can be powered down. dm a0 improves the system performance and efficiency with hi gh data throughput peripherals. dma0 contains seven independent channels, common co ntro l registers, and a dma0 engine (see figure 11.1 ). each channel includes a register that assign s a p e ripheral to the channel, a channel control register, and a set of sfrs that in clu de xram address information an d sfr address information used by the channel during a data transfer. the dma0 architecture is descr ibed in detail in section 11.1 . the dma0 in si102x/3x devices su pports four peripherals: aes0, enc0, crc1, and spi1. peripherals with dma0 capability should be conf igured to work with the dma0 thro ugh their own registers. the dma0 provides up to seven channels, and each channel can be configured for one of nine possible data transfer functions: ? xram to enc0l/m/h ? enc0l/m/h sfrs to xram ? xram to crc1in sfr ? xram to spi1dat sfr ? spi1dat sfr to xram ? xram to aes0kin sfr ? xram to aes0bin sfr ? xram to aes0xin sfr ? aes0yout sfr to xram the dma0 subsystem signals the mcu through a set of i n terrupt service routine flags. interrupts can be generated when the dma0 transfers half of the data length or full data length on any channel.
si102x/3x 148 rev. 0.3 figure 11.1. dma0 block diagram 11.1. dma0 architecture the first step in configuring a dma0 channel is to select the desired channel for data transfer using dma0sel[2:0] bits (dma0sel ). after setting the dma0 channel, fi rmware can address channel-specific registers such as dma0ncf, dm a0nbah/l, dma0naoh/l, and dma0ns zh/l. once firmware selects a channel, the subsequent sfr configuration applies to the dma0 transfer of that selected channel. each dma0 channel consists of an sfr assigning the ch an nel to a peripheral, a channel control register and a set of sfrs that describe xram and sfr add resses to be used during data transfer (see figure 11.1 ). the peripheral assignment bits of dma0ncf se lect one of the eight data transfer functions. the selected channel can choose the desired function b y writing to the periph[2:0] bits (dma0ncf[2:0]). the control register dma0ncf of each channel configures the endian-ness of the data in xram, stall e nab le, full-length interrupt enable and mid-point interrupt enable. when a channel is stalled by setting the stall bit (dma0ncf.5), dma0 tran sfers in progress will not be aborted, but new dma0 transfers will be blocked until the stall status of the channel is reset. af ter the stall bit is set, so ftware should poll the corre - sponding dma0busy to verify that there ar e no mo re dma transfers for that channel. the memory interface configuration sf rs of a chan nel define the linear region of xram involved in the transfer through a 12-bit base address register dma0nbah:l, a 10-bit address offset register dma0naoh:l and a 10-bit data transfer size dma0nszh:l. the effective memory address is the address involved in the current dma0 transaction. effective memory address = base address + address offset the address offset serves as byte counter. the addres s of fset should be always less than data transfer length. the address offset increments by one after ea ch byte transferred. for dma0 configuration of any channel, address offsets of active channels s hould be reset to 0 before dma0 transfers occur. internal dma bus control xram to enc0 request enc0 to xram request xram to crc1 request xram to spi1 request spi1 to xram request xram to aes0kin request xram to aes0bin request xram to aes0xin request channel memory interface config channel control channel 0 channel 1 channel 6 ... peripheral assignment - dma0ncf[2:0] dma0en dma0int dma0mint dma0busy dma0sel dma0sel[0] ch0_en ch1_en ch2_en ch3_en ch4_en ch5_en ch6_en ch0_int ch1_int ch2_int ch3_int ch4_int ch5_int ch6_int ch0_mint ch1_mint ch2_mint ch3_mint ch4_mint ch5_mint ch6_mint ch0_busy ch1_busy ch2_busy ch3_busy ch4_busy ch5_busy ch6_busy dma0sel[0] dma0sel[1] dma0sel[2] common control/ status dma engine minten stall inten endian periph2 dma0ncf periph0 periph1 dma0nbah dma0nbal dma0naoh dma0naol dma0nszh dma0nszl aes0yout to xram request dma0nmd wrap periph3
rev. 0.3 149 si102x/3x data transfer size dma0nszh:l de fines the maximum number of bytes for the dma0 transfer of the selected channel. if the address offset reaches data tr ansfer size, the fu ll-length interrupt flag bit chn_int (dma0int) of the selected channel will be asserted. similarly, the mid-point interrup t flag bit chn_mint is set when the address offset is equal to half of data transf er size if the transfer size is an even number or when the address offset is equal to half of the transfer size plus one if the transfer size is an odd number. interrupt flags must be cleared by software so that the next dma0 data transfer can proceed. the dma0 subsystem permits data transfer between sfr registers and xram. the dma0 subsystem executes its task based on settings of a channel?s control and memory interface configuration sfrs. when data is copied from xram to sfr re gisters, it takes two cycles for dm a0 to read from xram and the sfr write occurs in the second cycle. if mo re than one byte is involved, a pipe line is used. when data is copied from sfr registers to xram, the dma0 only requires one cycle for one byte transaction. the selected dma0 channel for a peripheral should be enabled through the enable bits chn_en ( d ma0en.n) to allow the dma0 to transfer the data. when the dma0 is transferring data on a channel, the busy status bit of the channel chn_busy (dma0bus y.n) is set. during the transaction, writes to dma0nszh:l, dma0nbah:l, and dma0naoh:l are disabled. each peripheral is responsible for asserting the periph era l transfer requests necessary to service the par - ticular peripheral. some peripherals may have a complex state machine to manage the peripheral request s . please refer to the dm a enabled peripheral chap ters for additional in formation (aes0, crc1, enc0 and spi1). besides reporting transaction status of a channel, dm a0bu sy can be used to force a dma0 transfer on an already configured channel by setting the chn_busy bit (dma0busy.n). the dma0nmd sfr has a wrap bit that supports addr ess o ffset wrapping. the size register dma0nsz sets the transfer size. normally the address offset starts at zero and increases until it reaches size minus one. at this point the transfer is complete and the interrupt bit will be set. when the wrap bit is set, the address offset will automatically be reset to zero and tr ansfers will continue as lo ng as the peripheral keeps requesting data. the wrap feature can be used to support key wrapping for the aes0 mo dule. normally the same key is used over and over with additional data blocks. so the wrap bit should be set when using the xram to aes0kin request. this feat ure supports multiple-blo ck encryption operations. 11.2. dma0 arbitration 11.2.1. dma0 memory access arbitration if both dma0 and cpu attempt to a ccess sfr re gister or xram at the same time, the cpu pre-empts the dma0 module. dma0 will be stalled unt il cpu completes its bus activity. 11.2.2. dma0 channel arbitration multiple dma0 channels can request transfer simu ltaneously, but only one dma0 channel will be granted the bus to transfer the data. channel 0 has the highes t priority. dma0 channels are serviced based on their priority. a higher priority channel is serviced first. channel arbitration occu rs at the end of the data transfer granularity (transaction boundary) of the dma. when there is a dma0 request at the transaction boundary from higher priority channe l, lower priority ones will be stalled unt il the highest priority one completes its transaction. so, for 16-bit transfers, the transaction boundary is at every 2 bytes. 11.3. dma0 operation in low power modes dma0 remains functional in normal active, low power ac tive, idle, low power idle modes but not in sleep or suspend mode. cpu will wait for dma0 to complete a ll pending requests before it ente rs sleep mode. when the system wakes up from suspend or sleep mode to normal active mode, pending dma0 interrupts will be serviced according to priority of channel s. dma0 stalls when cpu is in debug mode.
si102x/3x 150 rev. 0.3 11.4. transfer configuration the following steps are required to configure one of the dma0 channels for operation: 1. select the channel to be configured by writing dma0sel. 2. specify the data transfer function by writing dma0 ncf. this register also specifies the endian-ness of the data in xram and enables full or mid-point interrupts. 3. configure the wrapping mode by writing to dma0nmd. setting th is bit will automatically reset the address offset after each completed transfer. 4. specify the base address in xram for the transfer by writing dma0nbah:l. 5. specify the size of the transfer in bytes by writing dma0nszh:l. 6. reset the address offset coun ter by writing 0 to dma0naoh:l. 7. enable the dma0 channel by writing 1 to the appropriate bit in dma0en.
rev. 0.3 151 si102x/3x sfr page = 0x2; sfr address = 0xd2 sfr definition 11.1. dma0en: dma0 channel enable bit 7 6 5 4 3 2 1 0 name ch6_en ch5_en ch4_en ch3_en ch2_en ch1_en ch0_en type r r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 unused read = 0b, write = don?t care 6 ch6_en channel 6 enable. 0: disable dma0 channel 6. 1: enable dma0 channel 6. 5 ch5_en channel 5 enable. 0: disable dma0 channel 5. 1: enable dma0 channel 5. 4 ch4_en channel 4 enable. 0: disable dma0 channel 4. 1: enable dma0 channel 4. 3 ch3_en channel 3 enable. 0: disable dma0 channel 3. 1: enable dma0 channel 3. 2 ch2_en channel 2 enable. 0: disable dma0 channel 2. 1: enable dma0 channel 2. 1 ch1_en channel 1 enable. 0: disable dma0 channel 1. 1: enable dma0 channel 1. 0 ch0_en channel 0 enable. 0: disable dma0 channel 0. 1: enable dma0 channel 0.
si102x/3x 152 rev. 0.3 sfr page = 0x2; sfr address = 0xd3 sfr definition 11.2. dma0int: dma0 full-length interrupt bit 7 6 5 4 3 2 1 0 name ch6_int ch5_int ch4_int ch3_int ch2_int ch1_int ch0_int type r r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 unused read = 0b, write = don?t care 6 ch6_int channel 6 full-lengt h int errupt flag. 1 0: full-length interrupt has not occured on channel 6. 1: full-length interrupt has not occured on channel 6. 5 ch5_int 0: full-length interrupt has not occured on channel 5. 1: full-length interrupt has not occured on channel 5. 4 ch4_int channel 4 full-lengt h int errupt flag. 1 0: full-length interrupt has not occured on channel 4. 1: full-length interrupt has not occured on channel 4. 3 ch3_int channel 3 full-lengt h int errupt flag. 1 0: full-length interrupt has not occured on channel 3. 1: full-length interrupt has not occured on channel 3. 2 ch2_int channel 2 full-lengt h int errupt flag. 1 0: full-length interrupt has not occured on channel 2. 1: full-length interrupt has not occured on channel 2. 1 ch1_int channel 1 full-lengt h int errupt flag. 1 0: full-length interrupt has not occured on channel 1. 1: full-length interrupt has not occured on channel 1. 0 ch0_int channel 0 full-lengt h int errupt flag. 1 0: full-length interrupt has not occured on channel 0. 1: full-length interrupt has not occured on channel 0. note: 1.full-length interrupt flag is set when the offset addr ess dma0naoh/l is equal to the data transfer size dma0nszh/l minus 1. this flag must be cleared by software or system reset. the full-l ength interrupt is enabled by setting bit 7 of dma0ncf with dma0sel configured for the corresponding channel.
rev. 0.3 153 si102x/3x sfr page = 0x2; sfr address = 0xd4 sfr definition 11.3. dma0mint: dma0 mid-point interrupt bit 7 6 5 4 3 2 1 0 name ch6_mint ch5_mint ch4_mint ch3_mint ch2_mint ch1_mint ch0_mint type r r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 unused read = 0b, write = don?t care 6 ch6_mint channel 6 mid-poin t int errupt flag. 0: mid-point interrupt has not occured on channel 6. 1: mid-point interrupt has not occured on channel 6. 5 ch5_mint channel 5 mid-poin t int errupt flag. 0: mid-point interrupt has not occured on channel 5. 1: mid-point interrupt has not occured on channel 5. 4 ch4_mint channel 4 mid-poin t int errupt flag. 0: mid-point interrupt has not occured on channel 4. 1: mid-point interrupt has not occured on channel 4 . 3 ch3_mint channel 3 mid-poin t int errupt flag. 0: mid-point interrupt has not occured on channel 3. 1: mid-point interrupt has not occured on channel 3. 2 ch2_mint channel 2 mid-poin t int errupt flag. 0: mid-point interrupt has not occured on channel 2. 1: mid-point interrupt has not occured on channel 2. 1 ch1_mint channel 1 mid-poin t int errupt flag. 0: mid-point interrupt has not occured on channel 1. 1: mid-point interrupt has not occured on channel 1. 0 ch0_mint channel 0 mid-poin t int errupt flag. 0: mid-point interrupt has not occured on channel 0. 1: mid-point interrupt has not occured on channel 0. note: mid-point interrupt flag is set when the offset address dma0naoh/l is equal to half of the data transfer size dma0nszh/l if the transfer size is an even number or half of data transfer size dma0nszh/l plus one if the transfer size is an odd nu mber. this flag must be cleared by softwa re or system reset.the mid-point interrupt is enabled by setting bit 6 of dma0ncf with dm a0sel configured for the corresponding channel.
si102x/3x 154 rev. 0.3 sfr page = 0x2; sfr address = 0xd5 sfr definition 11.4. dma0busy: dma0 busy bit 7 6 5 4 3 2 1 0 name ch6_busy ch5_busy ch4_busy ch3_busy ch2_busy ch1_busy ch0_busy type r r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name description write read 7 unused no effect. always reads 0. 6 ch6_busy channel 6 busy. 0: no effect. 1: force dma0 transfer to st ar t on channel 6. 0: dma0 channel 6 idle. 1: dma0 transfer in prog - ress on channel 6. 5 ch5_busy channel 5 busy. 0: no effect. 1: force dma0 transfer to st ar t on channel 5. 0: dma0 channel 5 idle. 1: dma0 transfer in prog - ress on channel 5. 4 ch4_busy channel 4 busy. 0: no effect. 1: force dma0 transfer to st ar t on channel 4. 0: dma0 channel 4 idle. 1: dma0 transfer in prog - ress on channel 4. 3 ch3_busy channel 3 busy. 0: no effect. 1: force dma0 transfer to st ar t on channel 3. 0: dma0 channel 3 idle. 1: dma0 transfer in prog - ress on channel 3. 2 ch2_busy channel 2 busy. 0: no effect. 1: force dma0 transfer to st ar t on channel 2. 0: dma0 channel 2 idle. 1: dma0 transfer in prog - ress on channel 2. 1 ch1_busy channel 1 busy. 0: no effect. 1: force dma0 transfer to st ar t on channel 1. 0: dma0 channel 1 idle. 1: dma0 transfer in prog - ress on channel 1. 0 ch0_busy channel 0 busy. 0: no effect. 1: force dma0 transfer to st ar t on channel 0. 0: dma0 channel 0 idle. 1: dma0 transfer in prog - ress on channel 0.
rev. 0.3 155 si102x/3x sfr page = 0x2; sfr address = 0xd1 sfr definition 11.5. dma0sel: dma0 channel se lect for configuration bit 7 6 5 4 3 2 1 0 name dma0sel[2:0] type r r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:3 unused read = 0b, write = don?t care 2:0 dma0sel[2:0] channel select for configuration. these bits select the channel for configuration of the dma0 transfer. the f i rst step to configure a channel for dma0 transfer is to select the desired channel, and then write to channel specific registers dma0ncf, dma0nbal/h, dma0naol/h, dma0nszl/h. 000: select channel 0 001: select channel 1 010: select channel 2 011: select channel 3 100: select channel 4 101: select channel 5 110: select channel 6 111: invalid
si102x/3x 156 rev. 0.3 sfr page = 0x2; sfr address = 0xd6 sfr definition 11.6. dma0nmd: dma channel mode bit 7 6 5 4 3 2 1 0 name wrap type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:1 reserved read = 0, write = 0 0 wrap wrap enable. setting this bit will enable wrapping. the dma0nsz register sets the transfer size. normally the dma0ao value st art s at zero in increases to the dman sz minus one. at this point the trans - fer is complete and the in terrupt bit will be s et. if the wrap bit is set, the dma0nao will be reset to zero. note: this is a dma channel indirect register. select th e desired channel first writ ing the dma0sel register.
rev. 0.3 157 si102x/3x sfr page = 0x2; sfr address = 0xc9 sfr definition 11.7. dma0ncf: dma channel configuration bit 7 6 5 4 3 2 1 0 name inten minten stall endian periph[3:0] type r/w r/w r/w r/w r r/w reset 0 0 0 0 0 0 0 0 bit name function 7 inten full-length interrupt enable. 0: disable the full-length interrupt of the selected channel. 1: enable the full-length interrupt of the selected channel. 6 minten mid-point interrupt enable. 0: disable the mid-point interrupt of the selected channel. 1: enable the mid-point interrupt of the selected channel. 5 stall dma0 stall. setting this bit stalls the dma0 transfer on the selected channel. after a s t all, this bit must be cleared by software to resume normal operation. 0: the dma0 transfer of the sele cte d channel is not being stalled. 1: the dma0 transfer of the selec t ed channel is stalled. 4 endian data transfer endianness. this bit sets the byte order for multi-byte tr ansfers. this is only relevant for two or three byte transfers. the value of this bit does not matter for single byte transfers. 0: little endian 1: big endian 3:0 periph[2:0] peripheral selection of the selected channel. these bits choose one of the nine dm a0 tr ansfer functions for the selected channel. 0000: xram to enc0l/m/h 0001: enc0l/m/h to xram 0010: xram to crc1in 0011: xram to spi1dat 0100: spi1dat sfr to xram 0101: xram to aes0kin 0110: xram to aes0bin 0111: xram to aes0xin 1000: aes0youtto xram note: this is a dma channel indirect register. select th e desired channel first writ ing the dma0sel register.
si102x/3x 158 rev. 0.3 sfr page = 0x2; sfr address = 0xcb sfr page = 0x2; sfr address = 0xca sfr definition 11.8. dma0nbah: memory base address high byte bit 7 6 5 4 3 2 1 0 name nbah[3:0] type r r r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7:4 unused read = 0b, write = don?t care 3:0 nbah[3:0] memory base address high byte. sets high byte of the memory base address which is the dma0 xram start - ing address of the selected channel if the channel?s address offset dma0nao is reset to 0. note: this is a dma channel indirect register. select th e desired channel first writ ing the dma0sel register. sfr definition 11.9. dma0nbal: memory base address low byte bit 7 6 5 4 3 2 1 0 name nbah[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 nbal[7:0] memory base address low byte. sets low byte of the memory base ad dress which is the dma0 xram start - ing address of the selected channel if the channel?s address offset dma0nao is reset to 0. note: this is a dma channel indirect register. select th e desired channel first writ ing the dma0sel register.
rev. 0.3 159 si102x/3x sfr page = 0x2; sfr address = 0xcd sfr page = 0x2; sfr address = 0xcc sfr definition 11.10. dma0naoh: memory a ddress offset high byte bit 7 6 5 4 3 2 1 0 name naoh[1:0] type r r r r r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7:2 unused read = 0b, write = don?t care 1:0 naoh[1:0] memory address offset high byte. sets the high byte of the add re ss offset of the sele cted channel which acts a counter during dma0 transfer. the address offset auto-increments by one after one byte is transferred. when configuring a channel for dma0 transfer, the address offset should be reset to 0. note: this is a dma channel indirect register. select th e desired channel first writ ing the dma0sel register. sfr definition 11.11. dma0naol: memory address offset low byte bit 7 6 5 4 3 2 1 0 name nacl[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 nacl[7:0] memory address offset low byte. sets the low byte of the address offset of the selected channel which acts a co un ter during dma0 transfer. the address offset auto-increments by one after one byte is transferred. when configuring a channel for dma0 transfer, the address offset should be reset to 0. note: this is a dma channel indirect register. select th e desired channel first writ ing the dma0sel register.
si102x/3x 160 rev. 0.3 sfr page = 0x2; sfr address = 0xcf sfr page = 0x2; sfr address = 0xce sfr definition 11.12. dma0nszh: transfer size high byte bit 7 6 5 4 3 2 1 0 name nszh[1:0] type r r r r r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7:2 unused read = 0b, write = don?t care 1:0 nszh[1:0] transfer size high byte. sets high byte of dma0 transfer size o f the selected channel. transfer size sets the maximum number of bytes for the dma0 transfer. when the address offset is equal to the transfer size, a full-length interrupt is gener - ated on the channel. note: this is a dma channel indirect register. select th e desired channel first writ ing the dma0sel register. sfr definition 11.13. dma0nszl: memory transfer size low byte bit 7 6 5 4 3 2 1 0 name nszl[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 nszl[7:0] memory transfer size low byte. sets low byte of dma0 tr ansf er siz e of the selected channel. transfer size sets the maximum number of bytes for the dma0 transfer. when the address offset is equal to the transfer size, a full-length interrupt is gener - ated on the channel. note: this is a dma channel indirect register. select th e desired channel first writ ing the dma0sel register.
rev. 0.3 161 si102x/3x 12. cyclic redundancy check unit (crc0) si102x/3x devices include a cyclic redundancy check unit ( crc0) that can perform a crc using a 16-bit or 32-bit polynomial. crc0 accepts a stream of 8-bit dat a written to the crc0in register. crc0 posts the 16- bit or 32-bit result to an internal register. the internal result register may be accessed indirectly using the crc0pnt bits and crc0dat register, as shown in figure 12.1 . crc0 also has a bit reverse register for quick data manipulation. figure 12.1. crc0 block diagram 12.1. 16-bit crc algorithm the crc0 unit calculates the 16-bit crc msb-firs t, using a polynomial of 0x1021. the following describes the 16-bit crc algorithm performed by the hardware: 1. xor the most-significant byte of the curr ent crc result with the input by te. if this is the first iteration of the crc unit, the current crc result will be the set init ial value (0x000 0 or 0xffff). a. if the msb of the crc result is set, left-shift the crc result, and then xor the crc result with the polynomial (0x1021). b. if the msb of the crc result is not set, left-shift the crc result. 2. repeat at step 2a for the number of input bits (8). crc0in 8 crc0dat crc0cn crc0sel crc0init crc0val crc0pnt1 crc0pnt0 crc engine 4 to 1 mux result 32 8 8 8 8 8 crc0auto crc0cnt automatic crc controller flash memory 8 crc0flip write crc0flip read
si102x/3x 162 rev. 0.3 the 16-bit si102x/3x crc algorithm can be described by the following code: unsigned short updatecrc (unsigned short crc_acc, unsigned char crc_input) { unsigned char i; // loop counter #define poly 0x1021 // create the crc "dividend" for polynomial arithmetic (binary arithmetic // with no carries) crc_acc = crc_acc ^ (crc_input << 8); // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x8000) == 0x8000) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc << 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc << 1; } } // return the final remainder (crc value) return crc_acc; }? the following table lists several inpu t values and the associated outputs using the 16-bit crc algorithm: table 12.1. example 16-bit crc outputs input output 0x63 0xbd35 0x8c 0xb1f4 0x7d 0x4eca 0xaa, 0xbb, 0xcc 0x6cf6 0x00, 0x00, 0xaa, 0xbb, 0xcc 0xb166
rev. 0.3 163 si102x/3x 12.2. 32-bit crc algorithm the crc0 unit calculates the 32-bit crc using a poly nomial of 0x04c11db7. the crc-32 algorithm is reflected, meaning that all of the input bytes and the final 32-bit output are bit-reversed in the processing engine. the following is a description of a simplified c rc algorithm that produces results identical to the hardware: step 1. xor the least-sign ificant by te of the current crc result wi th the input byte. if this is the first iteration of the crc un it, the current crc result w ill be the set initial value (0x00000000 or 0xffffffff). step 2. right-shift the crc result. step 3. if the lsb of the crc result is set, xor the crc result with the reflected polynomial (0xedb88320). step 4. repeat at step 2 for the number of input bits (8). ? for example, the 32-bit crc algorithm can be described by the following code: unsigned long updatecrc (unsigned long crc_acc, unsigned char crc_input) { unsigned char i; // loop counter #define poly 0xedb88320 // bit-reversed version of the poly 0x04c11db7 // create the crc "dividend" for polynomial arithmetic (binary arithmetic // with no carries) crc_acc = crc_acc ^ crc_input; // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x00000001) == 0x00000001) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc >> 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc >> 1; } } // return the final remainder (crc value) return crc_acc; } the following table lists several input values and th e associated outputs using the 32-bit crc algorithm (an initial value of 0xffffffff is used):
si102x/3x 164 rev. 0.3 12.3. preparing fo r a crc calculation to prepare crc0 for a crc calculati on, software should select the desired polynomial and set the initial value of the result. two polynomials are available: 0x1021 (16-bit) and 0x04c11db7 ( 32-bit). the crc0 result may be initialized to one of two values: 0x00000000 or 0xffffffff. the following steps can be used to initialize crc0. 1. select a polynomial (set crc0sel to 0 for 32-bit or 1 for 16-bit). 2. select the initial result value (set crc0val to 0 for 0x 00000000 or 1 for 0xffffffff). 3. set the result to its initia l v a lue (write 1 to crc0init). 12.4. performing a crc calculation once crc0 is initialized, the input data stream is sequenti ally written to crc0in, one byte at a time. the crc0 result is automatically updated after each byte is written. the crc engine may also be configured to automatically perform a crc on one or more flash se ctors. the following steps can be used to automati - cally perform a crc on flash memory. 1. prepare crc0 for a crc calculation as shown above. 2. if necessary, set the ifbank bits in the psbank for the desired code bank. 3. write the index of the starting page to crc0auto. 4. set the autoen bit in crc0auto. 5. write the number of flash sectors to perform in the crc calculation to crc0cnt. ? note: each flash sector is 1024 bytes. 6. write any value to crc0cn (or or its contents with 0x00) to initiat e th e crc calculation. the cpu will not execute code any additional code until the crc operation completes. 7. clear the autoen bit in crc0auto. 8. read the crc result using the procedure below. setting the ifbank bits in the psbank sfr is only necessary when accessing the upper banks on 12 8 kb code bank devices (si1020/24/30/34). multiple crcs are required to co ver the entire 128 kb flash array. when writing to the psbank sfr, the code initiating th e auto crc of flash mu st be executing from the common area. 12.5. accessing th e crc0 result the internal crc0 result is 32-b its (crc0sel = 0b) or 16-bits (crc0sel = 1b). the crc0pnt bits select the byte that is targeted by read and write operations on crc0dat and increment after each read or write. the calculation re sult will remain in the internal cr0 result register until it is set, overwritten, or addi - tional data is written to crc0in. table 12.2. example 32-bit crc outputs input output 0x63 0xf9462090 0xaa, 0xbb, 0xcc 0x41b207b3 0x00, 0x00, 0xaa, 0xbb, 0xcc 0x78d129bc
rev. 0.3 165 si102x/3x sfr page = 0xf; sfr address = 0x92 sfr definition 12.1. crc0cn: crc0 control bit 7 6 5 4 3 2 1 0 name crc0sel crc0init crc0val crc0pnt[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:5 unused read = 000b; write = don?t care. 4 crc0sel crc0 polynomial select bit. this bit selects the crc0 polynomial and result length (32-bit or 16-bit). 0: crc0 uses the 32-bit polynomial 0x 04c 1 1db7 for calcul ating the crc result. 1: crc0 uses the 16-bit polynomial 0x10 21 for calculating the crc result. 3 crc0init crc0 result init ializ ation bi t. writing a 1 to this bit initializes th e entire crc res ult based on crc0val. 2 crc0val crc0 set value initialization bit. this bit selects the set value of the crc result. 0: crc result is set to 0x00000000 on write of 1 to crc0init. 1: crc result is set to 0xfff fffff on write of 1 to crc0init. 1:0 crc0pnt[1:0] crc0 result pointer. specifies the byte of the crc result to b e read/written on the next access to crc0dat. the value of these bits will auto -increment upon ea ch read or write. for crc0sel = 0: 00: crc0dat accesses bits 7?0 of the 32-bit crc result. 01: crc0dat accesses bits 15?8 of the 32-bit crc result. 10: crc0dat accesses bits 23?16 of the 32-bit crc result. 11: crc0dat accesses bits 31?24 of the 32-bit crc result. for crc0sel = 1: 00: crc0dat accesses bits 7?0 of the 16-bit crc result. 01: crc0dat accesses bits 15?8 of the 16-bit crc result. 10: crc0dat accesses bits 7?0 of the 16-bit crc result. 11: crc0dat accesses bits 15?8 of the 16-bit crc result.
si102x/3x 166 rev. 0.3 sfr page = 0xf; sfr address = 0x93 sfr page = 0xf; sfr address = 0x91 sfr definition 12.2. crc0in: crc0 data input bit 7 6 5 4 3 2 1 0 name crc0in[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 crc0in[7:0] crc0 data input. each write to crc0in result s in the written data being computed into the existing crc result according to the crc algorithm described in section 12.1 sfr definition 12.3. crc0dat: crc0 data output bit 7 6 5 4 3 2 1 0 name crc0dat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 crc0dat[7:0] crc0 data output. each read or write performed on crc0dat targets the crc result bits pointed to by the crc 0 result pointer (crc0pnt bits in crc0cn).
rev. 0.3 167 si102x/3x sfr page = 0xf; sfr address = 0x96 sfr page = 0xf; sfr address = 0x97 sfr definition 12.4. crc0auto: crc0 automatic control bit 7 6 5 4 3 2 1 0 name autoen crcdone crc0st[5:0] type r/w r/w reset 0 1 0 0 0 0 0 0 bit name function 7 autoen automatic crc calc ulation enable. when autoen is set to 1, any write to c rc0cn will initiate an automatic crc starting at flash sector crc0st an d continuing for crc0cnt sectors. 6 crcdone crcdone automatic crc calculation complete. set to 0 when a crc calculation is in progress. note that code execution is stopped duri ng a crc calc ulation, therefore read s from firmware will always return 1. 5:0 crc0st[5:0] automatic crc calculation s t arting flash sector. these bits specify the flash sector to star t the automatic crc calculation. the starting address of the first flash sector included in the automatic crc calculation is crc0st x 1024. for 128 kb devices, pages 32?63 access the upper code bank as selected by the if bank bits in the psbank sfr. sfr definition 12.5. crc0cnt: crc0 automati c flash sector count bit 7 6 5 4 3 2 1 0 name crc0cnt[5:0] type r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:6 unused read = 00b; write = don?t care. 5:0 crc0cnt[5:0] automatic crc calculation flash sector count. these bits specify the number of flash sectors to include in an automatic crc cal - culation. the starting address of the last fla s h sector included in the automatic crc calculation is (crc0st+crc0cnt) x 1024. the last page should not exceed page 63. setting both crc0st and crc0cnt to 0 will perform a crc over the 64kb banked memory space.
si102x/3x 168 rev. 0.3 12.6. crc0 bit reverse feature crc0 includes hardware to reverse the bit order of each bit in a byte as shown in figure 12.2 . each byte of data written to crc0flip is read back bit reversed. f o r example, if 0xc0 is written to crc0flip, the data read back is 0x03. bit reversal is a useful mathem atical function used in algorithms such as the fft. figure 12.2. bit reverse register sfr page = 0xf; sfr address = 0x94 sfr definition 12.6. crc0flip: crc0 bit flip bit 7 6 5 4 3 2 1 0 name crc0flip[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 crc0flip[7:0] crc0 bit flip. any byte written to crc0flip is read back in a bit-rev e rsed order, i.e. the written lsb becomes the msb. for example: if 0xc0 is written to crc0flip, the data read back will be 0x03. if 0x05 is written to crc0flip, the dat a read back will be 0xa0. crc0flip write crc0flip read
rev. 0.3 169 si102x/3x 13. dma-enabled cyclic re dundancy check module (crc1) si102x/3x devices include a dma-enabled cyclic redu ndancy check module (crc1) that can perform a crc of data using an arbitrary 16-bit polynomial. this peripheral can compute crc results using direct dma access to data in xram. using a dma transfer provides much higher data thr oug hput than using sfr access. since the cpu can be in idle mode while the crc is calculated, crc1 also provides substantial power savings. the crc1 module is not restricted to a limit ed list of fixed polynomials. instead, the user can specify any valid 16-bit polynomial. crc1 accepts a stream of 8-bit data written to the cr c1in r egister. a dma transfer can be used to auton - omously transfer data from xram to the crc1in sf r . t he crc1 module may also be used with sfr access by writing directly to the crc1in sfr. after eac h byte is written, the crc resultant is updated on the crc1outh:l sfrs. after writing all data bytes, the final crc results are available from the crc1outh:l registers. the final results may be flipped or inverted using the flip and inv bits in the crc1cn sfr. the initial seed value can be reset to 0x0000 or seeded with 0xffff. 13.1. polynomial specification the arbitrary polynomial should be written to the crc 1polh:l sfrs before writ ing data to the crcin sfr. a valid 16-bit crc polynom ial must hav e an x 16 term and an x 0 term. theoretically, a 16-bit polynomial might have 17 terms total. however, the polynomial sf r is only 16-bits wide. the convention used is to omit the x 16 term. the polynomial should be wr itten in big endian bit order. the most significant bit corre - sponds to the highest order term. thus, the most si gnificant bit in the cr c1 poll sfr represents the x 15 term, and the least significant bit in the crc1polh sfr represents the x 0 term. the least significant bit of crc1poll should always be set to one. the crc results are undefined if this bit is cleared to a zero. figure 13.1 depicts the polynomial representation for the crc-16-ccit polynomial x 16 + x 12 + x 5 + 1, or 0x1021. figure 13.1. polynomial representation 7 6 5 4 3 2 1 0 crc1polh 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 x 16 + x 12 + x 5 +1 1 crc1polh:l = 0x1021 crc1poll
si102x/3x 170 rev. 0.3 13.2. endianness the crc1 module is optimized to process big endian data. data written to the crc1in sfr should be in the normal bit order with the most significant bit stored in bit 7 and the least significant bit stored in bit 0. the input dat a is shifted left into the crc engine . the crc1 module will process one byte at a time and update the results for each byte. when used with the dma, the first byte to be written should be stored in the lowest address. some communications systems may tra nsmit data least significant bi t first and may require calculation of a crc in the transmission bit order. in this case, the bits must be flippe d, using the crc0fl ip sfr, before writing to the crc1in sfr. the fina l 16-bit result may be flipped usin g the flip bit in the crc1cn sfr. note that the polynomial is always written in big endian bit order.
rev. 0.3 171 si102x/3x 13.3. crc seed value normally, the initial value or the c rc results is cleared to 0x0000. howe ver, a crc might be specified with an initial value preset to all ones (0xffff). the steps to preset the crc wit h all ones is as follows: 1. set the see d bit to 1. 2. reset the crc1 module by se tting the clr bit to 1 in crc1cn. 3. clear the seed bit to 0. the crc1 module is not r eady to calculate a crc using a crc seed value of 0xffff. 13.4. inverting the final value sometimes it is necessary to invert the final value. this will take the on es complement of the final result. the steps to flip the final crc result s are as follows: 1. clear the crc module by se tting the clr bit in crc1cn sfr. 2. write the polynomial to crc1polh:l. 3. write all data bytes to crc1in. 4. set the inv bit in the crc1cn sfr to invert th e final results. 5. read the final crc results from crc1outh:l. clear the flip bit in the crc1cn sfr. 13.5. flipping the final value the steps to flip the final crc results are as follows: 1. clear the crc module by se tting the clr bit in crc1cn sfr. 2. write the polynomial to crc1polh:l. 3. write all data bytes to crc1in. 4. set the flip bit in the crc1 cn sfr to flip the final results. 5. read the final crc results from crc1outh:l. 6. clear the flip bit in the crc1cn sfr. the flip operation will exchange bit 15 with bit 0, bit 14 with bit 1, bit 13 wi th bit 2, and so on.
si102x/3x 172 rev. 0.3 13.6. using crc1 with sfr access the steps to perform a crc using sfr access with the crc1 module is as follow: 1. if desired, set the seed bit in the crc1cn sfr to seed with 0xffff. 2. clear the crc module by sett ing the clr bit in the crc1cn sfr. 3. clear the seed bit, if set previously in step 1. 4. write the polynomial to crc1polh:l. 5. write all data bytes to crc1in. 6. if desired, invert and/or flip the final results using the inv and flip bits. 7. read the final crc results from crc1outh:l. 8. clear the inv and/or flip bits, if set previously in step 6. note that all of the crc1 sf rs ar e on sfr page 0x2. 13.7. using the crc1 module with the dma the steps to computing a crc using the dma are as follows. 1. if desired, set the seed bit in crc1cn to seed with 0xffff. 2. clear the crc module by se tting the clr bit in crc1cn sfr. 3. clear the seed bit, if set previously in step 1. 4. write the polynomial to crc1polh:l. 5. configure the dma for the crc operation: a. disable the desired dma channel by clearing the corresponding bit in dma0en. b. select the desired dma ch annel by writing to dma0sel. c. configure the selected dma channel to use t he crc1in peripheral request by writing 0x2 to dma0ncf. d. enable the dma interrupt on the selected channel by setting bit 7 of dma0ncf. e. write 0 to dma0nm d to disable wrapping. f. write the address of the first byte of crc data to dma0nbah:l. g. write the size of the crc data in bytes to dma0nszh:l. h. clear the address offset sfrs dma0a0h:l. i. enable the interrupt on the desired channel by setting the corresponding bit in dma0int. j. enable the desired channel by setting the corresponding bit in dma0en. k. enable dma interrupts by setting bit 5 of eie2. 6. set the dma mode bit (bit 3) in the crc1cn sfr to initiate the crc operation. 7. wait on the dma interrupt. 8. if desired, invert and/or flip the final results using the inv and flip bits. 9. read the final results from crc1outh:l. 10. clear the inv and/or flip bits , if set previously in step 8.
rev. 0.3 173 si102x/3x sfr page = 0x2; sfr address = 0xbe; not bit-addressable sfr definition 13.1. crc1cn: crc1 control bit 7 6 5 4 3 2 1 0 name clr dma flip inv seed type r/w r r r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 rst reset. setting this bit to 1 will reset the crc module and set the c rc results sfr to the seed value as specified by the seed bit. t he crc module should be reset before starting a new crc. this bit is self-clearing. 6:4 reserved 3 dma dma mode. setting this bit will configure the crc 1 module for dma mode. once a dma channel has been configured to use accept peripheral requests from crc 1, setting this bit will initiate a dma crc operation. this bit should be cleared after each crc dma transfer. 2 flip flip. setting this bit will flip the contents of the 16- bit crc result sfrs. (crc0outh:crc0outl) this operation is normally performed only on the final crc results. this bit should be cleared before starting a new crc computation. 1 inv invert. setting this bit will invert the conten t s of the 16-bit crc result sfr. (crc0outh:crc0outl) this operation is normally performed only on the final crc results. this bit should be cleared before starting a new crc computation. 0 seed seed polarity. if this bit is zero, a seed value or 0x0000 will be used. if this bit is 1, a seed value of 0xffff will be used. this bit should be set before setting the rst bit.
si102x/3x 174 rev. 0.3 sfr page = 0x2; sfr address = 0xb9; not bit-addressable sfr page = 0x2; sfr address = 0xbc; not bit-addressable sfr page = 0x2; sfr address = 0x bd; not bit-addressable sfr definition 13.2. crc1in: crc1 data in bit 7 6 5 4 3 2 1 0 name crc1in[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 crc1in[7:0] crc1data in. crc data should be sequentially written, one byte at a time, to the crc1in da ta input sfr. when the crc1 module is used with the dma, the dm a will write directly to this sfr. sfr definition 13.3. crc1poll: crc1 polynomial lsb bit 7 6 5 4 3 2 1 0 name crc1poll[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 crc1poll[7:0] crc1 polynomial lsb. sfr definition 13.4. crc1polh: crc1 polynomial msb bit 7 6 5 4 3 2 1 0 name crc1polh[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 crc1polh[7:0] crc1 polynomial msb.
rev. 0.3 175 si102x/3x sfr page = 0x2; sfr address = 0xba; not bit-addressable sfr page = 0x2; sfr address = 0xbb; not bit-addressable sfr definition 13.5. crc1outl: crc1 output lsb bit 7 6 5 4 3 2 1 0 name crc1outl[7:0] type r r r r r r r r reset 0 0 0 0 0 0 0 0 bit name function 7:0 crc1outl[7:0] crc1 output lsb sfr definition 13.6. crc1outh: crc1 output msb bit 7 6 5 4 3 2 1 0 name crc1outh[7:0] type r r r r r r r r reset 0 0 0 0 0 0 0 0 bit name function 7:0 crc1outh[7:0] crc1 output msb.
si102x/3x 176 rev. 0.3 14. advanced encryption standard (aes) peripheral the si102x/3x devices include a hardware implementat ion of the advanced encryption standard block cipher as specified in nist pub lication fips 197 ?advanced encrypti on standard (aes), november 2001. the rijndael encryption algorithm was chosen by ni st for the aes block cipher. the aes block cipher can be used to encrypt data for wireless communications. data can be encrypted before transmission and decrypted upon reception. this prov ides security for private networks. the aes block cipher is a symmetric ke y encryption algorithm. symmetric key encryption relies on secret keys th at are known by both the sender and receiver. the decryption key may be obtained using a simple transformation of the encryp tion key. aes is not a public key encrypti on algorithm. the aes block cipher uses a fixed 16 byte block size . so data less than 16 bytes must be padded with zeros to fill the entire block. wire less data must be padded and transmitted in 16 -byte blocks. the entire 16-byte block must be transmitted to successfully decrypt the information. the aes engine supports key lengt hs of 128-bit s, 192-bits, or 256-bits. a key size of 128-bits is sufficient to protect the confidentiality of classified secret information. the advanced encryption standard was designed to be secure for at least 20 to 30 years. the 128-bit key provides fastest encryption. the 192-bit and 256-bit key lengths may be used to protect highly sensitive classified top secret information. since symmetric key encryption relies on secret keys, the secu rity o f the data can only be protected if the key remains secret. if the encryption key is stored in flash memory, then the entire flash should be locked to ensure the encryption key cannot be discovered. (see flash security.) the basic aes block cipher is implem ented in hardware. this hardware accelerator provides performance that may be 1000 times faster than a software implementation. the higher performance translates to a power savings for low-power wirele ss applications. the aes block cipher, or block cip her modes based on the aes block cipher, is used in many wireless standards. these include several i eee standards in the wireless pan (8 02.15) and wirele ss lan (802.11) working groups.
rev. 0.3 177 si102x/3x 14.1. hardware description figure 14.1. aes peripheral block diagram the aes encryption module consists of the following elements: ? aes encryption/decryption core ? configuration sfrs ? key input sfr ? data sfrs ? input multiplexer ? output multiplexer ? input exclusive or block ? output exclusive or block ? internal state machine aes core key in key out data in data out aes0bin aes0xin aes0kin aes0yout aes0dcf aes0bcfg + + internal state machine
si102x/3x 178 rev. 0.3 14.1.1. aes encryption/decryption core the aes encryption/decryption core is a digital implementation of th e advanced encryption standard block cipher. the core may be used for either encrypti on or decryption. encryption may be selected by set - ting bit 5 in the aes0bcfg sfr. when configured for encryption, plaintext is w r itten to the aes core data input and the encrypted ciphertext is read from th e data output. conversely, when configured for decryp - tion, encrypted ciphertext is written to the data input and decrypted plaintext is read form the data output. when configured for encryption, the encryption key must be written to the key input. when configured for decryption, the decryp tion key must be written to the key input. the aes core may also be used to gen erate a decryption key from a know n encryption key . to generate a decryption key, the core must be co nfigured for encryption, the encryption key is written to the key input, and the decryption key may be read from the key output. aes is a symmetric key encryption algo rithm. this means that the decr yption key may be generated from a n encryption key using a simple algorithm. both keys must remain secret. if securi ty of the encryption key is compromised, one can easily generate the decryption key. since it is easy to generate the decryption key, on ly the e n cryption key may be stored in flash memory. 14.1.2. data sfrs the data sfrs are used for the data flow into and o u t of the aes module. when used with the dma, the dma itself will write to and read from the data sfrs. when used in manual mode, the data must be written to the data sfrs one byte at a time in the proper sequence. the aes0kin sfr provid es a dat a path for the aes core key i nput. for an encryption oper ation, the encryption key is written to the aes0kin sfr, either by the dma or direct sfr access. for a decryption operation, the decryption key mu st be written to the aes0kin sfr. the aes0bin is the direct data input sfr for the aes block. for a simple encryption operation, the plain - text is written to the aes0bin sfr ? either by the dma or direct sfr access . fo r decryption, the cipher - text to be decrypted is written to the aes0bin sfr. the aes0bin sfr is also used togeth er with the aes0xin when an exclusive or operation is required on the input data path. the aes0xin sfr provides an input data path to the exclusive or operator. the aes0xin is not used for simple aes block cipher encr yption or decryption. it is only use for bloc k cipher modes that require an exclusive or operator on the input or output data. the aes core requires that the input dat a bytes are written in a specif ic order. when used with the dma, this is managed by the internal state machine. when using direct sfr access, each of input data must be written one byte at a time to each sfr in this particular order. 1. write aes0bin 2. w r ite aes0xin (optional) 3. write aes0kin this sequence is repeated 16 times. when using a 19 2- bit or 256-bit key length, the remaining additional key bytes are written after writing all sixteen of th e aes0bin and aes0xin bytes. after encryption or decryption is completed, the resulti ng dat a may be read from the aes0yout. option - ally, exclusive or data may be written to th e aes0xin sfr before reading the aes0yout sfr. 1. write aes0xin (optional) 2 . read aes0yout
rev. 0.3 179 si102x/3x 14.1.3. confi guration sfrs the aes module has two configuration sfrs. the aes0bcfg sfr is used to configure the aes core. bits 0 and 1 are used to select th e key size. the aes core supports 128- bit, 192-bit and 256-bit encryption. bit 2 selects encrypt or de crypt. the aes enable bit (bit 3) is used to enable t he aes module and start new encryption operation. the aes done bit (bit 5) is the aes interr upt flag that signals a block of data has been completely encrypted or decrypted and is ready to be read from the aes0yout sfr. note that the aes done interrupt is not normally used when the aes module is used with the dma. instead, the dma interrupt is used to signal that the encrypted or decrypted data has been transferred completely to memory. the dma done interrupt is normally only used with direct sfr access. the aes0dcfg sfr is used to sele ct the dat a path for th e aes module. bits 0 th rough 2 are used to select the input and output multiplexer configuration. the aes data path should be configured prior to initi - ating a new encryption or decryption operation. 14.1.4. input multiplexer the input multiplexer is used to sele ct either the contents of the aes0bin sfr or the contents of the aes0bin sfr exclusive ored with the contents of the aes0xin sfr. the exclusive or input data path provides support for cbc encryption. 14.1.5. output multiplexer the output multiplexer selects the da t a source for the aes0yout sfr. the three possible sources are the aes core data output, th e aes core key output, and the aes core data output ex clusive ored with the aes0xin sfr. the aes core data output is used for simple encr yption and decryption. the exclusive or output data path provides suppo rt fo r cbc mo de decryption and ctr mode encryp - tion/decryption. the aes0xin is the source for bo th in pu t and output exclusive or data. when the aes0xin is used with the i nput exclusive or data path, the aexin data is written in sequence with the aes0bin data. when used with the output xro data path, the aes0xin data is written after the encryp - tion or decryption operation is complete. the key output is used to generate an inverse key. t o generate a decryption key from an encryption key, the aes core should be configured for an encryption operation. to generate an encrypti on key from a decryption key, the aes core should be configured fo r a decryption operation. 14.1.6. internal s t ate machine the aes module has an in ternal state machine that manages the dat a flow. th e internal state machine accommodates the two different us age scenarios. when us ing the dma, the inte rnal state machine will send peripheral requests to the dma requesting the dma to transfer data from xram to the aes module input sfrs. upon the completion of one block of data, the aes module will send peripheral requests requesting data to be transferred from the aes0yout sfr to xram. these peripher al requests are man - aged by the internal state machine. when not using the dma, data must be w ritten and read in a specif ic order. the dma state machine will advance with each byte written or read. the internal state machine may be reset by clearing the enable bit in the aesbgfg sfr. clearing the enable bit before encry ption or decrypt ion operation will ensure that the st ate machine starts at the proper state. when encrypting or decrypting multiple blocks it is n o t necessary to disable the aes module between blocks, as long as the proper sequence of events is obeyed.
si102x/3x 180 rev. 0.3 14.2. key inversion the key output is used to generate an inverse key. to generate a decryption key from an encryption key, the aes core should be configured for an encryption operation. dummy data and the encryption key are written to the aes0bin and aes0kin sfrs respectively. the output mu ltiplexer should be configured to output the decryption key to the aes0yout sfr. figure 14.2. key inversion data flow the dummy data may be zeros or arbitrary data. the content of the dummy data does not matter. but six - teen bytes of data must be written to t he aes0bin sfr to generate the inverse key . aes core key in key out data in data out aes0bin aes0xin aes0kin aes0yout aes0dcfg aes0bcfg + + internal state machine
rev. 0.3 181 si102x/3x 14.2.1. key inversion using dma normally, the aes block is used with the dma. this provides the best performance and lo west power con - sumption. code examples are provided in 8051 comp ile r in dependent c code using the dma. it is highly recommended to use the code examples. the steps are listed here for completeness. steps to generate the decryption key from encryption key ? prepare encryption key and dummy data in xram. ? reset aes module by clea ring bit 3 of aes0bcfg. ? disable the first three dma channels by clearing bits 0 to 2 in dma0en. ? configure the first dm a channel for aes0kin. ?? select the first dma channel by writing 0x00 to dma0sel. ?? configure the first dma channel to move xr am to aes0kin by writing 0x05 to dma0ncf. ?? clear dma0nmd to disable wrapping. ?? write the xram address of the encryption key to dma0nbah and dma0nbal. ?? write the key length in bytes to dma0nszl. ?? clear dma0nszh ?? clear dma0naoh and dma0naol. ? configure the second dma channel for aes0bin. ?? select the second dma channel by writing 0x01 to dma0sel. ?? configure the second dma channel to move xram to aes0bin sfr by writing 0x06 to the dma0ncf sfr. ?? clear dma0nmd to disable wrapping. ?? write the xram address of dummy data to dma0nbah and dma0nbal. ?? write 0x10 (16) to dma0nszl. ?? clear dma0nszh ?? clear dma0naoh and dma0naol ? configure the third dma channel for aes0yout. ?? select the third dma channel by writing 0x02 to dma0sel. ?? configure the third dma channel to move the contents of aes0yout to xram by writing 0x08 to dma0ncf. ?? enable transfer complete interrupt by setting bit 7 of dma0ncf. ?? clear dma0nmd to disable wrapping. ?? write the xram address for the decrypt ion key to dma0nbah and dma0nbal. ?? write the key length in bytes to dma0nszl. ?? clear dma0nszh. ?? clear dma0naoh and dma0naol. ? clear first three dma inte rrupts by clearing bits 0 to 2 in dma0int. ? enable first three dma channels setting bits 0 to 2 in dma0en ? configure the aes module data flow for inverse key generat ion by writing 0x04 to aes0dcfg. ? write key size to bits 1 and 0 of aes0bcfg. ? configure the aes core fo r encryption by setting bit 2 of aes0bcfg. ? initiate the encr yption operation by setting bit 3 of aes0bcfg. ? wait on the dma interrupt from dma channel 2. ? disable the aes module by cl earing bit 2 of aes0bcfg. ? disable the dma by writing 0x00 to dma0en.
si102x/3x 182 rev. 0.3 the key and data to be encrypted should be stored as an array with the first byte to be encrypted at the lowest address. th e value of the big endian bit of the dmacf0 sfr does not matter. the aes block uses only one byte transfers, so there is no particular endianness associated with a one byte transfer. the dummy data can be zeros or any value. the encrypt ed data is discarded, so the value of the dummy data does not mater. it is not strictly required to use dma ch annels 0, 1, and 2. any three dma channels may be used. the internal state machine of the aes module will send the peripheral requests in the required order. if the other dma channels are going to be used concur rently with encryption, then only the bits corre - sponding to the encryption channels should be manipulated in dm0aen and dma0nt sfr s. 14.2.2. key inversion using sfrs normally, the aes block is used with the dma. this provides the best performance and lo west power con - sumption. however, it is also possible to use the dma with d i rect sfr access. the steps are documented here for completeness. steps to generate the decryption key from the encryption key using sfr access follow: ? first configure the aes block for key inversion: ?? reset aes module by writing 0x00 to aes0bcfg. ?? configure the aes module data flow for inverse key generation by writ ing 0x04 to aes0dcfg. ?? write key size to bits 1 and 0 of aes0bcfg. ?? configure the aes core for encrypti on by setting bit 2 of aes0bcfg. ?? enable the aes core by se tting bit 3 of aes0bcfg. ? write the dummy data alternating with key data: ?? write the first dummy byte to aes0bin ?? write the first key byte to aes0kin ?? repeat until all dummy data bytes are written ? if using 192-bit and 256-bit key, wr ite remaining key bytes to aes0kin: ? wait on aes done interrupt or poll bit 5 of aes0bcfg ? read first byte of the decryption key from aes0yout
rev. 0.3 183 si102x/3x 14.2.3. extended key output byte order when using a key length of 128-bits, the key output is in the same order as the bytes were written. when using an extended key of 192-bits or 256-bits. the extended portion of the key comes out first, before the first 16-bytes of the extended key.this is illustrated in table 14.1 . table 14.1. extended key output byte order size input output bits bytes order order 128 16 k0...15 k0...15 192 24 k0...23 k16...23 k0...15 256 32 k0...31 k16...23 k24...31 k0...15
si102x/3x 184 rev. 0.3 14.2.4. using the dma to unwrap the extended key when used with the dma, the address offset sfr dmanaoh/l may be manipulated to store the extended key in the desired order. this re quires two dma transfer s for the aes0yout chann el. when using a 192- bit key, the dma0nsz can be set to 24 bytes and the dma0na0 set to 16 . this will place the last 8 bytes of the 192-bit key in the desired location as shown in table 14.2 . the yout arrow indicates the address off - set position after each 8 bytes are trans f erred. enabling the wrap bit in dma0nmd will reset the dma0nao value after byte 23. then the dma0nz can be reset to 16 for the remaining sixteen bytes. when using a 256-bit key, dma0nsz ca n be s et to 32 and dma0naol set to 16 this will place the last 16 bytes of the 256-bit key in the desired location as shown in ta b l e 14.3 . enabling the wrap bit in dma0nmd will reset the dma0nao value af ter byte 31. then dma0nz can be set to 16 for the remaining sixteen bytes. table 14.2. 192-bit key dma usage ? yout ? yout k16...23 ? yout k0...7 k16...23 ? yout k0...7 k8...15 k16...23 table 14.3. 256-bit key dma usage ? yout ? yout k16...23 ? yout k16...23 k24...31 ? yout k0...7 k16...23 k24...31 ? yout k0...7 k8...15 k16...23 k24...31
rev. 0.3 185 si102x/3x 14.3. aes block cipher the basic aes block cipher is the basic encryption/decry ption algorithm as defined by the nist standard. a clock cipher mode is a method of encrypting and decr ypting one block of data. the input data and output data are not manipulated, chained, or exclusive ored with other data. this simple block cipher mode is sometimes called the electronic code book (ecb) mode. this mode is illustrated in figure 14.3 each operation represents one block (sixteen bytes) of d ata. the plaintext is the plain unencrypted data. the ciphertext is the encrypted data. the encryption key and decryption keys are symmetric. the decryp - tion key is the inverse key of the decryption key. note tha t the encryption operation is not the same as the decryption operation. the two operations are different and the aes core operates differently depending on whether encryption or de cryption is selected. note that each encryption or decryption operation is inde pen dent of other operati ons. also note that the same key is used over and over again for each operation.
si102x/3x 186 rev. 0.3 14.4. aes block cipher data flow the aes0 module data flow for aes block cip her encryption and decryption shown in figure 14.3 . the data flow is the same for encrypt ion and decryption. the aes0dcf sfr is always configured to route the aes core output to aes0yout. the xor on the input and output paths are not used. for an encryption operation, the core is configured fo r an encryption cipher, the encryption key is written to aes0kin, the plaintext is written to the aes0bin sfr . and the ciphertext is read from aes0yout. for a decryption operation, the core is configured fo r an decryption cipher, the decryption key is written to aes0kin, the ciphertext is written to the aes0bin sfr . and the plaintext is read from aes0yout. the key size is set to the desired key size. figure 14.3. aes block cipher data flow aes core key in key out data in data out aes0bin aes0xin aes0kin aes0yout aes0dcfg aes0bcfg + + internal state machine
rev. 0.3 187 si102x/3x 14.4.1. aes block cipher encryption using dma normally, the aes block is used with the dma. this provides the best performance and lo west power con - sumption. code examples are provided in 8051 comp ile r in dependent c code using the dma. it is highly recommended to use the code examples. the steps are listed here for completeness. steps to encrypt data using simple aes block encryption (ecb mode) ? prepare encryption key and data to be encrypted in xram. ? reset aes module by clea ring bit 2 of aes0bcfg. ? disable the first three dma channels by clearing bits 0 to 2 in dma0en. ? configure the first dm a channel for aes0kin ?? select the first dma channel by writing 0x00 to dma0sel ?? configure the second dma channel to move xram to aes0kin by writing 0x05 to dma0ncf ?? write 0x01 to dma0nmd to enable wrapping ?? write the xram location of the encryption key to dma0nbah and dma0nbal. ?? write the key length in bytes to dma0nszl ?? clear dma0nszh ?? clear dma0naoh and dma0naol. ? configure the second dma channel for aes0bin sfr. ?? select the second dma channel by writing 0x01 to dma0sel. ?? configure the second dma channel to move xram to aes0bin by writing 0x06 to dma0ncf. ?? clear dma0nmd to disable wrapping. ?? write the xram address of the data to be encrypted to dma0nbah and dma0nbal. ?? write the number of bytes to be encrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0naoh and dma0naol. ? configure the third dma channel for aes0yout ?? select the third dma channel by writing 0x02 to dma0sel ?? configure the third dma channel to move the contents of aes0you to xram by writing 0x08 to dma0ncf. ?? enable transfer complete interrupt by setting bit 7 of dma0ncf. ?? clear dma0nmd to disable wrapping. ?? write the xram address for the encrypt ed data to dma0nbah and dma0nbal. ?? write the number of bytes to be encrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0naoh and dma0naol. ? clear first three dma inte rrupts by clearing bits 0 to 2 in dma0int. ? enable first three dma channels by setting bits 0 to 2 in dma0en. ? configure the aes module data flow for aes block cipher by writing 0x00 to aes0dcfg. ? write key size to bits 1 and 0 of aes0bcfg ? configure the aes core fo r encryption by setting bit 2 of aes0bcfg ? initiate the encryption operation be setting bit 3 of aes0bcfg ? wait on the dma interrupt from dma channel 2 ? disable the aes module by cl earing bit 2 of aes0bcfg ? disable the dma by writing 0x00 to dma0en
si102x/3x 188 rev. 0.3 14.4.2. aes block cipher encryption using sfrs ? first configure aes module for aes block cipher ?? reset aes module by writing 0x00 to aes0bcfg. ?? configure the aes module data flow for aes bl ock cipher by writin g 0x00 to aes0dcfg. ?? write key size to bits 1 and 0 of aes0bcfg. ?? configure the aes core for encrypti on by setting bit 2 of aes0bcfg. ?? enable the aes core by se tting bit 3 of aes0bcfg. ? repeat alternating write sequence 16 times ?? write plaintext byte to aes0bin. ?? write encryption key byte to aes0kin. ? write remaining encryption key bytes to aes0kin for 192-bit and 256-bit encryption only. ? wait on aes done interrupt or poll bit 5 of aes0bcfg. ? read 16 encrypted bytes from aes0yout. if encrypting multiple blo cks, this process may be re peated. it is not necessa ry reconfigure the aes mod - ule for each block.
rev. 0.3 189 si102x/3x 14.5. aes block cipher decryption 14.5.1. aes block cipher decryption using dma normally, the aes block is used with the dma. this provides the best performance and lo west power con - sumption. code examples are provided in 8051 comp ile r in dependent c code using the dma. it is highly recommended to use the code examples. the steps are listed here for completeness. ? prepare decryption key and data to be decryption in xram. ? reset aes module by clea ring bit 2 of aes0bcfg. ? disable the first three dma channels by clearing bits 0 to 2 in dma0en. ? configure the first dm a channel for aes0kin ?? select the first dma channel by writing 0x00 to dma0sel ?? configure the first dma channel to move xr am to aes0kin by writing 0x05 to dma0ncf ?? write 0x01 to dma0nmd to enable wrapping ?? write the xram location of the decryption key to dma0nbah and dma0nbal. ?? write the key length in bytes to dma0nszl ?? clear dma0nszh ?? clear dma0naoh and dma0naol. ? configure the second dma channel for aes0bin. ?? select the second dma channel by writing 0x01 to dma0sel. ?? configure the second dma channel to move xram to aes0bin by writing 0x06 to dma0ncf. ?? clear dma0nmd to disable wrapping. ?? write the xram address of the data to be decrypted to dma0nbah and dma0nbal. ?? write the number of bytes to be decrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0naoh and dma0naol. ? configure the third dma channel for aes0yout ?? select the third dma channel by writing 0x02 to dma0sel ?? configure the third dma channel to move the conten ts of aes0yout to xram by writing 0x08 to dma0ncf ?? enable transfer complete interrupt by setting bit 7 of dma0ncf ?? clear dma0nmd to disable wrapping ?? write the xram address for decrypted data to dma0nbah and dma0nbal. ?? write the number of bytes to be decrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0nszh ?? clear dma0naoh and dma0naol. ? clear first three dma inte rrupts by clearing bits 0 to 2 in dma0int. ? enable first three dma channels setting bits 0 to 2 in dma0en ? configure the aes module data flow for aes block cipher by writing 0x00 to aes0dcfg. ? write key size to bits 1 and 0 of aes0bcfg ? configure the aes core fo r decryption by clearing bit 2 of aes0bcfg ? initiate the encryption operation be setting bit 3 of aes0bcfg ? wait on the dma interrupt from dma channel 2 ? disable the aes module by cl earing bit 2 of aes0bcfg ? disable the dma by writing 0x00 to dma0en
si102x/3x 190 rev. 0.3 14.5.2. aes block cipher decryption using sfrs ? first, configure aes modu le for aes block cipher ?? reset aes module by writing 0x00 to aes0bcfg. ?? configure the aes module data flow for aes bl ock cipher by writin g 0x00 to aes0dcfg. ?? write key size to bits 1 and 0 of aes0bcfg. ?? configure the aes core for decrypti on by setting bit 2 of aes0bcfg. ?? enable the aes core by se tting bit 3 of aes0bcfg. ? repeat alternating write sequence 16 times ?? write ciphertext byte to aes0bin. ?? write decryption key byte to aes0kin. ? write remaining decryption key bytes to aes0kin for 192-bit and 256-bit decryption only. ? wait on aes done interrupt or poll bit 5 of aes0bcfg. ? read 16 plaintext bytes from aes0yout. if decrypting multiple blo cks, this process may be re peated. it is not necessa ry reconfigure the aes mod - ule for each block.
rev. 0.3 191 si102x/3x 14.6. block cipher modes 14.6.1. cipher block chaining mode the cipher block chaining (cbc) algo rithm significantly improves the st rength of basic aes encryption by making each block encryption be a func tion of the previous block in addi tion to the current plaintext and key. this algorithm is shown in figure 14.4 figure 14.4. cipher block chaining mode encryption cipher plain text cipher text xor encryption cipher encryption key plain text cipher text initialization vector (iv) xor encryption decryption decryption cipher plain text xor decryption cipher plain text xor encryption key decryption key decryption key cipher text cipher text initialization vector (iv)
si102x/3x 192 rev. 0.3 14.6.1.1. cbc encryption data flow the aes0 module data flow fo r cbc encryption is shown in figure 14.5 . the plaintext is written to aes0bin. for the first block, the init ialization vector is wr itten to aes0xin. for subsequent blocks, the previous block ciphertext is written to aes0xin. aes0dcfg is configured to xor aes0xin with aes0bin for the aes core data input. the xor on the output is not us ed. the aes core is configured for an encryption operation. the encryption key is writt en to aes0kin. the ke y size is set to the desired key size. figure 14.5. cbc encryption data flow aes core key in key out data in data out aes0bin aes0xin aes0kin aes0yout aes0dcfg aes0bcfg + + internal state machine
rev. 0.3 193 si102x/3x 14.6.2. cbc encryption initia lization vector location the first block to be encrypted uses the initialization vector for the aes0xin data. subsequent blocks will use the encrypted ciphertext from the previous block. the dma is capable of encrypting multiple bocks. if the initialization is located at an arbitrary loca tion in xram, the dma base add ress location will need to be changed to the start of the encrypted ciphertext after en crypting the first block. ho wever, if the initialization vector is located in xram immediat ely before the encrypt ed ciphertext, the pointe r will be advanced to the start of the encrypted ciphertext, and mult iple blocks can be encrypted autonomously. 14.6.3. cbc encryption using dma normally, the aes block is used with the dma. this provides the best performance and lo west power con - sumption. code examples are provided in 8051 comp ile r in dependent c code using the dma. it is highly recommended to use the code examples. the steps are listed here for completeness. ? prepare encryption key, initialization vector, and data to be encrypted in xram. (the initialization vector s hou ld b e located immediately before the data to be encrypted to encrypt multiple blocks.) ? reset aes module by clea ring bit 2 of aes0bcfg. ? disable the first four dma channels by clearing bits 0 to 3 in dma0en. ? configure the first dm a channel for aes0kin ?? select the first dma channel by writing 0x00 to dma0sel ?? configure the first dma channel to move xr am to aes0kin by writing 0x05 to dma0ncf ?? write 0x01 to dma0nmd to enable wrapping ?? write the xram location of the encryption key to dma0nbah and dma0nbal. ?? write the key length in bytes to dma0nszl ?? clear dma0nszh ?? clear dma0naoh and dma0naol ? configure the second dma channel for aes0bin. ?? select the second dma channel by writing 0x01 to dma0sel. ?? configure the second dma channel to move xram to aes0bin by writing 0x06 to dma0ncf. ?? clear dma0nmd to disable wrapping. ?? write the xram address of the data to be encrypted to dma0nbah and dma0nbal. ?? write the number of bytes to be encrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0naoh and dma0naol. ? configure the third dma channel for aes0xin. ?? select the third dma channel by writing 0x02 to dma0sel. ?? configure the third dma channel to move xram to aes0xin sfr by writing 0x07 to the dma0ncf sfr. ?? clear dma0nmd to disable wrapping. ?? write the xram address of the initializa tion vector to dma0nbah and dma0nbal. ?? write the number of bytes to be encrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0naoh and dma0naol. ? * configure the fo rth dma channel for the aes0yout sfr ?? select the forth channel by writing 0x03 to dma0sel ?? configure the fourth dma channel to move the contents of aes0yout to xram by writing 0x08 to dma0ncf ?? enable transfer complete interrupt by setting bit 7 of dma0ncf ?? clear dma0nmd to disable wrapping ?? write the xram address for the encrypt ed data to dma0nbah and dma0nbal. ?? write the number of bytes to be encrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0naoh and dma0naol. ? clear first four dma in terrupts by clearing bits 0 to 3 in dma0int. ? enable first four dma channels by setting bits 0 to 3 in dma0en ? configure the aes module data flow for xor on input da ta by writing 0x01 to aes0dcfg.
si102x/3x 194 rev. 0.3 ? write key size to bits 1 and 0 of aes0bcfg ? configure the aes core fo r encryption by setting bit 2 of aes0bcfg ? initiate the encryption operation be setting bit 3 of aes0bcfg ? wait on the dma interrupt from dma channel 3 ? disable the aes module by cl earing bit 2 of aes0bcfg ? disable the dma by writing 0x00 to dma0en
rev. 0.3 195 si102x/3x 14.6.3.1. cbc encryption using sfrs ? first configure the aes module for cbc encryption ?? reset aes module by writing 0x00 to aes0bcfg. ?? configure the aes module data flow for xor on input data by writing 0x01 to aes0dcfg. ?? write key size to bits 1 and 0 of aes0bcfg. ?? configure the aes core for encrypti on by setting bit 2 of aes0bcfg. ?? enable the aes core by se tting bit 3 of aes0bcfg. ? repeat alternating write sequence 16 times ?? write plaintext byte to aes0bin. ?? write initialization vector to aes0xin ?? write encryption key byte to aes0kin. ? write remaining encryption key bytes to aes0kin for 192-bit and 256-bit decryption only. ? wait on aes done interrupt or poll bit 5 of aes0bcfg. ? read 16 encrypted bytes from aes0yout. if encrypting multiple blo cks, this process may be re peated. it is not necessa ry reconfigure the aes mod - ule for each block. when using cipher block chaining, the init ialization vector is wr itten to aes0xin for the first block only, as described. additional blocks will chain the encrypted data from the previous block.
si102x/3x 196 rev. 0.3 14.6.4. cbc decryption the aes0 module data flow for cbc decryption is shown in figure 14.6 . the ciphertext is written to aes0bin. for the first block, the init ialization vector is wr itten to aes0xin. for subsequent blocks, the previous block ciphertext is written to aes0xin. aes0dcfg is configured to xor aes0xin with the aes core data output. the xor on the i nput is not used. t he aes core is configured fo r a decryption operation. the decryption key is written to aes0kin. the key size is set to the desired key size. figure 14.6. cbc decryption data flow aes core key in key out data in data out aes0bin aes0xin aes0kin aes0yout aes0dcfg aes0bcfg + + internal state machine
rev. 0.3 197 si102x/3x 14.6.4.1. cbc decryption using dma normally, the aes block is used with the dma. this provides the best performance and lo west power con - sumption. code examples are provided in 8051 comp ile r in dependent c code using the dma. it is highly recommended to use the code examples. the steps are listed here for completeness. ? prepare decryption key, initialization vector, and data to be decrypted in xram. ? the initialization vector should be located immediat ely before the data to be decrypted to decrypt multiple blocks. ? reset the aes module by cl earing bit 2 of aes0bcfg. ? disable the first four dma channels by clearing bits 0 to 3 in dma0en. ? configure the first dm a channel for aes0kin ?? select the first dma channel by writing 0x00 to dma0sel ?? configure the first dma channel to move xr am to aes0kin by writing 0x05 to dma0ncf ?? write 0x01 to dma0nmd to enable wrapping ?? write the xram location of the decryption key to dma0nbah and dma0nbal. ?? write the key length in bytes to dma0nszl ?? clear dma0nszh ?? clear dma0naoh and dma0naol ? configure the second dma channel for aes0bin. ?? select the second dma channel by writing 0x01 to dma0sel. ?? configure the second dma channel to move xram to aes0bin by writing 0x06 to dma0ncf. ?? clear dma0nmd to disable wrapping. ?? write the xram address of the data to be decrypted to dma0nbah and dma0nbal. ?? write the number of bytes to be decrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0naoh and dma0naol. ? configure the third dma channel for aes0xin. ?? select the third dma channel by writing 0x02 to dma0sel. ?? configure the third dma channel to move xr am to aes0xin by writing 0x07 to dma0ncf. ?? clear dma0nmd to disable wrapping. ?? write the xram address of the initializa tion vector to dma0nbah and dma0nbal. ?? write the number of bytes to be decrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0naoh and dma0naol. ? configure the forth dm a channel for aes0yout ?? select the forth channel by writing 0x03 to dma0sel ?? configure the forth dma channel to move the contents of aes0yout to xr am by writing 0x08 to dma0ncf ?? enable transfer complete interrupt by setting bit 7 of dma0ncf ?? clear dma0nmd to disable wrapping ?? write the xram address for the decrypt ed data to dma0nbah and dma0nbal. ?? write the number of bytes to be decrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0naoh and dma0naol. ? clear first four dma in terrupts by clearing bits 0 to 3 in dma0int. ? enable first four dma channels setting bits 0 to 3 in dma0en ? configure the aes module data flow for xor on output data by writing 0x02 to aes0dcfg. ? write key size to bits 1 and 0 of aes0bcfg ? configure the aes core fo r decryption by clearing bit 2 of aes0bcfg ? initiate the decryption operation be setting bit 3 of aes0bcfg ? wait on the dma interrupt from dma channel 3 ? disable the aes module by cl earing bit 2 of aes0bcfg ? disable the dma by writing 0x00 to dma0en
si102x/3x 198 rev. 0.3 14.6.4.2. cbc decryption using sfrs ? first configure aes module for cbc block cipher mode decryption ?? reset the aes module by writing 0x00 to aes0bcfg. ?? configure the aes module data flow for xor on output data by writ ing 0x02 to aes0dcfg. ?? write key size to bits 1 and 0 of aes0bcfg. ?? configure the aes core for decrypti on by setting bit 2 of aes0bcfg. ?? enable the aes core by se tting bit 3 of aes0bcfg. ? repeat alternating write sequence 16 times ?? write plaintext byte to aes0bin. ?? write encryption key byte to aes0kin. ? write remaining encryption key bytes to aes0kin for 192-bit and 256-bit decryption only. ? wait on aes done interrupt or poll bit 5 of aes0bcfg. ? repeat alternating write read sequence 16 times ?? write initialization vector to aes0xin ?? read decrypted data from aes0yout if decrypting multiple blo cks, this process may be re peated. it is not necessa ry reconfigure the aes mod - ule for each block. when using cipher block chaining the initialization ve ctor is written to aes0xin for the first block only, as described. additional blocks will c hain the ciphertext data from the previous block.
rev. 0.3 199 si102x/3x 14.6.5. counter mode the counter (ctr) mode uses a sequential counter whic h is incremented after each block. this turns the block cipher into a stream cipher. this algorithm is shown in figure 14.4 . note that the decryption operation actually uses the encryption key and encryption bl ock ciphe r . the xor operation is always on the output of the cipher. the counter is a 16-byte block. often, several bytes of the counter are initialized to a nonce (number used once). the last byte of the counter is incremented and propagated. thus, the counter is treated as a 16-byte big endian integer. figure 14.7. counter mode encryption decryption encryption cipher encryption key ciphertext counter (0x00...00) plaintext xor encryption cipher encryption key plaintext ciphertext xor encryption cipher encryption key ciphertext plaintext xor encryption cipher encryption key plaintext ciphertext xor counter (0x00...01) counter (0x00...01) counter (0x00...00)
si102x/3x 200 rev. 0.3 14.6.5.1. ctr data flow the aes0 module data flow for ctr encryption and decry ption shown in figure 14.5 . the data flow is the same for encryption and decryption. aes 0dc fg is always configur ed to xor aes0xin with the aes core output.the xor on the input is not used. the aes core is configur ed for an encryption operation. the encryption key is written to aes0kin. the key size is se t to the desired key size. for an encryption operation, the plaintext is writ te n to aes0 bin and the ciphertext is read from aes0yout. for decryption, the ciph ertext is written to aes0bin and the plaintext is read from aes0yout. note the counte r must be incremented after each block using software. figure 14.8. counter mode data flow aes core key in key out data in data out aes0bin aes0xin aes0kin aes0yout aes0dcfg aes0bcfg + + internal state machine
rev. 0.3 201 si102x/3x 14.6.6. ctr encryp tion using dma normally, the aes block is used with the dma. this provides the best performance and lo west power con - sumption. code examples are provided in 8051 comp ile r in dependent c code using the dma. it is highly recommended to use the code examples. the steps are listed here for completeness. ? prepare encryption key, counter, and data to be encrypted in xram. ? reset the aes module by cl earing bit 2 of aes0bcfg. ? disable the first four dma channels by clearing bits 0 to 3 in dma0en. ? configure the first dm a channel for aes0kin ?? select the first dma channel by writing 0x00 to dma0sel ?? configure the first dma channel to move xr am to aes0kin by writing 0x05 to dma0ncf ?? clear dma0nmd to disable wrapping. ?? write the xram location of the encryption key to dma0nbah and dma0nbal. ?? write the key length in bytes to dma0nszl ?? clear dma0nszh ?? clear dma0naoh and dma0naol ? configure the second dma channel for aes0bin. ?? select the second dma channel by writing 0x01 to dma0sel. ?? configure the second dma channel to move xram to aes0bin sfr by writing 0x06 to the dma0ncf sfr. ?? clear dma0nmd to disable wrapping. ?? write the xram address of the data to be encrypted to dma0nbah and dma0nbal. ?? write the number of bytes to be encrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl ?? clear the dma0nszh sfr ?? clear the dma0naoh and dma0naol sfrs. ? configure the third dma ch annel for the aes0xin sfr. ?? select the third dma channel by writing 0x02 to dma0sel. ?? configure the third dma channel to move xr am to aes0xin by writing 0x07 to dma0ncf. ?? clear dma0nmd to disable wrapping. ?? write the xram address of the counter to dma0nbah and dma0nbal. ?? write the number of bytes to be encrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0naoh and dma0naol. ? configure the fourth dma channel for aes0yout ?? select the fourth channel by writing 0x03 to dma0sel ?? configure the forth dma channel to move the contents of aes0yout to xr am by writing 0x08 to dma0ncf ?? enable transfer complete interrupt by setting bit 7 of dma0ncf ?? clear dma0nmd to disable wrapping ?? write the number of bytes to be encrypted in mu ltiples of 16 bytes to dma0nszh and dma0nszl. ?? clear dma0naoh and dma0naol. ? clear first four dma in terrupts by clearing bits 0 to 3 in dma0int. ? enable first four dma channels setting bits 0 to 3 in dma0en. ? configure the aes module data flow for xor on output data by writing 0x02 to aes0dcfg. ? write key size to bits 1 and 0 of aes0bcfg ? configure the aes core fo r encryption by setting bit 2 of aes0bcfg ? initiate the encryption operation be setting bit 3 of aes0bcfg ? wait on the dma interrupt from dma channel 3 ? disable the aes module by cl earing bit 2 of aes0bcfg ? disable the dma by writing 0x00 to dma0en ? increment counter and repeat all steps for additional blocks
si102x/3x 202 rev. 0.3 14.6.6.1. ctr encryption using sfrs ? first configure aes module for ctr encryption ?? reset the aes module by writing 0x00 to aes0bcfg. ?? configure the aes module data flow for xor on output data by writ ing 0x02 to aes0dcfg. ?? write key size to bits 1 and 0 of aes0bcfg. ?? configure the aes core for encrypti on by setting bit 2 of aes0bcfg. ?? enable the aes core by se tting bit 3 of aes0bcfg. ? repeat alternating write sequence 16 times ?? write plaintext byte to aes0bin. ?? write counter by te to aes0xin ?? write encryption key byte to aes0kin. ? write remaining encryption key bytes to aes0kin for 192-bit and 256-bit decryption only. ? wait on aes done interrupt or poll bit 5 of aes0bcfg. ? read 16 encrypted bytes from aes0yout. if encrypting multiple blocks, increment the count er and re peat this process. it is not necessary reconfigure the aes module fo r each block.
rev. 0.3 203 si102x/3x sfr address = 0xe9; sfr page = 0x2; not bit-addressable sfr definition 14.1. aes0bcfg: aes block configuration bit 7 6 5 4 3 2 1 0 name done busy en enc ksize type r r r/w r r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 5 done done flag. this bit is set upon completion of an encr yption operation. when used with the dma, the done bit signals the start of the out transfer. when used without the dma, the done flag indicates data is ready to be read from aes0yout. the done bit is not cleared by hardware and must be cleared to zero by software at the start of the next encryption operation. 4 busy aes busy. this bit is set while the aes bl ock is engaged in an encryption or decryption operation. this bit is read only. 3 en aes enable. this bit should be set to 1 to initiate an encryp tion o r decryption operation. clearing this bit to 0 will reset the aes module. 2 enc encryption/decryption select. this is set to 1 to select an encryption operation. clearin g this bit to 0 will select a decryption operation. 1:0 size[1:0] aes key size. these bits select the key si ze for encryption/ decryption. 00: 128-bits (16-bytes) 01: 198-bits (24-bytes) 10: 256-bits (32-bytes) 11: reserved
si102x/3x 204 rev. 0.3 sfr address = 0xea; sfr page = 0x2; not bit-addressable sfr definition 14.2. aes0dcfg: aes data configuration bit 7 6 5 4 3 2 1 0 name outsel[1:0] xorin type r r r r r r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 2:1 outsel[1:0] data select. these bits select the output da t a source for the aes0yout sfr. 00: direct aes data 01: aes data xor with aes0xin 10: inverse key 11: reserved 0 xorin xor input enable. setting this bit with enable the xor da t a path on the aes input. if enabled, aes0bin will be xored with the aes0xin and the results will feed into the aes data input. clearing this bit to 0 will di sable the xor gate on the input. the con - tents of aes0bin will go directly into the aes data input.
rev. 0.3 205 si102x/3x sfr address = 0xeb; sfr page = 0x2; not bit-addressable sfr definition 14.3. aes0bin: aes block input bit 7 6 5 4 3 2 1 0 name aes0bin[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 aes0bin[7:0] aes block input. during an encryption operation, the plaintext is wri tten to the aes0bin sfr . during an decryption operation, the ciphertext is written to the aes0bin sfr. during a key inversion the encryption key is written to aes0bin. when used with the dma, the dma will write direc t ly to this sfr. the aes0bin may be used in conjunction with the aes 0xin sfr for some cipher block modes. when used without the dma, aes0bin, aes0xin, and aes0kin must be written in sequence. reading this register will yield the last va lue wri tten. this ca n be used for debug purposes.
si102x/3x 206 rev. 0.3 sfr address = 0xec; sfr page = 0x2; not bit-addressable sfr address = 0xed; sfr page = 0x2; not bit-addressable sfr definition 14.4. aes0xin: aes xor input bit 7 6 5 4 3 2 1 0 name aes0xin[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 aes0xin[7:0] aes xor input. the aes0xin may be used in conjunction with the aes0 bin sfr for some cipher block modes. when used with the dma, the dma will write directly to this sfr. when used without the dma - aes0bin, a es0x in, and aes0kin must be written in sequence. reading this register will yield the last va lue w ritten. this ca n be used for debug purposes. sfr definition 14.5. aes0kin: aes key input bit 7 6 5 4 3 2 1 0 name aes0kin[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 aes0kin[7:0] aes key input. during an encryption operation, the plaint ext is written to the aes0bin sfr . during an decryption oper ation, the ciphertext is written to the aes0bin sfr. during a key inversion the encryption key is written to aes0bin. when used with the dma, the dma will w r ite directly to this sfr. the aes0bin may be used in conjunctio n with the aes0xin sfr for some cipher block modes. when used without the dma - aes0bin, aes0xin, and aes0kin must be written in se quence.
rev. 0.3 207 si102x/3x sfr address = 0xf5; sfr page = 0x2; not bit-addressable sfr definition 14.6. aes0yout: aes y output bit 7 6 5 4 3 2 1 0 name aes0yout[7:0] type r r r r r r r r reset 0 0 0 0 0 0 0 0 bit name function 7:0 aes0yout[7:0] aes y output. upon completion of an encryption/decryption operation the output data may be re ad, one byte at a time, from the aes0yout sfr. when used with the dma, the dma will read directly from this sfr. the aes0yout sfr may be used in c onjunction with the ae s0xin sfr for some cipher block modes. when used without the dma, the firmware should wait on th e done flag be fore reading from the aes0yout sfr. when used without the dma and using xor on the output, one byte should be wr itten to aes0xin bef ore reading each by te from aes0yout. reading this register over the c2 inte rface will not incremen t the output data.
si102x/3x 208 rev. 0.3 15. encoder/decoder the encoder/decoder consists of three 8-bit data re gisters, a control register and an encoder/decoder logic block. the size of the input data depends on the mode. the in put d ata for manchester encoding is one byte. for manchester decoding it is two bytes. three-out-of-six encoding is two bytes. three-out-of six decoding is three bytes. the output size also depends on the mode select e d . the input and output data size are shown below: the input and output data is always right justified. so for manchester mode the input uses only enc0l and the output data is only in enc0m and enc0l. enc0h is not used for manchester mode table 15.1. encoder input and output data sizes input data size output data size operation bytes bytes manchester encode 1 2 manchester decode 2 1 three out of six encode 2 3 three out of six decode 3 2
rev. 0.3 209 si102x/3x 15.1. manchester encoding to encode manchester data, first clear the mode bit for manchester encoding or decoding. to encode, one byte of data is written to the data register enc0l. setting the enc bit will initiate enc o ding. after enco ding, the encoded data will be in enc0m and enc0l. the upper nibble of the input data is encoded and placed in enc0m. the lower nibble is encoded and placed in enc0l. note that the input data should be readable in the data re gister u ntil the encode bit is set. once the ready bit is set, the input data has been replaced by the output data. the enc and dec bits are self clearing. the ready bi t is not cleared by hardware and must be cleared manually. the control register does not need to be bit addressable. the ready bit can be cleared while setting the enc or dec bit using a dire ct or immediate sfr mov instruction. table 15.2. manchester encoding input data encoded output nibble byte dec hex bin bin hex dec 0 0 0000 10101010 aa 170 1 1 0001 10101001 a9 169 2 2 0010 10100110 a6 166 3 3 0011 10100101 a5 165 4 4 0100 10011010 9a 154 5 5 0101 10011001 99 153 6 6 0110 10010110 96 150 7 7 0111 10010101 95 149 8 8 1000 01101010 6a 106 9 9 1001 01101001 69 105 10 a 1010 01100110 66 102 11 b 1011 01100101 65 101 12 c 1100 01011010 5a 90 13 d 1101 01011001 59 89 14 e 1110 01010110 56 86 15 f 1111 01010101 55 85
si102x/3x 210 rev. 0.3 15.2. manchester decoding two bytes of manchester data are written to enc0m an d enc0l sfrs. then the dec bit is set to initiate decoding. after decoding the ready bi t will be set. if the data is not a va lid encoded manchester data, the error bit will be set, and the output will be all ffs. the encoding and decoding process should be symmetric. data can be written to the enc0l sfr, then encoded, then decoding will giv e the original data. table 15.3. manchester decoding input decoded output byte nibble bin hex dec dec hex bin 01010101 55 85 15 f 1111 01010110 56 86 14 e 1110 01011001 59 89 13 d 1101 01011010 5a 90 12 c 1100 01100101 65 101 11 b 1011 01100110 66 102 10 a 1010 01101001 69 105 9 9 1001 01101010 6a 106 8 8 1000 10010101 95 149 7 7 0111 10010110 96 150 6 6 0110 10011001 99 153 5 5 0101 10011010 9a 154 4 4 0100 10100101 a5 165 3 3 0011 10100110 a6 166 2 2 0010 10101001 a9 169 1 1 0001 10101010 aa 170 0 0 0000
rev. 0.3 211 si102x/3x 15.3. three-out-of-six encoding three out of six encoding is similar to manchester encoding. in three-out-of-six encoding a nibble is encoded as a six-bit symbol. four nibbles are encoded as 24-bits (three bytes). two bytes of data to be encoded are written to en c0m an d enc0l. the mode bit is set to 1 for three- out-of-six encoding. setting th e enc bit will initiate encoding. after encoding, the three encoded bytes are in enc2-0. table 15.4. three-out-of-six encoding nibble input encoded output nibble symbol dec hex bin bin dec hex octal 0 0 0000 010110 22 16 26 1 1 0001 001101 13 0d 15 2 2 0010 001110 14 0e 16 3 3 0011 001011 11 0b 13 4 4 0100 011100 28 1c 34 5 5 0101 011001 25 19 31 6 6 0110 011010 26 1a 32 7 7 0111 010011 19 13 23 8 8 1000 101100 44 2c 54 9 9 1001 100101 37 25 45 10 a 1010 100110 38 26 46 11 b 1011 100011 35 23 43 12 c 1100 110100 52 34 64 13 d 1101 110001 49 31 61 14 e 1110 110010 50 32 62 15 f 1111 101001 41 29 51
si102x/3x 212 rev. 0.3 15.4. three-out-of-six decoding three-out-of-six decoding is a similar inverse process. three bytes of encoded data are written to enc2- 0. the dec bit is set to initiate decoding. the r eady bit will be set when de coding is co mplete. the error bit will be set if the input date is not valid three- out-of-six data. the three-out-of-six encoder decode process is also sym metric. two bytes of arbitrary data may be writ - ten to enc0m-enc0l, then encoded, then decoding will yield the original data. table 15.5. three-out-of-six decoding input decoded output symbol nibble bin octal dec dec hex bin 001011 13 11 3 3 0011 001101 15 13 1 1 0001 001110 16 14 2 2 0010 010011 23 19 7 7 0111 010110 26 22 0 0 0000 011001 31 25 5 5 0101 011010 32 26 6 6 0110 011100 34 28 4 4 0100 100011 43 35 11 b 1011 100101 45 37 9 9 1001 100110 46 38 10 a 1010 101001 51 41 15 f 1111 101100 54 44 8 8 1000 110001 61 49 13 d 1101 110010 62 50 14 e 1110 110100 64 52 12 c 1100
rev. 0.3 213 si102x/3x 15.5. encoding/decoding with sfr access the steps to perform a encode/decode operation us ing sfr access with the enc0 module are as follow: 1. clear enc0cn by writing 0x00. 2. write the input data to enc0h:m:l. 3. write the operation value to enc0cn setting enc, dec, and mode bits as desired and clearing all other bits. a. write 0x10 for manchester decode operation. b. write 0x11 for three-out-of-six decode operation. c. write 0x20 for manchester encode operation. d. write 0x21 for three-out-of-six encode operation. 4. wait on the ready bit in enc0cn. 5. for a decode operation only, check the error bit in enc0cn for a decode error. 6. read the results from enc0h:m:l. 7. repeat steps 2-6 for all remaining data. note that all of the enc0 sfrs are on sfr page 0x2. the ready and error must be cleared in enc0cn with each o per ation. 15.6. decoder error interrupt the encoder/decoder peripheral is capable of generating an interrupt on a decoder error. normally, when used with the dma, the dma will tr ansfer the entire specified transfer size to and from the encoder/decoder peripheral. if a decoder error occurs, decoding will co ntinue until all data has been decoded. the error bit in the enc0cn sfr will indicate if an error has occurred anywhere in the dma transfer. some applications will discar d the entire packet after a single decoder error. a borting the decoder operation at the first decoder erro r will conserve energy and minimize packet receiver turn-around time. the decoder interrupt service routine should first st all the enc0 dma channels by selecting the enc0 dma channels and then setting the stall bit. then di sable the dma channels by clearing the relevant dma0en bits. in addition, clear any enc dma channel interrupts by clearing the respective bits in dma0nint.
si102x/3x 214 rev. 0.3 15.7. using the enc0 module with the dma the steps for encoding/decoding using the dma are as follows. 1. clear the enc module by writing 0x00 to the enc0cn sfr. 2. configure the first dma channel for the xram-to-enc0 input transfer: a. disable the first dma channel by clearing the corresponding bit in dma0en. b. select the first dma chan nel by writing to dma0sel. c. configure the selected dma channel to use the xram-to-enc0 input peripheral request by writing 0x00 to dma0ncf. d. set the endian bit in dma0ncf to enable big-endian multi-byte dma transfers. e. write 0 to dma0nm d to disable wrapping. f. write the address of the first byte of input data dma0nbah:l. g. write the size of the input data transfer in bytes to dma0nszh:l. h. clear the address offset sfrs dma0a0h:l. 3. configure the second dma channel for the enc0-to-xram output transfer: a. disable the second dma channel by cl earing the corresponding bit in dma0en. b. select the second dma ch annel by writing to dma0sel. c. configure the selected dma channel to use t he spi1dat-to-xram output peripheral request by writing 0x01 to dma0ncf. d. set the endian bit in dma0ncf to enable big-endian multi-byte dma transfers. e. enable dma interrupts for the second channel by setting bit 7 of dma0ncf. f. write 0 to dma0nmd to disable wrapping. g. write the address for the first byte of the output data to dma0nbah:l. h. write the size of the output data transfer in bytes to dma0nszh:l. i. clear the address offset sfrs dma0a0h:l. j. enable the interrupt on the second channel by setting the corresponding bit in dma0int. 4. clear the interrupt bits in dma0int for both channels. 5. enable dma in terrupts by setting bit 5 of eie2. 6. if desired for a decode operation, enable the error interrupt bit by setting bit 6 of eie2. 7. write the operation value to enc0cn setting enc, dec, and mode bits for the desired operation. the dma bit and endian bits must be set. the ready bits and error bits must be cleared. a. write 0x16 for manchester decode operation. b. write 0x17 for three-out-of-six decode operation. c. write 0x26 for manchester encode operation. d. write 0x27 for three-out-of-six encode operation. 8. wait on the dma interrupt. 9. clear the dma enables in the dma0en sfr. 10. clear the dma interrup ts in the dma0int sfr. 11. for a decode operation only, check the error bit in enc0cn for a decode error. note that the encoder and all dma channels should be configured for big-endian mode.
rev. 0.3 215 si102x/3x sfr address = 0xc5; sfr page = 0x2; not bit-addressable sfr definition 15.1. enc0cn: encoder decoder 0 control bit 7 6 5 4 3 2 1 0 name ready error enc dec dma endian mode type r r r/w r/w r r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ready ready flag. 6 error error flag. 5 enc encode. setting this bit will initia te an enc ode operation. 4 dec decode. setting this bit will initia te a decode operation. 2 dma dm a mode enable. this bit should be set when using the encoder/decoder with the dma. 1 endian big-endian dma mode select. this bit should be set when using the dma with big-endian multiple byte dma trans - fers. the dma must also be configured for the same endian mode. 0 mode mode. 0: select manchester encoding or decoding. 1:select three-out-of-six en co ding or decoding.
si102x/3x 216 rev. 0.3 sfr page = 0x2; sfr addres s = 0xc2; bit-addressable sfr page = 0x2; sfr addres s = 0xc3; bit-addressable sfr page = 0x2; sfr addres s = 0xc4; bit-addressable sfr definition 15.2. enc0l: enc0 data low byte bit 7 6 5 4 3 2 1 0 name enc0l[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 enc0l[7:0] enc0 data low byte. sfr definition 15.3. enc0m: enc0 data middle byte bit 7 6 5 4 3 2 1 0 name enc0m[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 enc0m[7:0] enc0 data middle byte. sfr definition 15.4. enc0h: enc0 data high byte bit 7 6 5 4 3 2 1 0 name enc0h[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 enc0h[7:0] enc0 data high byte.
rev. 0.3 217 si102x/3x 16. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchange with the si102x/3x's resources and peripherals. the cip-51 controller core duplicates t he sfrs found in a typical 8051 implementation as well as implementing additional sfrs used to configure and access the sub-systems unique to the si102x/3x. this allows the addition of new functionality while retainin g compatibility with the mcs-51? instruction set. ta b l e 16.3 lists the sfrs implemented in the si102x/3x device family. the sfr registers are accessed anytime the direct ad dr essing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g., p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing unoccupied addresses in the sfr space will have an indeterminate effect and should be avoided. refer to the corresponding pages of the data sheet, as indicated in table 16.3 , for a detailed description of each register. 16.1. sfr paging the cip-51 features sfr paging , allowing the device to map many sfrs into the 0x80 to 0xff memory address space. the sfr memory space has 256 pages . in this way, each memory location from 0x80 to 0xff can access up to 256 sfrs. the si102x/3x family of dev ices utilizes two sfr pages: 0x00 and 0x0f. sfr pages are selected using the special function register page selection register, sfrpage (see sfr definition 11.3). the procedure for reading and writing an sfr is as follows: 1. select the appropriate sfr page number using the sfrpage register. 2 . use direct accessing mode to read or write th e special function register (mov instruction). 16.2. interrupts and sfr paging when an interrupt occurs, the current sfrpage is pu shed onto the sfr page stack. upon execution of the reti instructio n, the sfr page is automatically restored to the sfr page in use prior to the interrupt. this is accomplished via a three-byte sfr page stack . the top byte of the stack is sfrpage, the current sfr page. the second byte of the sfr page stack is sfrnext. the third, or bottom byte of the sfr page stack is sfrlast. upon an interrupt, the current sfrpage value is pushed to the sfrnext byte, and the value of sfrnext is pushed to sfrlast. on a return from interrupt, the sfr page stack is popped resulting in the value of sfrnext returning to the sfrpage register, thereby restoring the sfr page context without software intervention. the value in sfrlast (0x00 if there is no sfr page value in the bottom of the stack) of the stack is placed in sfrnext register. if desired, the values stored in sfrnext and sfrlast may be modified during an interrupt, enabling th e cpu to return to a different sfr page upon execution of the reti instruction (on interrupt exit). modifying registers in the sfr page stack does not cause a push or pop of the stack. only interrupt calls and returns will cause push/pop oper - ations on the sfr page stack. on the si102x/3x devices, the sfrpage must be explicitly set in the in ter rupt service routine.
si102x/3x 218 rev. 0.3 figure 16.1. sfr page stack automatic hardware switching of the sfr page on interrupts may be enabled or disabled as desired using the sfr automatic page control enab le bit located in the sfr page control register (sfr0cn). this function defaults to ?enabled? upon reset. in this way, the autoswitching functi on will be enabled unless dis - abled in software. a summary of the sfr locations (address and sfr page) are provided in ta b l e 16.3 in the form of an sfr memory map. each memory location in the map has an sfr page row, denoting the page in which that sf r re sides. certain sfrs are acce ssible from all sfr pages, and are denoted by the ?(all pages)? designation. for example, the port i/o registers p0, p1, p2, and p3 all have the ?(all pages)? designa - tion, indicating these sfrs are accessible from all sfr p age s regardless of the sfrpage register value. sfrnext sfrpage sfrlast cip-51 interrupt logic sfrpgcn bit
rev. 0.3 219 si102x/3x 16.3. sfr page stack example the following is an example that shows the operation of the sfr page stack during interrupts. in this example, the sfr control register is left in the de fault enabled state (i.e., sfrpgen = 1), and the cip-51 is executing in-line code that is writing values to smbus address register (sfr ?smb0adr?, located at address 0xf4 on sfr page 0x0). the device is also using the spi peripheral (spi0) and the programma - ble counter array (pca0) peripheral to generate a pw m ou tp ut. the pca is timing a critical control func - tion in its interrupt se r v ice routine, and so its associated isr is set to high priority. at this point, the sfr page is set to access the sm b0adr sfr (sfrpage = 0x0). see figure 16.2 . figure 16.2. sfr page stack while using sfr page 0x0 to access smb0adr while cip-51 executes in-line code (writing a value to smb0adr in this example), the spi0 interrupt occurs. the cip-51 vectors to the spi0 isr and pushes the current sfr page value (sfr page 0x0f) into sfrnext in the sfr page stack. sf rpage is considered the ?top? of the sfr page stack. software may switch to any sfr page by writing a new value to the sfrpage register at any time during the spi0 isr. see figure 16.3 . 0x0f (smb0adr) sfrpage sfrlast sfrnext sfr page stack sfr's
si102x/3x 220 rev. 0.3 figure 16.3. sfr page stack after spi0 interrupt occurs while in the spi0 isr, a pca inte rrupt occurs. recall the pca interrupt is configured as a high priority interrupt, while the spi0 inte rrupt is configured as a low priority interrup t. thus, the cip-51 will now vector to the high priority pca isr. upon doing so, the cip-51 will automatically plac e the sfr page needed to access the pca?s special function registers into th e sfrpage register, sfr page all pages. the value that was in the sfrpage register before the pca inte rrupt (sfr page 0x00 for spi00) is pushed down the stack into sfrnext. likewise, the value that was in the sfrnext register before the pca interrupt (in this case sfr page 0x0f for smb0adr) is pushed down to the sfrlast register, the ?bottom? of the stack. note that a value st ored in sfrlast (via a previous softwa re write to the sfrlast register) will be overwritten. see figure 16.4 . 0x00 (spi0) 0x0f (smb0adr) sfrpage sfrlast sfrnext sfrpage pushed to sfrnext sfr page 0x00 automatically pushed on stack in sfrpage on spi0 interrupt
rev. 0.3 221 si102x/3x figure 16.4. sfr page stack upon pca interrupt occurring during a spi0 isr on exit from the pca interrupt servic e routine, the cip-51 will return to the spi0 isr. on execution of the reti instruction, sfr page all page s used to access the pca registers will be automatica lly popped off of the sfr page stack, and the conten ts of the sfrnext register will be moved to the sfrpage register. software in the spi0 isr can continue to access sfrs as it did pr ior to the pca interrupt. likewise, the contents of sfrlast are moved to the sfrnext register. recall this was the sfr page value 0x0f being used to access smb0adr before the spi0 interrupt occurred. see figure 16.5 . 0x00 (pca0) 0x00 (spi0) 0x0f (smb0adr) sfrpage sfrlast sfrnext sfr page 0x00 automatically pushed on stack in sfrpage on pca interrupt sfrpage pushed to sfrnext sfrnext pushed to sfrlast
si102x/3x 222 rev. 0.3 figure 16.5. sfr page stack upon return from pca interrupt on the execution of the re ti instruction in the spi0 isr, the valu e in sfrpage register is overwritten with the contents of sfrnext. the cip-51 may now acce ss the smb0adr register as it did prior to the interrupts occurring. see figure 16.6 . 0x00 (spi0) 0x0f (smb0adr) sfrpage sfrlast sfrnext sfr page 0x00 automatically popped off of the stack on return from interrupt sfrnext popped to sfrpage sfrlast popped to sfrnext
rev. 0.3 223 si102x/3x figure 16.6. sfr page stack upon return from spi0 interrupt in the example above, all three bytes in the sfr page stack are accessible via the sfrpage, sfrnext, and sfrlast special function registers. if the stack is altered while servicing an in terrupt, it is possible to return to a different sfr page upon interrupt exit than selected prior to the interrupt call. direct access to the sfr page stack can be useful to enable real-t ime operating systems to control and manage context switching between multiple tasks. push operations on the sfr page stack only occur on inter r upt service, and pop operations only occur on interrupt exit (execution on the reti instruction). the automatic switching of the sfrpage and operation of the sfr page stack as described above can be disabled in software by clearing the sfr automatic page enable bit (sfrpgen) in the sfr page control register (sfr0cn). see sfr definition 16.1 . 0x0f (smb0adr) sfrpage sfrlast sfrnext sfr page 0x00 automatically popped off of the stack on return from interrupt sfrnext popped to sfrpage
si102x/3x 224 rev. 0.3 ;sfr page = 0xf; sfr address = 0x8e sfr definition 16.1. sfrpgcn: sfr page control bit 7 6 5 4 3 2 1 0 name sfrpgen type r r r r r r r r/w reset 0 0 0 0 0 0 0 1 bit name function 7:1 unused read = 0000000b; write = don?t care 0 sfrpgen sfr automatic page control enable. upon interrupt, the c8051 core will vector to the specified interr upt service routine and a utomatically switch the sfr page to the corresponding peripheral or function?s sfr page. this bit is used to control this autopaging function. 0: sfr automatic paging disa bled. the c8051 core w ill no t automatically change to the appropriate sfr page (i.e., the sfr page that contains the sfrs for the periph - eral/function that was the source of the interrupt). 1: sfr automatic paging enabled. upon i n terrupt, the c80 51 will switch the sfr page to the page that contains the sfrs fo r the peripheral or function that is the source of the interrupt.
rev. 0.3 225 si102x/3x sfr page = all pages; sfr address = 0xa7 sfr definition 16.2. sfrpage: sfr page bit 7 6 5 4 3 2 1 0 name sfrpage[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 sfrpage[7:0] sfr page bits. represents the sfr page the c8051 core uses when reading or modifying sfrs. write: sets the sfr page. read: byte is the sfr page the c8051 core is using. when enabled in the sfr page control register (s fr 0cn), the c8051 core will automatically switch to the sfr page that contains the sfrs of the correspond - ing peripheral/function that caused the interrupt, and return to the previous sfr p a ge upon return from interrupt (unless sfr stack was altered before a return - ing from the interrupt). sfrpage is th e top byte of the sfr page stack, and push/pop events of this stack are caused by interrupts (and not by reading/writ - ing to the sfrpage register)
si102x/3x 226 rev. 0.3 ;sfr page = all pages; sfr address = 0x85 sfr definition 16.3. sfrnext: sfr next bit 7 6 5 4 3 2 1 0 name sfrnext[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 sfrnext[7:0] sfr page bits. this is the value that will go to the sfr pa ge register upon a return from inter - rupt. write: sets the sfr page contained in th e second byte of the sfr stack. this will cause the sfrpage sfr to have this sfr page value upon a return from interrupt. read: returns the value of the sfr page contained in the second byte of the sfr st ack. sfr p age context is retained upon interrupts/return from interrupts in a 3 byte sfr page st ack: sfrpage is the firs t entry, sfrnext is the second, and sfrlast is the third entry. the sfr stack bytes may be used alter the context in the sfr page stack, and will not caus e the stack to ?push? or ?pop?. only interrupts and return from interrupts cause pushes and pops of the sfr page stack.
rev. 0.3 227 si102x/3x ;sfr page = all pages; sfr address = 0x86 sfr definition 16.4. sfrlast: sfr last bit 7 6 5 4 3 2 1 0 name sfrlast[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 sfrlast[7:0] sfr page stack bits. this is the value that will go to the sfrn ext register upon a return from inter - r upt. write: sets the sfr page in the last en try of the sfr stack. this will cause the sfrnext sfr to have this sfr page va lue upon a return from interrupt. read: returns the value of the sfr page contained in the last entry of the sfr stack. sfr p age context is retained upon interrupts/return from interrupts in a 3 byte sfr page st ack: sfrpage is the firs t entry, sfrnext is the second, and sfrlast is the third entry. the sfr stack bytes may be used alter the context in the sfr page stack, and will not caus e the stack to ?push? or ?pop?. only interrupts and return from interrupts cause pushes and pops of the sfr page stack.
si102x/3x 228 rev. 0.3 table 16.1. sfr map (0xc0?0xff) addr. page 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) 0xf8 0x0 spi0cn pca0l pca0h pca0cpl0 pca0cph0 pca0cpl4 pca0cph4 vdm0cn 0x2 spi1cn pc0dcl pc0dch pc0int0 pc0int1 dc0rdy 0xf p4mdout p5mdout p6mdout p7mdout clkmode pclken 0xf0 0x0 p0mdin p1mdin p2mdin smb0adr smb0adm eip1 eip2 0x2 pc0cmp1l pc0cmp1m pc0cmp1h pc0hist aes0yout 0xf p3mdin p4mdin p5mdin p6mdin pclkact 0xe8 0x0 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 pca0cpl3 pca0cph3 rstsrc 0x2 aes0bcfg aes0dcfg aes0bin aes0xin aes0kin 0xf deviceid revid 0xe0 0x0 acc xbr0 xbr1 xbr2 it01cf eie1 eie2 0x2 pc0cmp0l pc0cmp0m pc0cmp0h pc0th 0xf xbr0 xbr1 xbr2 it01cf 0xd8 0x0 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 pca0cpm3 pca0cpm4 pca0pwm 0x2 pc0md pc0ctr0l pc0trml pc0ctr0h pc0ctr1l pc0trmh pc0ctr1h 0xf p4 p5 p6 p7 0xd0 0x0 psw ref0cn pca0cpl5 pca0cph5 p0skip p1skip p2skip p0mat 0x2 dma0sel dma0en dma0int dma0mint dma0busy dma0nmd pc0pcf 0xf 0xc8 0x0 tmr2cn reg0cn tmr2rll tmr2rlh tmr2l tmr2h pca0cpm5 p1mat 0x2 dma0ncf dma0nbal dma0nbah dma0naol dma0naoh dma0nszl dma0nszh 0xf 0xc0 0x0 smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth p0mask 0x2 pc0stat enc0l enc0m enc0h enc0cn vreginsdl vreginsdh 0xf
rev. 0.3 229 si102x/3x table 16.2. sfr map (0x80?0xbf) addr. page 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) 0xb8 0x0 ip iref0cn adc0ac adc0mx adc0cf adc0l adc0h p1mask 0x2 crc1in crc1outl crc1outh crc1poll crc1polh crc1cn 0xf iref0cf adc0pwr adc0tk toffl toffh 0xb0 0x0 p3 oscxcn oscicn pmu0md pmu0cf pmu0fl flkey 0x2 dc0cn dc0cf dc0md lcd0chpcn lcd0bufmd 0xf p3mdout oscifl oscicl flscl 0xa8 0x0 ie clksel emi0cn emi0cf rtc0adr rtc0dat rtc0key emi0tc 0x2 lcd0clkdivl lcd0clkdivh lcd0mscn lcd0mscf lcd0chpcf lcd0chpmd lcd0vbmcf 0xf clksel p6drv p7drv lcd0bufcf 0xa0 0x0 p2 spi0cfg spi0ckr spi0dat p0mdout p1mdout p2mdout sfrpage 0x2 spi1cfg spi1ckr spi1dat lcd0pwr lcd0cf lcd0vbmcn 0xf p3drv p4drv p5drv p0drv p1drv p2drv 0x98 0x0 scon0 sbuf0 cpt1cn cpt0cn cpt1md cpt0md cpt1mx cpt0mx 0x2 lcd0dd lcd0de lcd0df lcd0cntrst lcd0cn lcd0blink lcd0togr 0xf lcd0bufcn 0x90 0x0 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h 0x2 lcd0d6 lcd0d7 lcd0d8 lcd0d9 lcd0da lcd0db lcd0dc 0xf crc0dat crc0cn crc0in crc0flip crc0auto crc0cnt 0x88 0x0 tcon tmod tl0 tl1 th0 th1 ckcon psctl 0x2 lcd0d0 lcd0d1 lcd0d2 lcd0d3 lcd0d4 lcd0d5 0xf sfrpgcn 0x80 0x0 p0 sp dpl dph psbank sfrnext sfrlast pcon 0x2 0xf
si102x/3x 230 rev. 0.3 table 16.3. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page adc0ac 0xba 0x0 adc0 accumulator configuration 88 adc0cf 0xbc 0x0 adc0 configuration 87 adc0cn 0xe8 all pages adc0 control 86 adc0gth 0xc4 0x0 adc0 greater-than compare high 92 adc0gtl 0xc3 0x0 adc0 greater-than compare low 92 adc0h 0xbe 0x0 adc0 high 91 adc0l 0xbd 0x0 adc0 low 91 adc0lth 0xc6 0x0 adc0 less-than compare word high 93 adc0ltl 0xc5 0x0 adc0 less-than compare word low 93 adc0mx 0xbb 0x0 adc0 mux 96 adc0pwr 0xba 0xf adc0 burst mode power-up t ime 89 a dc0tk 0xbb 0xf adc0 tracking control 90 aes0bcfg 0xe9 0x2 aes0 block configuration 203 aes0bin 0xeb 0x2 aes0 block input 205 aes0dcfg 0xea 0x2 aes0 data configuration 204 aes0kin 0xed 0x2 aes0 key input 206 aes0xin 0xec 0x2 aes0 xor input 206 aes0yout 0xf5 0x2 aes y out 207 ckcon 0x8e 0x0 clock control 492 clkmode 0xfd 0xf clock mode 269 clksel 0xa9 0x0 and 0xf clock select 298 cpt0cn 0x9b 0x0 comparator0 control 106 cpt0md 0x9d 0x0 comparator0 mode selection 107 cpt0mx 0x9f 0x0 comparator0 mux selection 113 cpt1cn 0x9a 0x0 comparator1 control 108 cpt1md 0x9c 0x0 comparator1 mode selection 109 cpt1mx 0x9e 0x0 comparator1 mux selection 114 crc0auto 0x96 0xf crc0 automatic control 167 crc0cnt 0x97 0xf crc0 automatic flash sector count 167 crc0cn 0x92 0xf crc0 control 165 crc0dat 0x91 0xf crc0 data 166 crc0flip 0x94 0xf crc0 flip 168 crc0in 0x93 0xf crc0 input 166
rev. 0.3 231 si102x/3x crc1cn 0xbe 0x2 crc1 control 173 crc1in 0xb9 0x2 crc1 in 174 crc1outh 0xbb 0x2 crc1 out high 175 crc1outl 0xba 0x2 crc1 out low 175 crc1polh 0xbd 0x2 crc1 polynomial high 174 crc1poll 0xbc 0x2 crc1 polynomial low 174 dc0cf 0xb2 0x2 dc0 configuration 281 dc0cn 0xb1 0x2 dc0 control 280 dc0md 0xb3 0x2 dc0 mode 282 dc0rdy 0xfd 0x2 dc0 ready 283 deviceid 0xe9 0xf device id 255 dma0busy 0xd5 0x2 dma0 busy 154 dma0en 0xd2 0x2 dma0 enable 151 dma0int 0xd3 0x2 dma0 interrupt 152 dma0mint 0xd4 0x2 dma0 middle interrupt 153 dma0naoh 0xcd 0x2 dma0 address offset high (selected channel) 159 dma0naol 0xcc 0x2 dma0 address offset low (selected channel) 159 dma0nbah 0xcb 0x2 dma0 base address high (selected channel) 158 dma0nbal 0xca 0x2 dma0 base address low (selected channel) 158 dma0ncf 0xc9 0x2 dma0 configuration 157 dma0nmd 0xd6 0x2 dma0 mode (selected channel) 156 dma0nszh 0xcf 0x2 dma0 size high (selected channel) 160 dma0nszl 0xce 0x2 dma0 size low (selected channel) 160 dma0sel 0xd1 0x2 dma0 channel select 155 dph 0x83 all pages data pointer high 121 dpl 0x82 all pages data pointer low 121 eie1 0xe6 all pages extended interrupt enable 1 244 eie2 0xe7 all pages extended interrupt enable 2 246 eip1 0xf6 all pages extended interrupt priority 1 245 eip2 0xf7 all pages extended interrupt priority 2 247 emi0cf 0xab 0x0 emif configuration 134 emi0cn 0xaa 0x0 emif control 133 emi0tc 0xaf 0x0 emif timing control 139 enc0cn 0xc5 0x2 enc0 control 215 table 16.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page
si102x/3x 232 rev. 0.3 enc0h 0xc4 0x2 enc0 high 216 enc0l 0xc2 0x2 enc0 low 216 enc0m 0xc3 0x2 enc0 middle 216 flkey 0xb7 all pages flash lock and key 261 flscl 0xb6 0xf flash scale register 262 flwr 0xe5 0x0 flash write only 262 frbcn 0xb5 0xf flash read buffer control 263 ie 0xa8 all pages interrupt enable 242 ip 0xb8 all pages interrupt priority 243 iref0cf 0xb9 0xf current reference iref0 configuration 111 iref0cn 0xb9 0x0 current reference iref0 configuration 110 it01cf 0xe4 0x0 and 0xf int0/int1 configuration 249 lcd0blink 0x9e 0x2 lcd0 blink mask 353 lcd0bufcf 0xac 0xf lcd0 buffer configuration 357 lcd0bufcn 0x9c 0xf lcd0 buffer control 356 lcd0bufmd 0xb6 0x2 lcd0 buffer mode 357 lcd0cf 0xa5 0x2 lcd0 configuration 355 lcd0chpcf 0xad 0x2 lcd0 charge pump configuration 356 lcd0chpcn 0xb5 0x2 lcd0 charge pump control 355 lcd0chpmd 0xae 0x2 lcd0 charge pump mode 356 lcd0clkdivh 0xaa 0x2 lcd0 clock divider high 352 lcd0clkdivl 0xa9 0x2 lcd0 clock divider low 352 lcd0cn 0x9d 0x2 lcd0 control 344 lcd0cntrst 0x9c 0x2 lcd0 contrast 348 lcd0d0 0x89 0x2 lcd0 data 0 342 lcd0d1 0x8a 0x2 lcd0 data 1 342 lcd0d2 0x8b 0x2 lcd0 data 2 342 lcd0d3 0x8c 0x2 lcd0 data 3 342 lcd0d4 0x8d 0x2 lcd0 data 4 342 lcd0d5 0x8e 0x2 lcd0 data 5 342 lcd0d6 0x91 0x2 lcd0 data 6 342 lcd0d7 0x92 0x2 lcd0 data 7 342 lcd0d8 0x93 0x2 lcd0 data 8 342 table 16.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page
rev. 0.3 233 si102x/3x lcd0d9 0x94 0x2 lcd0 data 9 342 lcd0da 0x95 0x2 lcd0 data a 342 lcd0db 0x96 0x2 lcd0 data b 342 lcd0dc 0x97 0x2 lcd0 data c 342 lcd0dd 0x99 0x2 lcd0 data d 342 lcd0de 0x9a 0x2 lcd0 data e 342 lcd0df 0x9b 0x2 lcd0 data f 342 lcd0mscf 0xac 0x2 lcd0 master configuration 350 lcd0mscn 0xab 0x2 lcd0 master control 349 lcd0pwr 0xa4 0x2 lcd0 power 350 lcd0togr 0x9f 0x2 lcd0 toggle rate 354 lcd0vbmcf 0xaf 0x2 lcd0 vbat monitor configuration 357 lcd0vbmcn 0xa6 0x2 lcd0 vbat monitor control 351 oscicl 0xb3 0xf internal oscillator calibration 300 oscicn 0xb2 0x0 internal oscillator control 299 oscxcn 0xb1 0x0 external oscillator control 301 p0drv 0xa4 0xf port 0 drive strength 373 p0mask 0xc7 0x0 port 0 mask 368 p0mat 0xd7 0x0 port 0 match 368 p0mdin 0xf1 0x0 port 0 input mode configuration 372 p0mdout 0xa4 0x0 port 0 output mode configuration 372 p0skip 0xd4 0x0 port 0 skip 371 p0 0x80 all pages port 0 latch 371 p1drv 0xa5 0xf port 1 drive strength 375 p1mask 0xbf 0x0 port 1 mask 369 p1mat 0xcf 0x0 port 1 match 369 p1mdin 0xf2 0x0 port 1 input mode configuration 374 p1mdout 0xa5 0x0 port 1 output mode configuration 375 p1skip 0xd5 0x0 port 1 skip 374 p1 0x90 all pages port 1 latch 373 p2drv 0xa6 0xf port 2 drive strength 378 p2mdin 0xf3 0x0 port 2 input mode configuration 377 p2mdout 0xa6 0x0 port 2 output mode configuration 377 p2skip 0xd6 0x0 port 2 skip 376 table 16.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page
si102x/3x 234 rev. 0.3 p2 0xa0 all pages port 2 latch 376 p3drv 0xa1 0xf port 3 drive strength 380 p3mdin 0xf1 0xf port 3 input mode configuration 379 p3mdout 0xb1 0xf p3 mode out 379 p3 0xb0 all pages port 3 378 p4drv 0xa2 0xf port 4 drive strength 382 p4mdin 0xf2 0xf port 4 input mode configuration 381 p4mdout 0xf9 0xf p4 mode out 381 p4 0xd9 0xf port 4 latch 380 p5drv 0xa3 0xf port 5 drive strength 384 p5mdin 0xf3 0xf port 5 input mode configuration 383 p5mdout 0xfa 0xf p5 mode out 383 p5 0xda 0xf port 5 latch 382 p6drv 0xaa 0xf port 6 drive strength 386 p6mdin 0xf4 0xf port 6 input mode configuration 385 p6mdout 0xfb 0xf p6 mode out 385 p6 0xdb 0xf port 6 latch 384 p7drv 0xab 0xf port 7 drive strength 387 p7mdout 0xfc 0xf p7 mode out 387 p7 0xdc 0xf port 7 latch 386 pc0cmp0h 0xe3 0x2 pc0 comparator 0 high 336 pc0cmp0l 0xe1 0x2 pc0 comparator 0 low 336 pc0cmp0m 0xe2 0x2 pc0 comparator 0 middle 336 pc0cmp1h 0xf3 0x2 pc0 comparator 1 high 337 pc0cmp1l 0xf1 0x2 pc0 comparator 1 low 337 pc0cmp1m 0xf2 0x2 pc0 comparator 1 middle 337 pc0ctr0h 0xdc 0x2 pc0 counter 0 high 334 pc0ctr0l 0xda 0x2 pc0 counter 0 low 334 pc0ctr0m 0xd8 0x2 pc0 counter 0 middle 334 pc0ctr1h 0xdf 0x2 pc0 counter 1 high 335 pc0ctr1l 0xdd 0x2 pc0 counter 1 low 335 pc0dch 0xfa 0x2 pc0 debounce configuration high 332 pc0dcl 0xf9 0x2 pc0 debounce configuration low 333 pc0hist 0xf4 0x2 pc0 history 338 table 16.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page
rev. 0.3 235 si102x/3x pc0int0 0xfb 0x2 pc0 interrupt 0 339 pc0int1 0xfc 0x2 pc0 interrupt 1 340 pc0md 0xd9 0x2 pc0 mode 328 pc0pcf 0xd7 0x2 pc0 pull-up configuration 329 pc0stat 0xc1 0x2 pc0 status 331 pc0th 0xe4 0x2 pc0 threshold 330 pca0cn 0xd8 all pages pca0 control 527 pca0cph0 0xfc 0x0 pca0 capture 0 high 532 pca0cph1 0xea 0x0 pca0 capture 1 high 532 pca0cph2 0xec 0x0 pca0 capture 2 high 532 pca0cph3 0xee 0x0 pca0 capture 3 high 532 pca0cph4 0xfe 0x0 pca0 capture 4 high 532 pca0cph5 0xd3 0x0 pca0 capture 5 high 532 pca0cpl0 0xfb 0x0 pca0 capture 0 low 532 pca0cpl1 0xe9 0x0 pca0 capture 1 low 532 pca0cpl2 0xeb 0x0 pca0 capture 2 low 532 pca0cpl3 0xed 0x0 pca0 capture 3 low 532 pca0cpl4 0xfd 0x0 pca0 capture 4 low 532 pca0cpl5 0xd2 0x0 pca0 capture 5 low 532 pca0cpm0 0xda 0x0 pca0 module 0 mode register 530 pca0cpm1 0xdb 0x0 pca0 module 1 mode register 530 pca0cpm2 0xdc 0x0 pca0 module 2 mode register 530 pca0cpm3 0xdd 0x0 pca0 module 3 mode register 530 pca0cpm4 0xde 0x0 pca0 module 4 mode register 530 pca0cpm5 0xce 0x0 pca0 module 5 mode register 530 pca0h 0x0 pca0 counter high 531 pca0l 0xf9 0x0 pca0 counter low 531 pca0md 0xd9 0x0 pca0 mode 528 pca0pwm 0xdf 0x0 pca0 pwm configuration 529 pclkact 0xf5 0xf peripheral clock enable active mode 267 pclken 0xfe 0xf peripheral clock enables (lp idle) 268 pcon 0x87 all pages power control 275 pmu0cf 0xb5 0x0 pmu0 configuration 0 272 pmu0fl 0xb6 0x0 pmu0 flag 273 table 16.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page
si102x/3x 236 rev. 0.3 pmu0md 0xb3 0x0 internal oscillator calibration 274 psbank 0x84 all pages flash page switch bank sfr 127 psctl 0x8f all pages program store r/w control 260 psw 0xd0 all pages program status word 123 ref0cn 0xd1 0x0 voltage reference control 102 reg0cn 0xc9 0x0 voltage regulator (reg0) control 284 revid 0xea 0xf revision id 256 rstsrc 0xef 0x0 reset source configuration/status 292 rtc0adr 0xac 0x0 rtc0 address 305 rtc0dat 0xad 0x0 rtc0 data 306 rtc0key 0xae 0x0 rtc0 key 305 sbuf0 0x99 0x0 uart0 data buffer 415 scon0 0x98 all pages uart0 control 414 sfrlast 0x86 all pages sfr page stack last 227 sfrnext 0x85 all pages sfr page stack next 226 sfrpage 0xa7 all pages sfr page 225 sfrpgcn 0x8e 0xf sfr page control 224 smb0adm 0xf5 0x0 smbus slave address mask 399 smb0adr 0xf4 0x0 smbus slave address 398 smb0cf 0xc1 0x0 smbus0 configuration 394 smb0cn 0xc0 all pages smbus0 control 396 smb0dat 0xc2 0x0 smbus0 data 400 spi0cfg 0xa1 0x0 spi0 configuration 425 spi0ckr 0xa2 0x0 spi0 clock rate control 427 spi0cn 0xf8 0x0 spi0 control 426 spi0dat 0xa3 0x0 spi0 data 427 spi1cfg 0xa1 0x2 spi1 configuration 438 spi1ckr 0xa2 0x2 spi1 clock rate control 440 spi1cn 0xf8 0x2 spi1 control 439 spi1dat 0xa3 0x2 spi1 data 440 sp 0x81 all pages stack pointer 122 tcon 0x88 all pages timer/counter control 497 th0 0x8c 0x0 timer/counter 0 high 500 th1 0x8d 0x0 timer/counter 1 high 500 table 16.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page
rev. 0.3 237 si102x/3x tl0 0x8a 0x0 timer/counter 0 low 499 tl1 0x8b 0x0 timer/counter 1 low 499 tmod 0x89 0x0 timer/counter mode 498 tmr2cn 0xc8 all pages timer/counter 2 control 504 tmr2h 0xcd 0x0 timer/counter 2 high 506 tmr2l 0xcc 0x0 timer/counter 2 low 506 tmr2rlh 0xcb 0x0 timer/counter 2 reload high 505 tmr2rll 0xca 0x0 timer/counter 2 reload low 505 tmr3cn 0x91 0x0 timer/counter 3 control 510 tmr3h 0x95 0x0 timer/counter 3 high 512 tmr3l 0x94 0x0 timer/counter 3 low 512 tmr3rlh 0x93 0x0 timer/counter 3 reload high 511 tmr3rll 0x92 0x0 timer/counter 3 reload low 511 toffh 0xbb 0xf temperature offset high 99 toffl 0xbd 0xf temperature offset low 99 vdm0cn 0xff all pages vdd monitor control 289 xbr0 0xe1 0x0 and 0xf port i/o crossbar control 0 365 xbr1 0xe2 0x0 and 0xf port i/o crossbar control 1 366 xbr2 0xe3 0x0 and 0xf port i/o crossbar control 2 367 table 16.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page
si102x/3x 238 rev. 0.3 17. interrupt handler the si102x/3x microcontroller family includes an extended interrupt syst em supporting mu ltiple interrupt sources and two priority levels. the allocation of interrupt sources between on-chip peripherals and exter - nal input pins varies according to the specific version of the device. refer to ta b l e 17.1, ?interrupt sum - mary,? on page 240 for a detailed listing of all inter r upt sources supported by the device. refer to the data sheet section associated with a particular on-chip peri p her al for information regarding valid interrupt condi - tions for the peripheral and the behavior of its interrupt-pending flag(s). each interrupt source has one or more associated interrupt-pending flag(s) located in an sfr or an indi - rect register. when a peripheral or exter n al source meets a valid interrupt condition, the associated inter - rupt-pending flag is set to logic 1. if both global interrupts and the specific interrupt source is enabled, a cpu in terrupt request is generated when the interrupt-pending flag is set. as soon as execution of the curren t instruction is complete, the cpu generates an lcall to a predeter - mined address to begin exec ution of a n interrupt service routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal . (the interrupt-pending flag is set to logic 1 regard - less of the interrupt's enable/disable state.) some interrupt-pending flags are automatically cleared by hardware when the cpu vectors to the isr. howeve r , most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of th e next instruction. 17.1. enabling interrupt sources each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in the interrupt enable and extended interrupt enable sfrs. however, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are recog - nized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt- enable settings. note that interrupt s which occur wh en the ea bit is set to logic 0 will be held in a pending state, and will not be serviced until the ea bit is set back to logic 1. 17.2. mcu interrupt sources and vectors the cpu services interrupts by generating an lca ll to a predetermined address (the interrupt vector address) to begin execution of an interrupt service routine (isr). the interrupt vector addresses associ - ated with each interrupt source are listed in ta b l e 17.1 on page 240 . software should ensure that the inter - rupt vector for each enabled inter r upt source contains a valid interrupt service routine. software can simulate an interrupt by setting any interrupt-pending flag to logic 1. if interrupts are enabled for the flag, an interrupt request will be gene rated and the cpu will v ector to the isr address associated with the interrupt-pending flag.
rev. 0.3 239 si102x/3x 17.3. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior - ity interrupt service routine can be pree mpted b y a high priority interrupt. a high priority interrupt cannot be preempted. if a high priori ty interrupt preempts a low priority interrupt, the low priority interrupt will finish execution after the high priority interrupt completes. each interrupt has an associated interrupt priority bit in in the interrupt priority and extended interrupt priority registers used to configure its priority level. low pri - ority is the default. if two interrupts are recognized simultaneously, the interrup t with th e high er priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate. see ta b l e 17.1 on page 240 to determine the fixed priority order used to a r bitrate between simultaneously recognized inter - rupts. 17.4. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 7 system clock cycles: 1 clock cycle to detect the interrupt, 1 clock cycle to execute a single instr uction, and 5 clock cycles to complete the lcall to the isr. if an inter r upt is pending when a reti is executed, a sin - gle instruction is executed before an lcall is made to se rvice the pending interrupt. therefore, the maxi - mum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is o f greater priority) occurs when the cpu is perfor ming an reti instruction followed by a div as the next instruction. in this case , the response time is 19 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 5 clock cycles to ex ec ute the lcall to the isr. if the cpu is executing an isr for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction.
si102x/3x 240 rev. 0.3 table 17.1. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 to p none n/a n/a always enabled always highest external interrupt 0 ( int0 ) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 ( int1 ) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6 ) pspi0 (ip. 6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie 1. 0) psmb0 (eip 1.0) smartclock alarm 0x0043 8 alrm (rtc0cn.2)* n n eartc0 (eie 1. 1) partc0 (eip 1.1) adc0 window compara - tor 0x004b 9 ad0wint (ad c 0cn.3) y n ewadc0 (eie1. 2) pwadc0 (eip 1.2) adc0 end of conversion 0x0053 10 ad0int (adc0sta.5) y n eadc0 (eie 1. 3) padc0 (eip 1.3) programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) y n epca0 (eie 1. 4) ppca0 (eip 1.4) comparator0 0x0063 12 cp0fif (cpt0cn.4) cp0rif (cpt0cn.5) n n ecp0 (eie1. 5) pcp0 (eip 1.5) comparator1 0x006b 13 cp1fif (cpt1cn.4) cp1rif (cpt1cn.5) n n ecp1 (eie 1. 6) pcp1 (eip 1.6) timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) n n et3 (eie1.7) pt3 (eip 1.7) vdd/vbat supply monitor ea rly warning 0x007b 15 vddok (vdm0cn.5) 1 vbok (vdm0cn.2) 1 ewarn (eie2.0) pwarn (eip 2.0) port match 0x0083 16 none emat (eie2. 1) pmat (eip 2.1)
rev. 0.3 241 si102x/3x 17.5. interrupt re gister descriptions the sfrs used to enable the interrupt sources and se t their priority level ar e described in the following register descriptions. refer to the data sheet sectio n associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). smartclock oscillator fail 0x 008b 17 oscfail (rtc 0cn.5) 2 n n ertc0f (eie2. 2) pfrtc0f (eip 2.2) spi1 0x0093 18 spif (spi1cn.7) wcol (spi1cn.6) modf (spi1cn.5) rxovrn (spi1cn.4) n n espi1 (eie 2. 3) pspi1 (eip 2.3) pulse counter 0x009b 19 c0zf (pc0cn.4) c1zf (pc0cn.6) n n epc0 (eie 2. 4) ppc0 (eip 2.4) dma0 0x00a3 20 dmaint0...7 dmamint0...7 n n edma0 (eie2. 5) pdma0 (eip 2.5) encoder0 0x00ab 21 encerr(enccn.6) n n eenc0 (eie2. 6) penc0 (eip 2.6) aes 0x00b3 22 aesdone (aesbcf.5) n n eaes0 (eie 2. 7) paes0 (eip 2.7) notes: 1. indicates a read-only interrupt pending flag. the inte rrupt enable may be used to prevent software from vectorin g to the associated interrupt service routine. 2. indi cates a register located in an indirect memory space. table 17.1. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control
si102x/3x 242 rev. 0.3 sfr page = all pages; sfr ad dress = 0xa8; bit-addressable sfr definition 17.1. ie: interrupt enable bit 7 6 5 4 3 2 1 0 name ea espi0 et2 es0 et1 ex1 et0 ex0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ea enable all interrupts. globally enables/disables all interrupts. it ov erri des individual interrupt mask settings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. 6 espi0 enable serial peripheral interface (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. 5 et2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. 4 es0 enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. 3 et1 enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. 2 ex1 enable external interrupt 1. this bit sets the masking of ex ternal interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the int1 input. 1 et0 enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. 0 ex0 enable external interrupt 0. this bit sets the masking of ex ternal interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input.
rev. 0.3 243 si102x/3x sfr page = all pages; sfr ad dress = 0xb8; bit-addressable sfr definition 17.2. ip: interrupt priority bit 7 6 5 4 3 2 1 0 name pspi0 pt2 ps0 pt1 px1 pt0 px0 type r r/w r/w r/w r/w r/w r/w r/w reset 1 0 0 0 0 0 0 0 bit name function 7 unused read = 1b, write = don't care. 6 pspi0 serial peripheral interface (spi 0) interrupt priori ty control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. 5 pt2 timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority lev el. 1: timer 2 interrupt set to high priority level. 4 ps0 uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupt set to high priority level. 3 pt1 timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority lev el. 1: timer 1 interrupt set to high priority level. 2 px1 external interrupt 1 priority control. this bit sets the priority of the external interrupt 1 interrupt. 0: external interrupt 1 se t to low priority level. 1: external interrupt 1 se t to high priority level. 1 pt 0 timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority lev el. 1: timer 0 interrupt set to high priority level. 0 px0 external interrupt 0 priority control. this bit sets the priority of the external interrupt 0 interrupt. 0: external interrupt 0 se t to low priority level. 1: external interrupt 0 se t to high priority level.
si102x/3x 244 rev. 0.3 sfr page = all pages; sfr address = 0xe6 sfr definition 17.3. eie1: extended interrupt enable 1 bit 7 6 5 4 3 2 1 0 name et3 ecp1 ecp0 epca0 eadc0 ewadc0 ertc0a esmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 et3 enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. 6 ecp1 enable comparator1 (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by the cp1rif or cp1fif flags. 5 ecp0 enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. 4 epca0 enable programmable counte r ar ray ( pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 in terrupts. 1: enable interrupt requests generated by pca0. 3 eadc0 enable adc0 conversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversi on co mplete interrupt. 1: enable interrupt requests generated by the ad0int flag. 2 ewadc0 enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comp arison interrupt. 1: enable interrupt requests generated by adc0 wind ow compare flag (ad0wint). 1 ertc0a enable smartclock alarm interrupts. this bit sets the masking of the smartclock alarm interrupt. 0: disable smartclo ck ala rm interrupts. 1: enable interrupt requests generated by a smartclock alarm. 0 esmb0 enable smbus (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0.
rev. 0.3 245 si102x/3x sfr page = all pages; sfr address = 0xf6 sfr definition 17.4. eip1: extended interrupt priority 1 bit 7 6 5 4 3 2 1 0 name pt3 pcp1 pcp0 ppca0 padc0 pwadc0 prtc0a psmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 pt3 timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts set to low priority level. 1: timer 3 interrupts set to high priority level. 6 pcp1 comparator1 (cp1) interru pt priority control. this bit sets the priority of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. 5 pcp0 comparator0 (cp0) interru pt priority control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. 4 ppca0 programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. 3 padc0 adc0 conversion complete interrupt priority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt s e t to low priority level. 1: adc0 conversion complete interrupt set to high priority level. 2 pwadc0 adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt se t to low priority level. 1: adc0 window interrupt set to high priority level. 1 prtc0a smartclock alarm interr upt prior ity control. this bit sets the priority of the smartclock alarm interrupt. 0: smartclock alarm interrup t s e t to low priority level. 1: smartclock alarm interrupt s e t to high priority level. 0 psmb0 smbus (smb0) interrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level.
si102x/3x 246 rev. 0.3 sfr page = all pages;sfr address = 0xe7 sfr definition 17.5. eie2: extended interrupt enable 2 bit 7 6 5 4 3 2 1 0 name eaes0 eenc0 edma0 epc0 espi1 ertc0f emat ewarn type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 eaes0 enable aes0 interrupt. this bit sets the masking of aes0 interrupts. 0: disable all aes0 interrupts. 1: enable interrupt re quest s generat ed by aes0. 6 eenc0 enable encoder (enc0) interrupt. this bit sets the masking of enc0 interrupts. 0: disable all e nc0 interrupt s . 1: enable interrupt requests generated by enc0. 5 edma0 enable dma0 interrupt. this bit sets the masking of dma0 interrupts. 0: disable all dm a0 in terrupts. 1: enable interrupt requests generated by dma0. 4 epc0 enable pulse counter (pc0) interrupt. this bit sets the masking of pc0 interrupts. 0: disable all pc0 interrupts. 1: enable interrupt requests generated by pc0. 3 espi1 enable serial peripheral in te rface (spi1) interrupt. this bit sets the masking of the spi1 interrupts. 0: disable all spi1 interrupts. 1: enable interrupt requests generated by spi1. 2 ertc0f enable smartclock oscillator fail interrupt. this bit sets the masking of the smartclock alarm interrupt. 0: disable smartclock alarm interrupt s . 1: enable interrupt requests generated by smartclock alarm. 1 emat enable port match interrupts. this bit sets the masking of the port match event interrupt. 0: disable all port match interrupts. 1: enable interrupt requests generated by a port match. 0 ewarn enable vdd/dc+ supply monitor early warning interrupt. this bit sets the masking of the vdd/dc+ su pp ly monitor early warning interrupt. 0: disable the vdd/dc+ supply mo n i tor early warning interrupt. 1: enable interrupt requests generated by vdd/dc+ supply monitor.
rev. 0.3 247 si102x/3x sfr page = all pages; sfr address = 0xf7 sfr definition 17.6. eip2: extended interrupt priority 2 bit 7 6 5 4 3 2 1 0 name paes0 penc0 pdma0 ppc0 pspi1 prtc0f pmat pwarn type rrrrr/wr/wr/wr/w reset 0 0 0 0 0 0 0 0 bit name function 7 paes0 aes0 interrupt priority control. this bit sets the priori ty of the aes0 interrupt. 0: aes0 interrupt set to low priority level. 1: aes0 interrupt set to high priority level. 6 penc0 encoder (enc0) interrupt priority control. this bit sets the priority of the enc0 interrupt. 0 : enc0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. 5 pdma0 dma0 interrupt priority control. this bit sets the priority of the dma0 interrupt. 0: dma0 interr upt set to low priority level. 1: dma0 interrup t set to high priority level. 4 ppc0 pulse counter (pc0) inte rrupt priority control. this bit sets the priority of the pc0 interrupt. 0: pc0 interrupt set to l o w priority level. 1: pc0 interrupt set to high priority lev e l. 3 pspi0 serial peripheral interface (spi 1) interrupt pr iority control. this bit sets the priority of the spi0 interrupt. 0: spi1 interrupt set to low priority level. 1: spi1 interrupt set to high priority level. 2 prtc0f smartclock oscillator fail in terrupt priority contro l. this bit sets the priority of the smar tclock alarm interrupt. 0: smartclock alarm interrupt set to low priority level. 1: smartclock alarm interrupt set to high priority level. 1 pmat port match interrupt priority control. this bit sets the priority of the port match ev ent interrupt. 0: port match interrupt se t to low priority level. 1 : port match interrupt se t to high priorit y level. 0 pwarn vdd/dc+ supply monitor early warn ing interrupt priority control. th is bit sets the priority of the vdd/dc+ supply monitor early warning interrupt. 0: vdd/dc+ supply monitor early warnin g interrupt set to low priority level. 1: vdd/dc+ supply monitor early warning in t errupt set to hi gh priority level.
si102x/3x 248 rev. 0.3 17.6. external interrupts int0 and int1 the int0 and int1 external interrupt sources are configurable as active high or low, edge or level sensi - tive. the in0pl ( int0 polarity) and in1pl ( int1 polarity) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon ( section ?33.1. timer 0 and timer 1? on page 493 ) select level or edge sensitive. the table below lis t s the possible configurations. int0 and int1 are assigned to port pins as defined in the it01cf register (see sfr definition 17.7 ). note that int0 and int0 port pin assignments are independent of any crossbar assignments. int0 and int1 will monitor their assigned port pins wit hout disturbing the peripheral that was assigned the port pin via the crossbar. to assign a port pin only to int0 and/or int1 , configure the crossbar to skip the selected pin(s). this is accomplished by setting the associated bit in register xbr0 (see section ?27.3. priority crossbar decoder? on page 362 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the in te rrupt-pending flags for the int0 and int1 external inter - rupts, respectively. if an int0 or int1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the cpu ve ctors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in1pl); th e flag remains logic 0 while the input is inactive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrupt request befor e execution of the isr completes or another interrup t request will be generated. it0 in0pl int0 interrupt it1 in1pl int1 interrupt 10 active low, edge sensitive 10 active low, edge sensitive 11 active high, edge sensitive 11 active high, edge sensitive 00 active low, level sensitive 00 active low, level sensitive 01 active high, level sensitive 01 active high, level sensitive
rev. 0.3 249 si102x/3x sfr page = 0x0 and 0xf; sfr address = 0xe4 sfr definition 17.7. it01cf: int0 / int1 configuration bit 7 6 5 4 3 2 1 0 name in1pl in1sl[2:0] in0pl in0sl[2:0] type r/w r/w r/w r/w reset 0 0 0 0 0 0 0 1 bit name function 7 in1pl int1 polarity. 0: int1 input is active low. 1: int1 input is active high. 6:4 in1sl[2:0] int1 port pin se lection bits. these bits select which port pin is assigned to int1 . note that this pin assignment is independent of the crossbar; int1 will monitor the assigned port pin without disturb - ing the peripheral that has been assigned t he po rt pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p1.6 111: select p1.7 3 in0pl int0 polarity. 0: int0 input is active low. 1: int0 input is active high. 2:0 in0sl[2:0] int0 port pin se lection bits. these bits select which port pin is assigned to int0 . note that this pin assignment is independent of the crossbar; int0 will monitor the assigned port pin without disturb - ing the peripheral that has been assigned t he po rt pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p1.6 111: select p1.7
si102x/3x 250 rev. 0.3 18. flash memory on-chip, re-programmable flash memory is included for program code and non-volatile data storage. the flash memory can be programmed in-system, a single by te at a time, through the c2 interface or by soft - ware using the movx write instru c t ion. once cleared to logic 0, a flash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0 x ff) before being reprogrammed. the write and erase operations are automatically timed by hardware for proper execut ion; data polling to determine the end of the write/erase operations is not required. code execution is st alled during flash write/erase opera - tions. refer to table 4.8 for complete flash memory electrical characteristics. 18.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon laboratories or a th ird party vendor. this is the only means for programming a non-initialized device. for det ails on the c2 commands to program flash memory, see section ?35. c2 interface? on page 533 . the flash memory can be programmed by software using the movx write instruction with the address and data byte to be programmed provided as normal operands. before programming flash memory using movx, flash programming operations must be enabled by : (1) setting the pswe program store write enable bit (psctl.0) to logic 1 (this directs the movx writes to target flash memory); and (2) writing the flash key co des in sequence to the flash lock register (flkey). the pswe bit remains set until cleared by software. for detailed guidelines on programming flash from firmware, please see section ?18.5. flash write and erase guidelines? on page 256 . to ensure the integrity of the flas h content s, the on-chip vdd monitor must be enabled and enabled as a reset source in any system that includes code that writes and/or erases flash memory from software. fur - thermore, there should be no delay between enabling the v dd monitor and enabling the v dd monitor as a reset source. any attempt to write or erase flash memory while the v dd monitor is disabled, or not enabled as a reset source, will cause a flash error device reset. 18.1.1. flash lock and key functions flash writes and erases by user so f t ware are protected with a lock and key function. the flash lock and key register (flkey) must be writ ten with the correct key codes, in seque nce, before fl ash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and erases will also be disabled if a flash write or erase is attempted before the key codes hav e been written properly. the flash lock resets after each write or erase; the key code s must be written again before a fo llowing flash operation can be per - formed. the flkey regist er is det ailed in sfr definition 18.4 . 1 8.1.2. flash erase procedure the flash memory is organized in 1024-byte pages. the er ase op er ation applies to an entire page (setting all bytes in the page to 0xff). to erase an entire 1024-byte page, perform the following steps: 1. save current interrupt state and disable interrupts. 2. set the psee bit (register p sctl). 3. set the pswe bit (register psctl). 4. if writing to an addre ss in banks 1, 2, or 3, set the co bank[1:0] bits (register psbank) for the appropriate bank. 5. write the first key code to flkey: 0xa5. 6. write the second ke y code to flkey: 0xf1. 7. using the movx instruction, write a data byte to any location within the 1024-byte page to be erased. 8. clear the pswe and psee bits.
rev. 0.3 251 si102x/3x 9. restore previous interrupt state. steps 4?7 must be repeated for each 1024-byte page to be erased. notes: 1. flash security settings may prevent erasure of some flash p ages, such as the reserved area and the page containing the lock bytes. for a summary of flash security settings and restrictions affecting flash erase operations, please see section ?18.3. security options? on page 253 . 2. 8-bi t movx instructions cannot be used to erase or wr i te to flash memory at addresses higher than 0x00ff. 18.1.3. flash write procedure a write to flash memory can clear bits to logic 0 but cann ot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed should be erased before a new value is written. the recommended procedure for writing a si ngle byte in flash is as follows: 1. save current interrupt state and disable interrupts. 2. set the psw e bit (register psctl). 3. clear the psee bit (register psctl). 4. if writing to an addre ss in banks 1, 2, or 3, set the co bank[1:0] bits (register psbank) for the appropriate bank. 5. ensure that the flash byte has been erased (has a value of 0xff). 6. write the first key code to flkey: 0xa5. 7. write the second ke y code to flkey: 0xf1. 8. using the movx instruction, wr ite a single data byte to the desired location within the 1024-byte sector. 9. clear the pswe bit. 10. restore previous interrupt state. steps 2?8 must be repeated for each byte to be written. notes: 1. flash security settings may prevent writes to some areas o f flash, such as the reserved area. for a summary of flash security settings and restrictions affecting flash write operations, please see section ?18.3. security options? on page 253 . 2. 8-bi t movx instructions cannot be used to erase or wr i te to flash memory at addresses higher than 0x00ff.
si102x/3x 252 rev. 0.3 18.1.4. flash write optimization the flash write procedure includes a block write option to optimize the time to perform consecutive byte writes. when block write is enabled by setting the chblkw bit (flrbcn. 0), writes to flash will occur in blocks of 4 bytes and require the same amount of time as a single byte write. th is is performed by caching the bytes whose address end in 00b, 01b, and 10b that is written to flash and then committing all four bytes to flash when the byte with address 11b is written. w hen block writes are enabled, if the write to the byte with address 11b does not occur, the other three data bytes written is not committed to flash. a write to flash memory can clear bits to logic 0 but ca nn ot set them; only an erase operation can set bits to logic 1 in flash. the flash block to be programmed should be erased before a new value is writ - ten. the recommended procedure for writing a 4- by te flash block is as follows: 1. save current interrupt state and disable interrupts. 2 . set the chblkw bit (register flrbcn). 3. set the pswe bit (register psctl). 4. clear the psee bit (register psctl). 5. if writing to an addre ss in banks 1, 2, or 3, set the co bank[1:0] bits (register psbank) for the appropriate bank 6. write the first key code to flkey: 0xa5. 7. write the second ke y code to flkey: 0xf1. 8. using the movx instruct ion, write the first data byte to the desired location within the 1024-byte sector whose address ends in 00b. 9. write the first key code to flkey: 0xa5. 10. write the second key code to flkey: 0xf1. 11. using the movx instruction, write the second data byte to the next higher flash address ending in 01b. 12. write the first key code to flkey: 0xa5. 13. write the second key code to flkey: 0xf1. 14. using the movx instruction, write the third data byte to the next higher flash address ending in 10b. 15. write the first key code to flkey: 0xa5. 16. write the second key code to flkey: 0xf1. 17. using the movx instruction, write the final data byte to the next higher flash address ending in 11b. 18. clear the pswe bit. 19. clear the chblkw bit. 20. restore previous interrupt state. steps 5?17 must be repeated for each flash block to be written. notes: 1. flash security settings may prevent writes to some areas o f flash, such as the reserved area. for a summary of flash security settings and restrictions affecting flash write operations, please see section ?18.3. security options? on page 253 . 2. 8-bi t movx instructions cannot be used to erase or wr i te to flash memory at addresses higher than 0x00ff.
rev. 0.3 253 si102x/3x 18.2. non-volati le data storage the flash memory can be used for non-volatile data storage as well as progra m code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read using the movc instructi on. note: movx read instructions always target xram. 18.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft - ware as well as to prevent the viewing of proprietary program code and constants. the program store w r ite enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to 1 before software can modify the flash memory; both pswe and psee must be set to 1 before soft - ware can erase flash memory. additional security fe atur es pr event proprietary program code and data con - stants from being read or altered across the c2 interface. a security lock byte located at the last byte of flash user space offers protection of the flash program memor y from access (reads, writes, or erases) by unpro tected code or the c2 interface. the flash security mechanism allows the user to lock n 1024-byte flash pages, starting at page 0 (addresses 0x0000 to 0 x 03ff), where n is the 1s complement number repr esented by the security lock byte. the page con - taining the flash security lock byte is unlocked when no ot her flash pages are locked (all bits of the lock byte are 1) and locked when any other flash pages are locked (any bit of the lock byte is 0). see example in figure 18.1 figure 18.1. flash security example security lock byte: 11111101b ones complement: 00000010b flash pages locked: 3 (first two flash pages + lock byte page) lock byte page locked flash pages access limit set according to the flash security lock byte lock byte reserved area unlocked flash pages locked when any other flash pages are locked
si102x/3x 254 rev. 0.3 the level of flash security depends on the flash ac cess method. the three flash access methods that can be restricted are reads, writes, and erases from the c2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. ta b l e 18.1 summarizes the flash security features of the si102x/3x devices. table 18.1. flash security summary action c2 debug interface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages ( e xcept page with lock byte) permitted permitted permitted read, write or erase locked pages ( e xcept page with lock byte) not permitted flash error reset permitted read or write page containing lock byte ( i f no pages are locked) permitted permitted permitted r e a d o r wr i t e p a g e c o n t a i n i n g l o c k b y t e (if an y p age is locked) not permitted flash error reset permitted read contents of lock byte ( i f no pages are locked) permitted permitted permitted read contents of lock byte (if an y p age is locked) not permitted flash error reset permitted erase page containing lock byte ( i f no pages are locked) permitted flash error reset flash error reset erase page containing lock byte?unlock all p age s (if any page is locked) c2 device erase only flash error reset flash error reset lock additional pages (cha ng e 1s to 0s in the lock byte) not permitted flash error reset flash error reset unlock individual pages (cha ng e 0s to 1s in the lock byte) not permitted flash error reset flash error reset read, write or erase reserved area not permitted flash error reset flash error reset c2 device erase?erases all flash pages in clu d ing the page containing the lock byte. flash error reset?not permitted; ca uses flash error d e vice reset (ferror bit in rstsrc is '1' after reset). - all prohibited operations that are per for med via the c2 interface are ignored (do not cause device reset). - locking any flash page also locks the page containing the lock byte. - once written to, the lock byte cannot be modifi e d except by performing a c2 device erase. - if user code writes to the lock byte, the lock do es not t ake effect until the next device reset.
rev. 0.3 255 si102x/3x 18.4. determining the devi ce part number at run time in many applications, user software may need to determine the mcu part number at run time in order to determine the hardware capabilities. the part number can be determined by reading the value of the deviceid special function register. ? ? the value of the deviceid regi ster ca n be decoded as follows: ? ? 0xe0?si1020 ? 0xe1?si1021 ? 0xe2?si1022 ? 0xe3?si1023 ? 0xe4?si1024 ? 0xe5?si1025 ? 0xe6?si1026 ? 0xe7?si1027 ? 0xe8?si1030 ? 0xe9?si1031 ? 0xea?si1032 ? 0xeb?si1033 ? 0xec?si1034 ? 0xed?si1035 ? 0xee?si1036 ? 0xef?si1037 sfr page = 0xf; sfr address = 0xe9 sfr definition 18.1. deviceid: device identification bit 7 6 5 4 3 2 1 0 name deviceid[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 deviceid[7:0] device identification. these bits contain a value that can be de code d to determine the device part number.
si102x/3x 256 rev. 0.3 sfr page = 0xf; sfr address = 0xea 18.5. flash write and erase guidelines any system which contains routines which write or er ase flash memory from soft ware involves some risk that the write or erase ro utines will execute unin tentionally if the cpu is op erating outside its specified operating range of vdd, system clock frequency, or te mperature. this accidental execution of flash modi - fying code can result in alteration of flash m e mory contents causing a s ystem failure that is only recover - able by re-flashing the code in the device. to help prevent the accidental modi ficatio n of flash by firmware, the vdd monitor must be enabled and enabled as a reset source on si102x/3x device s for the flash to be successfully modified. if either the vdd monitor or the vdd monitor reset source is not enabled, a flash error device reset will be gener - ated when the firmware attempts to modify the flash. the following guidelines are recommended for any system that contains routines which write or erase flash from c o de. 18.5.1. vdd maintenance and the vdd monitor 1. if the system power supply is subject to voltage or current "spikes," add suffic ient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum vdd rise time specification of 1 ms is met. if the system cannot meet this rise time specification, then add an external vdd brownout circuit to the rst pin of the device that holds the device in reset until vdd reaches the minimum device operating voltage and re- asserts rst if vdd drops below the minimum device operating voltage. 3. keep the on-chip vdd monitor enabled and enable the vdd monitor as a reset source as early in code as possible. this should be the first set of instructions executed after the reset vector. for c- based systems, this will involve modifying the star tup code added by the 'c' compiler. see your compiler documentation for more details. make certain that there are no delays in software between enabling the vdd monitor and enabling the vdd monitor as a reset source. code examples showing this can be found in ?an201: writing to flash from firmware," available from the silicon laboratories web site. ? notes: ? on si102x/3x devices, both the vdd monitor and the vdd monitor reset source must be enabled to write o r erase flash without generating a flash error device reset. sfr definition 18.2. revid: revision identification bit 7 6 5 4 3 2 1 0 name revid[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 revid[7:0] revision identification. these bits contain a value that can be decoded to deter mine the s ilicon ? revision. for example, 0x00 for rev a and 0x01 for rev b, etc.
rev. 0.3 257 si102x/3x on si102x/3x devices, both the vdd monitor and the vdd monitor reset source are enabled by hardware after a power-on reset. 4. as an added precaution, explicitly enable the vdd monitor and enable the vdd monitor as a reset source inside the functions that write and erase flash memory. the vdd monitor enable instructions should be placed just after the in struction to set pswe to a 1, but before the flash write or erase operation instruction. 5. make certain that all writes to the rstsrc (reset sources) register use direct assignment operators and explicitly do not use the bit-wise operators (such as and or or). for example, "rstsrc = 0x02" is correct, but "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to the rstsrc regist er explicitly set the porsf bit to a '1'. areas to check are initialization code which enables other reset sources, such as the missing clock detector or comparator, for example, and instructions whic h force a software reset. a global search on "rstsrc" can quickly verify this.
si102x/3x 258 rev. 0.3 18.5.2. pswe maintenance 1. reduce the number of places in code where the pswe bit (b0 in psctl) is set to a 1. there should be exactly one routine in code that sets pswe to a 1 to write flash bytes and one routine in code that sets both pswe and psee both to a 1 to erase flash pages. 2. minimize the number of variable accesses while pswe is set to a 1. handle pointer address updates and loop maintenance outside the "pswe = 1;... pswe = 0;" area. code examples showing this can be found in ?an201: writing to flash from firmware, " available from the s ilicon laboratories web site. 3. disable interrupts prior to setting pswe to a 1 and leave them disabled until after pswe has been reset to 0. any interrupts posted during the flash wr ite or erase operation will be serviced in priority order after the flash operation has been completed and interrupts have been re-enabled by software. 4. make certain that the flash write and erase pointer variables are not located in xram. see your compiler documentation for instructions regarding how to explicitly locate variables in different memory areas. 5. add address bounds checking to the routines th at write or erase flash memory to ensure that a routine called with an illegal ad dress does not resu lt in modification of the flash. 18.5.3. system clock 1. if operating from an external crystal, be advise d that cr yst al performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noisy environment, use the internal oscillator or use an external cmos clock. 2. if operating from the external oscillator, switch to the internal oscillator during flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after the flash operation has completed. ? additional flash recommendations and example code can be found in ?an201: writing to flash from firm - ware," available from the silicon laboratories website.
rev. 0.3 259 si102x/3x 18.6. minimizing flash read current the flash memory in the si102x/3x devi ces is responsible for a substantial portion of the total digital supply current when the device is executing code. below are suggestions to minimi ze flash read current. 1. use idle, low powe r idle, su spend, or sleep modes while wait ing for an interrupt, rather than polling the interrupt flag. idle mode and low power idle mode is particularly well-suited for use in implementing short pauses, since the wake-up time is no more than three system clock cycles. see the power management chapter for details on the various low-power operating modes. 2. the flash memory is organized in 4-byte words starting with a byte with address ending in 00b and ending with a byte with address ending in 11b. a 4-byte pre-fetch buffer is used to read 4 bytes of flash in a single read operation. short loops that st raddle word boundaries or have an instruction byte with address ending in 11b should be avoided when po ssible. if a loop executes in 20 or more clock cycles, any resulting increase in operating current due to mis-alignment will be negligible. 3. to minimize the power consumption of small loops, it is best to loca te them such that the number of 4-byte words to be fetched from flash is minimized. consider a 2-byte, 3-cycle loop (e.g., sjmp $, or while(1);). the flash read current of such a loop will be minimized if both address bytes are contained in the first 3 bytes of a single 4-byte word. such a loop should be manually located at an address ending in 00b or the number of bytes in the loop should be increased (by padding with nop instructions) in order to minimize flash read current.
si102x/3x 260 rev. 0.3 sfr page =all pages; sfr address = 0x8f sfr definition 18.3. psctl: program store r/w control bit 7 6 5 4 3 2 1 0 name psee pswe type r r r r r r r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:2 unused read = 000000b, write = don?t care. 1 psee program store erase enable. setting this bit (in combinat ion with pswe) allows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx instruction will erase the entire page that contains the location addressed by the movx instruction. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. 0 pswe program store write enable. setting this bit allows writing a byte of data to the flash program memory using the movx write instruction . the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabled; the movx write instruction targets flash mem ory .
rev. 0.3 261 si102x/3x sfr page = all pages; sfr address = 0xb7 sfr definition 18.4. flkey: flash lock and key bit 7 6 5 4 3 2 1 0 name flkey[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 flkey[7:0] flash lock and key register. write: this register provides a lock and key function for flash erasures and writes. flash writes and erases ar e enabled by writing 0xa5 follo wed by 0xf1 to the flkey regis - ter. flash writes and erases are automatically disable d after the next write or erase is complete. if any writes to flkey are performed incorrectly, or if a flash write or erase operation is attempted while these operations are disabled, the flash will be perma - nently locked from writes or erasures unt il th e ne xt device reset. if an application never writes to flash, it can intentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1?0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases disabled until the next reset.
si102x/3x 262 rev. 0.3 sfr page = all pages; sfr address = 0xb7 sfr page = 0x0; sfr address = 0xe5 sfr definition 18.5. flscl: flash scale bit 7 6 5 4 3 2 1 0 name bypass type r r/w r r r r r r reset 0 0 0 0 0 0 0 0 bit name function 7 reserved always write to 0. 6 bypass flash read timing one-shot bypass. 0: the one-shot determines the flash read time. 1: the system clock determines the flash read time. leaving the one-shot enabled will provid e the lowest power consumption up to 25 mhz. 5:0 reserved always write to 000000. note: operations which clear the bypass bit do not need to be immediately followed by a benign 3-byte instruction. for code compatibility with c8051f930/ 31/20/21 devices, a benign 3-byte instruction whose third byte is a don't care should follow the clear operation. see the c8051f93x-c8051f92x data sheet for more details. sfr definition 18.6. flwr: flash write only bit 7 6 5 4 3 2 1 0 name flwr[7:0] type w reset 0 0 0 0 0 0 0 0 bit name function 7:0 flwr[7:0] flash write only. all writes to this register have no effect on system operation.
rev. 0.3 263 si102x/3x sfr page = 0xf; sfr address = 0xb5 sfr definition 18.7. frbcn: flash read buffer control bit 7 6 5 4 3 2 1 0 name frbd chblkw type r r r r r r r/w r/w reset 0 0 1 0 0 0 0 0 bit name function 7:2 unused read = 000000b. write = don?t care. 1 frbd flash read buffer disable bit. 0: flash read buffer is enabled and being used. 1: flash read buffer is disabled and bypassed. 0 chblkw block write enable bit. this bit allows block writes to fla s h memory from firmware. 0: each byte of a software flash write is written individually. 1: flash bytes are written in groups of four.
si102x/3x 264 rev. 0.3 19. power management si102x/3x devices support 6 power modes: normal, id le, stop, low power idle, suspend, and sleep. the power management unit (pmu0) allows the device to enter and wake-up from the available power modes. a brief description of each power mode is provided in ta b l e 19.1 . detailed descriptions of each mode can be found in the following sections. in battery powered systems, the system sh ou ld spend as much time as possible in sleep mode in order to preserve battery life. when a task with a fixed number of clock cycles needs to be performed, the device should switch to normal mode, finish the task as quickly as possible, and return to sleep mode. idle mode, low power idle mode, and suspend mode provide a very fast wake-up time; however, the power savings in these modes will not be as much as in sleep mode. stop mode is in cluded for legacy reasons; the system will be more power efficient and easier to wake up wh en idle, low power idle, sus pend, or sleep mode is used. although switching power modes is an integral part of power management, enabling/disabling individual peri pherals as needed will help lower power consumption in all power modes. each analog peripheral can be disabled when not in use or placed in a low power mode. digital peripherals such as timers or serial busses draw little power whenever they are not in us e. digital peripherals draw no power in sleep mode. table 19.1. power modes power mode description wake-up sour ces power savings normal device fully functional n/a excellent mips/mw idle all peripherals fully functional. very easy to wake up. any interrupt. good no code execution stop legacy 8051 low power mode. a reset is required to wake up. any reset. good no code execution precision oscillator disabled low power id le im proved idle mode that uses clock gating to save power . any interrupt very good no code execution selective clock gating suspend similar to stop mode, but very fast wa ke -up time and code resumes execution at the next instruction. smartclock, port match, comp ar ator0, rst pin, pulse counter vbat monitor. very good no code execution all internal oscillators disabled system clock gated sleep ultra low power and flexible wake-up sources . code resumes execution at the next instruction. smartclock, port match, comp ar ator0, rst pin, pulse counter vbat monitor. excellent power supply gated all oscillators except smart - clock disabled
rev. 0.3 265 si102x/3x 19.1. normal mode the mcu is fully functional in normal mode. figure 19.1 shows the on-chip power distribution to various peripherals. there are three supply voltages powering var i ous sections of the chip: vbat, dcout, and the 1.8 v internal core supply (output of vreg0). all analog p eripherals are directly powered from the vbat pin. all digital peripherals and the cip-51 core are powered from the 1.8 v internal core supply (output of vreg0) . the pulse counter, ram, pmu0, and the smartclock are powered from the internal core supply when the device is in normal mode. the input to vreg0 is controlled by software and depends on the set - tings of the power select switch. the power select switch ma y b e configured to power vreg0 from vbat or from the output of the dc0. figure 19.1. si102x/3x power distribution 19.2. idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes executio n. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled i nterrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction immedi ately following the one that se t the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. if enabled, the watchdog timer (wdt) will eventually cause an internal w atchdog reset and thereby termi - nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event ram pmu0 sleep active/idle/ stop/suspend vbatdc vbat 1.8 to 3.6 v analog peripherals adc temp sensor a m u x voltage comparators + - + - vref lcd digital peripherals flash cip-51 core uart spi smbus timers aes vio dc0 buck converter smartclock 1.9 v vio/viorf must be <= vbat gnddc ind vdc vreg0 power select pulse counter viorf 1.8 v
si102x/3x 266 rev. 0.3 of an inadvertent write to the pcon register. if this behavior is not desired, th e wdt may be disabled by software prior to entering th e idle mode if the wdt was initially config ured to allow this operation. this pro - vides the opportunity for additional power savings, allo w ing the sys tem to remain in the idle mode indefi - nitely, waiting for an external stimulus to wake up the system. refer to section ?22.6. pca watchdog timer reset? on page 290 for more information on the use and configuration of the wdt. 19.3. stop mode setting the stop mode select bit (pcon.1) causes the ci p-51 to enter stop mode as soon as the instruc - tion that sets the bit completes execution. in s t op mo de the precision internal oscillator and cpu are stopped; the state of the low power oscillator and the exte rnal oscillator circuit is not affected. each analog peripheral (including th e external oscillator circuit) may be shut down individua lly prior to entering stop mode. stop mode can only be terminated by an internal or external reset. on re set, the cip-51 performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout. stop mode is a legacy 8051 power mode; it will not result in optimal power s a vings. sleep, suspend, or low power idle mode will prov ide more power savings if the mcu needs to be inactive for a long period of time. 19.4. low power idle mode low power idle mode uses clock gating to reduce the supply current when the device is placed in idle mode. this mode is enabled by configuring the cloc k tree gates using the pclken register, setting the lpmen bit in the clkmode register, and placing the devi ce in idle mode. the clock is automatically gated from the cpu upon entry into idle mode when the lp men bit is set. this mode provides substantial power savings over the standard idle mode especially at high system clock frequencies. the clock gating logic may also be used to reduce po we r when executing code. low power active mode is enabled by configuring the pclkact and pclken re gisters, then setting the lpmen bit. the pclkact register provides the ability to over ride the pclken setting to force a cl ock to certain peripherals in low power active mode. if the pclkact regi ster is left at its default val ue, then pclken determines which perpherals will be clocked in this mode. the cpu is always cloc ked in low power active mode. figure 19.2. clock tree distribution smartclock pulse counter pmu0 timer 0, 1, 2 crc0 adc0 pca0 uart0 timer 3 spi0 smbus system clock cpu
rev. 0.3 267 si102x/3x sfr page = 0xf; sfr address = 0xf5 sfr definition 19.1. pclkact: peripheral ac tive clock enable bit 7 6 5 4 3 2 1 0 name pclkact[3:0] type r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:4 unused read = 0b; write = don?t care. 3 pclkact3 clock enable controls for periphe rals in low power acti ve mode. 0: clocks to the smartclock, pulse counte r , and pmu0 revert to the pclken set - ting in low power active mode. 1: enable clocks to the sm artcloc k, pulse counter, and pmu0 in low power active mode. 2 pclkact2 clock enable controls for periphe rals in low power acti ve mode. 0: clocks to timer 0, timer 1, timer 2, and crc0 revert to the pclken setting in low power active mode. 1: enable clocks to timer 0, timer 1, timer 2, and crc0 in low power active mode. 1 pclkact1 clock enable controls for periphe rals in low power acti ve mode. 0: clocks to adc0 and pca0 revert to the pclken setting in low power active mod e. 1: enable clocks to adc0 and pc a0 in low power active mode. 0 pclkact0 cloc k enable controls for periphe rals in low power acti ve mode. 0: clocks to uart0, timer 3, spi0, and th e smbus revert to th e pclken setting in low power active mode. 1: enable clocks to uart0, timer 3, spi0, and the smbus in low power active mode.
si102x/3x 268 rev. 0.3 sfr page = 0xf; sfr address = 0xfe sfr definition 19.2. pclken: peripheral clock enable bit 7 6 5 4 3 2 1 0 name pclken[3:0] type r/w r/w r/w r/w r/w reset bit name function 7:4 unused read = 0b; write = don?t care. 3 pclken3 clock enable controls for periphe rals in low power idle mode. 0: disable clocks to the smartclock, puls e coun ter , and pmu0 in low power idle mode. 1: enable clocks to the smartclock, pulse counte r, and pmu0 in low power idle mode. 2 pclken2 clock enable controls for periphe rals in low power idle mode. 0: disable clocks to timer 0, timer 1, t imer 2, and crc0 in low power idle mode. 1: enable clocks to timer 0, timer 1, timer 2, and crc0 in low power idle mode. 1 pclken1 clock enable controls for periphe rals in low power idle mode. 0: disableclocks to adc0 and pca 0 in low power idle mode. 1: enable clocks to adc0 and pca0 in low power idle mode. 0 pclken0 clock enable controls for periphe rals in low power idle mode. 0: disable clocks to uart0, timer 3, spi0, and the smbus in low power idle mode. 1: enable clocks to uart0, timer 3, spi0, and the smbus in low power idle mode.
rev. 0.3 269 si102x/3x sfr page = 0xf; sfr address = 0xfd; bit-addressable sfr definition 19.3. clkmode: clock mode bit 7 6 5 4 3 2 1 0 name reserved reserved reserved reserved reserved lpmen reserved reserved type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:3 reserved read = 0b; write = must write 00000b. 2 lpmen low power mode enable. setting this bit allows the devic e to enter low power active or idle mode. 1 reserved read = 0b; must write 0b. 0 reserved read = 0b; must write 0b.
si102x/3x 270 rev. 0.3 19.5. suspend mode setting the suspend mode select bit (pmu0cf.6) causes the system clock to be gated off and all internal oscillators disabled. the system cloc k source must be set to the low po wer internal oscillator or the preci - sion oscillator prior to entering susp end mode. all digit al logic (timers, communication pe ripherals, inter - rupts, cpu, etc.) stops func tion ing un til one of the enabled wake-up sources occurs. the following wake-up sources can be configured to wake the device from suspend mode: ? pulse counter count reached event ? vbat monitor (part of lcd logic) ? smartclock oscillator fail ? smartclock alarm ? port match event ? comparator0 rising edge note: upon wake-up from suspend mode, pmu0 requires two system clocks in order to update the pmu0cf wake- up flags. all flags will read back a value of '0' during the first two system clocks following a wake-up from suspend mode. in addition, a noise glitch on rst that is not long enough to reset the device will cause the device to exit suspend. in order for the mcu to respond to the pin reset event, software must not place the device back into suspend mode for a period of 15 s. the pmu0cf register may be checked to determine if the wake- up w a s due to a falling edge on the /rst pin. if the wake-up source is not due to a falling edge on rst , there is no time restriction on how soon software may place the device back into suspend mode. a 4.7 kw pu llu p resistor to vdd is recommend for rst to prevent no ise glitches from waking the device. 19.6. sleep mode setting the sleep mode select bit (pmu0cf.7) turns off the internal 1.8 v regulator (vreg0) and switches the po wer supply of all on-chip ram to the vbat pin (see figure 19.1 ). power to most digital logic on the chip is disconnected; only pmu0, lc d, power select switch, pulse co unter, and the smartclock remain powered. analog peripherals remain powered; howeve r, only the comparators remain functional when the device enters sleep mo de. all other analog peripherals (adc0, iref 0, external oscillator, etc.) should be disabled prior to entering sleep mode. the system cl ock source must be set to the low power internal oscillator or the precision oscillat or prior to entering sleep mode. gpio pins configured as digital outputs will retain thei r output st ate du ring sleep mode. in two-cell mode, they will maintain the same current drive capabilit y in sleep mode as they have in normal mode. gpio pins configured as digital inputs can be used du ring sleep mode as wakeup sources using the port match feature. in two-cell mode, they will maintain the same input leve l specs in sleep mode as they have in normal mode. ?si102x/3x devices support a wakeup request for extern a l devices. upon exit from sleep mode, the wake- up request signal is driven low, allowing other devices in the system to wake up from their low power modes. ram and sfr register contents are preserved in sleep mode as long as the voltage on vbat does not fall below v por . the pc counter and all other volatile state information is preserved allowing the device to resume code execution upon waking up from sleep mode.
rev. 0.3 271 si102x/3x the following wake-up sources can be configured to wake the device from sleep mode: ? pulse counter count reached event ? vbat monitor (part of lcd logic) ? smartclock oscillator fail ? smartclock alarm ? port match event ? comparator0 rising edge the comparator requires a supply voltage of at least 1.8 v to operate properly. on si102x/3x devices, the po r su pply monitor can be disabled to save power by writing 1 to the mondis (pmu0md.5) bit. when the por supply monitor is disabled, all reset sour ces will trigger a full por and will re-enable the por supply monitor. in addition, any falling edge on rst (due to a pin reset or a noise glit ch) will cause the device to exit sleep mode. in order for the mcu to respond to the pin reset event, software must not place the device back into sleep mode for a period of 15 s. the pmu0cf register may be checke d to determine if the wake-up was due to a falling edge on the rst pin. if the wake-up source is not due to a falling edge on rst , there is no time restriction on how soon software may place the device back into sleep mode. a 4.7 k: pullu p resistor to vdd is recommend for rst to prevent noise glitches from waking the device. 19.7. configuring wakeup sources before placing the device in a low power mode, one or more wakeup sources should be enabled so that the device does not remain in the low power mode i ndefinitely. for idle mode, this includes enabling any interrupt. for stop mode, this includes enabling any reset source or relying on the rst pin to reset the device. wake-up sources for suspend and sleep modes are configured through the pmu0cf register. wake-up sour ces are enabled by writing 1 to the corresponding wake-up source enable bit. wake-up sources must be re-enabled each time the device is placed in suspend or sleep mode, in the same write that places the device in the low power mode. the reset pin is always enabled as a wa ke-up s o urce. on the falling edge of rst , the device will be awaken from sleep mode. the device must remain awake for more than 15 s in order for the reset to take p l ace. 19.8. determining the event that caused the last wakeup when waking from idle m ode, the cpu will vector to th e interrupt which caused it to wake up. when wak - ing from stop mode, the rstsrc register may be re ad to dete rmine the cause of the last reset. upon exit from suspend or sleep mode, the wake-up fl ags in the pmu0cf r egister can be read to deter - mine the event which caused the devi ce to wake up. after waking up, the wake-up flags will continue to be updated if any of the wake-up events occur. wake-up flags are always updated, even if they are not enabled as wake-up sources. all wake-up flags enabled as wake-up sources in pmu0cf must be cle ared before the device can enter suspend or sleep mode. after clearing the wake-up flags, each of the enabled wake-up events should be checked in the individual peripherals to ensure that a wake-up event did not occur while the wake-up flags were being cleared.
si102x/3x 272 rev. 0.3 sfr page = 0x0; sfr address = 0xb5 sfr definition 19.4. pmu0cf: power management unit configuration 1,2,3 bit 7 6 5 4 3 2 1 0 name sleep suspend clear rstwk rtcfwk rtcawk pmatwk cpt0wk type w w w r r/w r/w r/w r/w reset 0 0 0 varies varies varies varies varies bit name description write read 7 sleep sleep mode select writing 1 places the de vice in sleep mode. n/a 6 suspend suspend mode select writing 1 places the device in suspend mode. n/a 5 clear wake-up flag clear writing 1 clears all wake- up fla gs. n/a 4 rstwk reset pin wake-up flag n/a set to 1 if a falling edge has be en detected on rst . 3 rtcfwk smartclock oscillator fa il w ake-up source enable and flag 0: disable wake-up on smartc lock osc. fail. 1: enable wake-up on smartc lock osc. fail. set to 1 if the smart - clock oscillator has failed. 2 rtcawk smartclock alarm wa ke-up source enable and flag 0: disable wake-up on smartclock alarm. 1: enab le wake-up on smartclock alarm. set to 1 if a smartclock alar m has occurred. 1 pmatwk port match wake-up sour ce ena ble and flag 0: disable wake-up on port match event. 1: enable wake-up on ? port match event. set to 1 if a port match event ha s occurred. 0 cpt0wk comparator0 wake-up sour ce ena ble and flag 0: disable wake-up on compar ator0 rising edge. 1: enable wake-up on compar ator0 rising edge. set to 1 if comparator0 ri sing edge has occurred. notes: 1. read-modify-write operations (orl, an l, e tc.) should not be used on this register. wake-up sources must be re-enabled each time the sleep or suspend bits are written to 1. 2. th e low power internal oscillator cannot be disabled and the mcu cannot be placed in suspend or sleep mode i f any wake-up flags are set to 1. software should clear all wake-up sources after each reset and after each wake-up from suspend or sleep modes. 3. pmu0 requi res two system clocks to update the wake-up source flags after waking from suspend mode. the wake-up source flags will read ?0? during the first two system clocks following the wake from suspend mode.
rev. 0.3 273 si102x/3x sfr page = 0x0; sfr address = 0xb6 sfr definition 19.5. pmu0fl: power management unit flag 1,2 bit 7 6 5 4 3 2 1 0 name batmwk reserved pc0wk type rr rrrr/wr/wr/w reset 00 00000varies bit name description write read 7:3 unused unused don?t care. 0000000 2 batmwk vbat monitor (inside lcd logic) wake-up source enable and flag 0: disable wake-up on vbat monitor event. 1: enable wake-up on cs0 even t. set to 1 if vbat monitor ev en t caused the last wake-up. 1 reserved reserved must write 0. always reads 0. 0 cs0wk pulse counter wake-up sour ce ena ble and flag 0: disable wake-up on pc0 event. 1: enab le wake-up on pc0 even t. set to 1 if pc0 event cau s ed the last wake-up. notes: 1. the low power internal oscillator cannot be disabled and the mcu cannot be placed in suspend or sleep mode i f any wake-up flags are set to 1. software should clear all wake-up sources after each reset and after each wake-up from suspend or sleep modes. 2. pmu0 req u ires two system clocks to update the wake-u p source flags after waking from suspend mode. the wake-up source flags will read 0 during the first tw o system clocks following the wake from suspend mode.
si102x/3x 274 rev. 0.3 sfr page = 0x0; sfr address = 0xb6 sfr definition 19.6. pmu0md: power management unit mode bit 7 6 5 4 3 2 1 0 name rtcoe wakeoe mondis type r/w r/w r/w r/w r/w r/w r/w r/w reset 00 000000 bit name function 7 rtcoe buffered smartclock output enable. enables the buffered smartclo ck os cillator output on p0.2. 0: buffered smartclock output not enabled. 1: buffered smartclock output not enabled. 6 wakeoe wakeup request output enable. enables the sleep mode wake-up request signal on p0.3. 0: wake-up request signal is not enabled. 1: wake-up request signal is enabled. 5 mondis por supply monitor disable. writing a 1 to this bit disables the por supply monitor. 4:0 unused read = 00000b. write = don?t care.
rev. 0.3 275 si102x/3x sfr page = all pages; sfr address = 0x87 19.9. power manage ment specifications see ta b l e 4.7 on page 61 for detailed power management specifications. sfr definition 19.7. pcon: power manageme nt control register bit 7 6 5 4 3 2 1 0 name gf[4:0] pwrsel stop idle type r/w r/w w w reset 00 000000 bit name description write read 7:3 gf[5:0] general purpose flags sets the logic value. returns the logic value. 2 pwrsel power select 0: vbat is selected as the input to vreg0. 1: vdc is selected as the input to vreg0. 1 stop stop mode select writing 1 places the de vice in stop mode. n/a 0 idle idle mode select writing 1 places the device in idle mode. n/a
si102x/3x 276 rev. 0.3 20. on-chip dc-dc buck converter (dc0) si102x/3x devices include an on-chip step down dc-dc converter to ef ficiently utilize the energy stored in the battery, thus extending the operational life time. the dc-dc converter is a switching buck converter with an input supply of 1.8 to 3.8 v and an output that is pr o g rammable from 1.8 to 3.5 v in steps of 0.1 v. the batt ery voltage should be at least 0.4 v higher than the programmed output voltage. the programmed out - put voltage has a default value of 1.9 v. the dc-dc converter can supply up to 250 mw. the dc-dc con - verter can be used to po wer the mcu and/ or external devices in the system (e.g., an rf transceiver). the dc-dc converter has a built in volt age referenc e and oscillator, and will automatically limit or turn off the switching activity in case the peak inductor current rises beyond a safe limit or the output voltage rises above the programmed target value. this allows the dc -dc converter output to be safely overdriven by a secondary power source (when available) in order to preserve battery life. wh en enabled, the dc-dc con - verter can source current into the ou tput cap acitor, but cannot sink curr ent. the dc-dc converter?s settings can be modified using sfr registers described in section 20.8 . figure 20.1 shows a block diagram of the buck converter. figure 20.1. step down dc-dc buck converter block diagram vbat vdc vbatdc gnd 2.2 uf i load control logic m1 dc/dc converter sfr control local oscillator voltage reference 4.7 uf 0.56 uh + 0.1uf + 0.01uf ind mbyp gnddc +0.1uf +0.01uf
rev. 0.3 277 si102x/3x 20.1. startup behavior the dc-dc converter is enabled by setting bit dc0en (dc0md.0) to logic 1. when first enabled, the m1 switch turns on and continues to supply current into the output capacitor through the inductor until the vdc output voltage reache s the programmed level set by by the vsel bits (dc0cf.[6:3]). the peak transient current in the inductor is limited fo r sa fe operation. the peak inductor current is pro - grammable using the ilimit bits (dc0md.[6:4]). the pea k indu ctor current, size of the output capacitor and the amount of dc load cu rrent present during startup will determine the length of time it takes to charge the output capacitor. the rdyh and rdyl bits (dc0rdy.7 and dc0dry.6) may be used to determine when the output voltage is within approximately 100 mv of the programmed voltage. in order to ensure reliable startup of the dc-dc conv er ter , the following restrictions have been imposed: ? the maximum dc load current allowed during startup is given in ta b l e 4.20 on page 69 . if the dc-dc converter is powering external sensors or devices throug h the vdc pin, then the current supplied to these sensors or devices is counted towards this lim it. the in-rush current in to capacitors does not count towards this limit. ? ? the maximum total output capacitance is given in ta b l e 4.20 on page 69 . this value includes the required 2.2 f ceramic output capacitor and any additional capacitance connected to the vdc pin. ? the peak inductor current limit is pr og ra mmable by software as shown in ta b l e 20.1 . limiting the peak inductor current can allow the dc-dc converter to star t u p using a high impedance power source (such as when a battery is near its end of life) or allow inductors with a low curren t rating to be utilized. by default, the peak inductor cu rrent is set to 500 ma. . the peak inductor current is dependent on several fa ctors including the dc load current and can be esti - mated using following equation: efficiency = 0.80 inductance = 0.68 h frequency = 2.4 mhz ? table 20.1. ipeak inductor current limit settings ilimit peak current (ma) 001 200 010 300 011 400 100 500 101 600 i pk 2 i load ? vdc vbatdc ? ?? ? efficiency inductance ? frequency ? ------------------- ---------------------------------------------------------------- --------------- - =
si102x/3x 278 rev. 0.3 20.2. high power applications the dc-dc converter is designed to provide the system with 150 mw of output power. at high output power, an inductor with low dc resistance should be chosen in order to minimize power loss and maximize effi - ciency. at load currents higher than 20 ma, efficiency improvents may be achieved by placing a schottky d i ode (e.g. mbr052lt1) between the ind pin and gnd in parallel with the internal diode (see figure 20.1 ). 20.3. pulse skipping mode the dc-dc converter allows the user to set the minimu m pulse width such that if the duty cycle needs to decrease below a cert ain width in order to maintain regulation , an entire "clock pulse" will be skipped. pulse skipping can provide substantial power savings, pa rticularly at low values of load current. the con - verter will continue to maintain a mi nimum output volt age at its programme d value when pulse skipping is employed, though the output voltage ripple can be high er. another consideration is that the dc-dc will oper - ate with pulse-frequency modulation rather than pulse -wid th modulation, which makes the switching fre - quency spectrum less predictable; this could be an is su e if the dc-dc converter is used to power a radio. 20.4. optimizing board layout the pcb layout does have an effect on the overa ll efficiency. the following guidelines are recommended to acheive the optimum layout: ? place the input capacitor stack as close as possible to the vbatdc pin. the smallest capacitors in the stack should be placed closest to the vbatdc pin. ? place the output capacitor stack as close as possible to the vdc pin. the smallest ca pacitors in the stack should be placed closest to the vdc pin. ? minimize the trace length between the i nd pin, the inductor, and the vdc pin. 20.5. selecting the optimum switch size the dc-dc converter provides the ability to change the size of the bu ilt-in switches. to maximize efficiency, one of two switch sizes may be sele cted. the large switches are ideal for carrying high currents and the small switches are ideal fo r low current applications. the ideal swit chover point to swit ch from the small switches to the large switches is at approximately 5 ma total output current. 20.6. dc-dc converter clocking options the dc-dc converter may be clocked from its internal oscillator, or from any system cl ock source, select - able by the clksel bit (dc0cf.0). the dc-dc conver ter internal oscillator fr equenc y is approximately 2.4 mhz. for a more accurate clock source, the system cl oc k, or a divided version of the system clock may be used as the dc-dc clock source. the dc-dc converter has a built in clock divider (configured using dc0cf[6:5]) which allo ws any system clock frequency over 1.6 mhz to generate a valid clock in the range o f 1.9 to 3.8 mhz. when the precision inte rnal oscillator is selec ted as the system clock source, the oscicl register may be used to fine tune the oscillator frequency and the dc-dc converter cl ock. the oscillator frequency should only be decreased since it is factory calibrated at its maximum frequency. the minimum frequency which can be reached by the oscillator after taking into acco unt process variations is approximately 16 mhz. the system clo ck routed to the dc-dc converter clock divider also may be inverted by setting the clkinv bit (dc0cf.3) to logic 1. these options can be used to mi nimize interference in noise sensitive applications.
rev. 0.3 279 si102x/3x 20.7. bypass mode the dc-dc converter has a bypass switch (mbyp), see figure 20.1 , which allows the output voltage (vdc) to be directly tied to the input supply (vbatdc), bypassing the dc-dc converter. the bypass switch may be u s ed independently from the dc-dc converter. for exam ple, applications that need to power the vdc sup - ply in the lowest power sleep mode can turn on the bypass switch prior to turning off the dc-dc converter in o r der to avoid powering down the ex ternal circuitry connected to vdc. there are two ways to cl ose the bypa ss switch. using the firs t method, forced bypa ss mode, the forbyp bit is set to a logic 1 forc ing the bypass switch to close. clearing the forbyp bit to logic 0 will allow the switch to open if it is not being held closed using automatic bypass mode. the automatic bypass mode, enabled by setting the aut o byp to logic 1, closes the bypass switch when the difference between vbatdc and the programmed ou tput voltage is less than approximately 0.4 v. on ce the difference exceeds approximately 0.5 v, the bypass switch is opened unless being held closed by forced by pass mode. in most systems, automatic bypass mode will be left enabled, and the forced bypass mode will be used to close the switch as needed by the system. 20.8. dc-dc converter register descriptions the sfrs used to configure the dc-dc converter ar e described in the following register descriptions.
si102x/3x 280 rev. 0.3 sfr page = 0x2; sfr address = 0xb1 sfr definition 20.1. dc0cn: dc-dc converter control bit 7 6 5 4 3 2 1 0 name clksel clkdiv[1:0] ad0ckinv clkinv ilimit min_pw[1:0] type r r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 1 1 bit name function 7 clksel dc - dc converter clock source select. specifies the dc-dc converter clock source. 0: the dc-dc converter is cloc k e d from its local oscillator. 1: the dc-dc converter is clocked from the system clock. 6:5 clkdiv[1:0] dc - dc clock divider. divides the dc-dc converter clock when the s yst em clock is selected as the clock source for dc-dc converter. ignored all other times. 00: the dc-dc converter clock is system clock divided by 1. 01: the dc-dc converter clock is system clock divided by 2. 10: the dc-dc converter clock is system clock divided by 4. 11: the dc-dc converter clock is system clock divided by 8. 4 ad0ckinv adc0 clock inversion (clo ck inve rt during sync). inverts the adc0 sar clock de rived from the dc-dc converter clock when the sync bit (dc0cn.3) is enab led. this bit is ignored when the sync bit is set to zero. 0: adc0 sar clock is inverted. 1: adc0 sar clock is not inverted. 3 clkinv dc - dc converter clock invert. inverts the system clock used as th e input t o the dc-dc clock divider. 0: the dc-dc converter clock is not inverted. 1: the dc-dc converter clock is inverted. 2 sync adc0 synchronization enable. when synchronization is enabled, the adc0sc[4:0] bits in the adc0cf register mu st be set to 00000b. 0: the adc is not synchronized to the dc-dc converter. 1: the adc is synchronized to the dc-dc converter. adc0 tracking is performed dur - ing the longest quiet time of the dc-dc conv erter s witching cycle and adc0 sar clock is also synchronized to th e dc-dc converter switching cycle. 1:0 minpw[1:0] dc - dc converter minimum pulse width. specifies the minimum pulse width. 00: minimum pulse detection logic is disabled (no pulse skipping). 01: minimum pulse width is 10 ns. 10: minimum pulse width is 20 ns. 11: minimum pulse width is 40 ns.
rev. 0.3 281 si102x/3x sfr page = 0x2; sfr address = 0xb2 sfr definition 20.2. dc0cf: dc-dc conver ter configuration bit 7 6 5 4 3 2 1 0 name bypass vsel[3:0] oscdis swsel[1:0] type r r/w r/w reset 0 0 0 0 1 0 1 1 bit name function 7 bypass dc - dc converter bypass sw itch active indicator. 0: the bypass switch is open. 1: the bypass switch is closed (vdc is connected to vbatdc). 6:3 vsel[3:0] dc - dc converter output voltage select. specifies the target output voltage. 0000: target output voltage is 1.8 v. 0001: target output voltage is 1.9 v. 0010: target output voltage is 2.0 v. 0011: target output voltage is 2.1 v. 0100: target output voltage is 2.2 v. 0101: target output voltage is 2.3 v. 0110: target output voltage is 2.4 v. 0111: target output voltage is 2.5 v. 1000: target output voltage is 2.6 v. 1001: target output voltage is 2.7 v. 1010: target output voltage is 2.8 v. 1011: target output voltage is 2.9 v. 1100: target output voltage is 3.0 v. 1101: target output voltage is 3.1 v. 1110: target output voltage is 3.3 v. 1111: target output voltage is 3.5 v. 2 vsel[2:0] dc - dc converter local oscillator disabled. 0: the local oscillato r ins ide the dc-dc co nverter is enabled. 1: the local oscillator ins ide the dc-dc converter is disabled. 1:0 swsel[1:0] dc - dc converter power switch select. selects the size of the power switches (m1 , m2). u s ing smaller switches will resut in higher efficiency at low supply currents. 00: minimum switch size, optimized for load currents smaller than 5 ma. 01: reserved. 10: reserved. 11: maximum switch size, optimized fo r loa d currents greater than 5 ma.
si102x/3x 282 rev. 0.3 sfr page = 0x2; sfr address = 0xb3 sfr definition 20.3. dc0md: dc-dc converter mode bit 7 6 5 4 3 2 1 0 name reserved ilimit forbyp autobyp reserved dc0en type r/w r/w r/w r/w r/w r/w reset 0 1 0 0 0 0 0 0 bit name function 7 reserved read = 0b; must write 0b. 6:4 ilimit peak current limit threshold. 000: reserved 001: peak inductor current is limited to 200 ma 010: peak inductor current is limited to 300 ma 011: peak inductor current is limited to 400 ma 100: peak inductor current is limited to 500 ma 101: peak inductor current is limited to 600 ma 110: reserved 111: reserved 3 forbyp enable forced bypass mode. 0: forced bypass mode is disabled. 1: forced bypass mode is enabled. 2 autobyp enable automatic bypass mode. 0: automatic bypass mode is disabled. 1: automatic bypass mode is enabled. 1 reserved read = 1b; must write 1b. 0 dc0en dc - dc converter enable. 0: dc-dc converter is disabled. 1: dc-dc converter is enabled.
rev. 0.3 283 si102x/3x sfr page = 0x2; sfr address = 0xfd 20.9. dc-dc converter specifications see ta b l e 4.20 on page 69 for a detailed listing of dc-dc converter specifications. sfr definition 20.4. dc0rdy: dc-dc conver ter ready indicator bit 7 6 5 4 3 2 1 0 name rdyh rdyl reserved type r r r/w reset 0 0 0 1 1 1 1 1 bit name function 7 rdyh dc0 ready indicator (high threshold). indicates when vdc is 100 mv higher than the target output value. 0: vdc pin voltage is less than the dc0 high threshold. 1: vdc pin voltage is higher than the dc0 high threshold. 6 rdyl dc0 ready indicator (low threshold). indicates when vdc is 100 mv lower than the target output value. 0: vdc pin voltage is less than the dc0 low threshold. 1: vdc pin voltage is higher than the dc0 low threshold. 5:0 reserved read = 011111b; must write 011111b.
si102x/3x 284 rev. 0.3 21. voltage regulator (vreg0) si102x/3x devices include an internal voltage regulator (vreg0) to regulate the internal core supply to 1.8 v from a vdd/dc+ supply of 1.8 to 3.6 v. electrical characteristics for the on-chip regulator are speci - fied in the electrical specifications chapter. the reg0cn register allows the prec ision oscillator bias to be disabled , reducing supply current in all non-sleep power modes. this bias sh ould only be disabled when the prec ision oscillator is not being used. the internal regulator (vreg0) is disabled when the de vice enters sleep mode and remains enabled when the device enters suspend mode. see section ?19. power management? on page 264 for complete details about low power modes. sfr page = 0x0; sfr address = 0xc9 21.1. voltage regulator electrical specifications see ta b l e 4.17 on page 67 for detailed voltage regulato r electrical sp ecifications. sfr definition 21.1. reg0cn: voltage regulator control bit 7 6 5 4 3 2 1 0 name oscbias type r/w r/w r/w r/w r/w r/w r/w r/w reset 00010000 bit name function 7:5 reserved read = 000b. must write 000b. 4 oscbias precision oscillator bias. when set to 1, the bias used by the precision osci llator is forced on. if the precision oscillator is not being used, this bit may be cleared to 0 to to save supply current in all non-sleep power modes. 3:0 reserved read = 0000b. must write 0000b.
rev. 0.3 285 si102x/3x 22. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled all sfrs are reset to the predefined values noted in the sfr descriptions. the contents of ram are unaf - fected during a reset; any previously stored data is pre s erved as long as power is not lost. since the stack pointer sfr is reset, the stack is effectively lost , even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur - ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to an internal os cillator . refer to section ?23. clocking sources? on page 293 for information on selecting and configur - ing the system clock source. the wa tc hdog t imer is enabled with the system clock divided by 12 as its clock source ( section ?34.4. watchdog timer mode? on page 524 details the use of the watchdog timer). program execution begins at location 0x0000. figure 22.1. reset sources pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf system clock cip-51 microcontroller core extended interrupt handler en wdt enable mcd enable illegal flash operation rst (wired-or) '0' + - comparator 0 vdc + - supply monitor enable vbat switch smartclock rtc0re c0rsef power-on reset power management block (pmu0) system reset vbat power on reset reset vbat + - supply monitor enable
si102x/3x 286 rev. 0.3 22.1. power-on reset during power-up, the device is held in a reset state and the rst pin voltage tracks the supply voltage (through a weak pull-up) until the device is released from reset. after the supply settles above vpor, a delay occurs before the device is released from re set; the delay decreases as the supply ramp time increases (ramp time is defined as how fast the supply ramps from 0 v to v por ). figure 22.2 plots the power-on and supply monitor reset timi ng. for valid ramp times (les s than 3 ms), the power-on reset delay (t pordelay ) is typically 7 ms (v dd = 1.8 v) or 15 ms (v dd = 3.6 v). note: the maximum supply ramp time is 3 ms; slower ramp times may cause the device to be released from reset before the supply reaches the v por level. on exit from a power-on reset, the porsf fl ag (rstsrc.1) is set by hardware to logic 1. when porsf is set, a ll of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000), software can read the porsf flag to determine if a power-up was the cause of reset. the contents of internal data memory should be assumed to be undefined after a power-on reset. the por supply monitor will continue to monitor the vba t supply , even in slee p mode, to reset the sys - tem if the supply voltage drops below vpor. it can be disab l ed to save power by writing 1 to the mondis (pmu0md.5) bit. when the por supply monitor is di sabled, all reset sources will trigger a full por and will re-enable the por supply monitor. figure 22.2. power-on reset timing diagram power-on reset power-on reset rst t volts logic high logic low t pordelay s u p p l y v o l t a g e v por supply voltage see specification table for min/max voltages. t pordelay
rev. 0.3 287 si102x/3x 22.2. power-fail reset si102x/3x devices have two active mode supply monitors that can hold the system in reset if the supply voltage drops below v rst . the first of the two identical supply moni tors is connected to the output of the supply select switch (which chooses the vbat or vdc pin as the source of the digital supply voltage) and is enabled and select ed as a reset source after each power-on or power-fail reset. this supply monitor will be referred to as the digital supply monitor. the sec ond supply monitor is connected directly to the vbat pin an is disabled after each power- on or power-fail reset. this supply monitor will be refe rred to as the analog supply monitor. the analog supply monitor shou ld be enabled any time the supply select switch is set to the vdc pin to ensure that the vbat supply does not drop below v rst . when enabled and selected as a reset source, any power d o wn transition or power irregularity that causes the monitored supply voltage to drop below v rst will cause the rst pin to be driven low and the cip-51 will be held in a reset state (see figure 22.2 ). when the supply voltage returns to a level above v rst , the cip-51 will be released from the reset st ate. after a power-fail reset, the porsf flag reads 1, the co nten ts of ram invalid, and the digital supply moni - tor is enabled and selected as a reset source. the enabl e st ate of either supply monitor and its selection as a reset source is only altered by power-on and power-fail resets. for example, if the supply monitor is de- selected as a reset source and disabled by software, then a software reset is performed, the supply moni - tor will remain disabled and de-selec ted af ter the reset. in battery-operated systems, the contents of ram c an be preserved near the end of the battery?s usable life if the device is placed in sleep mode prior to a power-fail reset occurring. when the device is in sleep mode, the power-fail reset is automatically disabled, bot h active mode supply monitors are turned off, and the contents of ram are preserved as long as the supply does not fall below v por . a large capacitor can be used to hold the power supply voltage above v por while the user is replacing the battery. upon waking from sleep mode, the enable and reset source select state of the v dd supply monitor are restored to the value last set by the user. to allow software early notification that a power failure is about to occur, the vddok bit is cleared when the supply falls below the v warn threshold. the vddok bit can be configured to generate an interrupt. each of the active mode supply montio rs have their independent vddok and v warn flags. see section ?17. interrupt hand le r? on page 238 for more details. important note: t o protect the integrity of flash contents, the active mode supply monitor(s) must be enabled and selected as a reset source if software contains routines which erase or write flash memory. if the digital supply monitor is not enabled, an y erase or write perfo rmed on flash memory will cause a flash error device reset.
si102x/3x 288 rev. 0.3 important notes: ? the power-on reset (por) delay is not incurred after a supply monitor reset. see section ?4. electrical characteristics? on page 50 for complete electrical ch ar acteristics of the acti ve mode supply monitors. ? software should take care not to inadvertently disable the supply monitor as a reset source when writing to rstsrc to enable other reset sources or to trigger a software reset. all writes to rstsrc should explicitly set porsf to 1 to keep t he supply monitor enabled as a reset source. ? the supply monitor must be enabled before selecting it as a reset source . selecting the supply monitor as a reset source before it has stabilized may generate a syste m reset. in systems where this reset would be undesirable, a delay should be introduce d between enabling the supply monitor and selecting it as a reset source. see section ?4. electrical characteristics? on page 50 for minimum supply monitor turn-on time. no d elay should be introduced in systems where software contains routines that erase or write flash memory. the procedure for enabling the v dd supply monitor and selecting it as a reset source is shown below: 1. enable the supply monitor (vdmen bit in vdm0cn = 1). 2. w a it for the supply monitor to stabilize (optional). 3. select the supply monitor as a reset source (porsf bit in rstsrc = 1).
rev. 0.3 289 si102x/3x sfr page = all pages; sfr address = 0xff sfr definition 22.1. vdm0cn: vdd supply monitor control bit 7 6 5 4 3 2 1 0 name vdmen vddstat vddok vddokie vbmen vbstat vbok vbokie type r/w r r r/w r/w r r r/w reset 1 varies varies 0 0 0 0 0 bit name function 7 vdmen digital supply monitor enable (power select switch output). 0: digital supply monitor disabled. 1: digital supply monitor enabled. 6 vddstat digital supply status. this bit indicates the current digital power supply status. 0: digital supply is at or below the v rst threshold. 1: digital supply is above the v rst threshold. 5 vddok digital supply status (early warning). this bit indicates the current digital power supply status. 0: digital supply is at or below the vdd warn threshold. 1: digital supply is above the vdd warn threshold. 4 vddokie digital early warning interrupt enable. enables the v dd early warning interrupt. 0: v dd early warning interrupt is disabled. 1: v dd early warning interrupt is enabled. 3 vbmen analog supply monitor enable (vbat pin). 0: analog supply monitor disabled. 1: analog supply monitor enabled. 2 vbstat analog supply status. this bit indicates the analog (vbat) power supply status. 0: vbat is at or below the v rst threshold. 1: vbat is above the v rst threshold. 1 vbok analog supply status (early warning). th is bit indicates the current vbat power supply status. 0: vbat is at or below the vdd warn threshold. 1: vbat is above the vdd warn threshold. 0 vbokie analog early warni ng inte rrup t enable. enables the vbat early warning interrupt. 0: vbat early warning interrupt is disabled. 1: vbat early warning interrupt is enabled.
si102x/3x 290 rev. 0.3 22.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert - ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induced resets. see ta b l e 4.6 for complete rst pin spec - ifications. the external reset remains functional even wh en the device is in the low power suspend and sleep modes. the pinrsf flag (rstsrc.0) is set on exit from an external reset. 22.4. missing cl ock detector reset the missing clock detector (mcd) is a one-shot circuit that is triggered by the system clock. if the system clock remains high or low for more than 100 s, the one-shot will time out an d generate a reset. af ter a mcd reset, the mcdrsf flag (rstsrc.2) will read 1, signifying the mcd as the reset source; otherwise, this bit reads 0. writing a 1 to the mcdrsf bit enables the missing clock detector; writing a 0 disables it. the missing clock detector reset is automatically disabl ed when the device is in the low power suspend or sleep mode. upon exit from either low power state, the enabled/disabled state of this reset source is restored to its previous value. the state of the rst pin is unaffected by this reset. 22.5. comparator0 reset comparator0 can be configured as a reset source by writing a 1 to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0?), the device is put into the reset state. after a compar ator0 reset, the c0rsef flag (rst src.5) will read 1 signifying comparator0 as the reset source; otherwise, this bit reads 0. the comparator0 reset source remains func - tional even when the device is in the low power suspen d an d sl eep states as long as comparator0 is also enabled as a wake-up source. the state of the rst pin is unaffected by this reset. 22.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of control during a system malfunction. the pca wdt function can be enabled or disabled by software as described in section ?34.4. watchdog timer mode? on page 524 ; the wdt is enabled and clocked by sysclk / 12 following any reset. if a sys tem malfunction prevents user software from updating the wdt, a reset is ge nerated and the wdtrsf bit (rstsrc.5) is set to 1. the pca watchdog timer reset source is automatically disabled when the device is in the low power sus - pend or sleep mode. upon exit from either low power st ate, th e en abled/disabled st ate of this reset source is restored to its previous value.the state of the rst pin is unaffected by this reset.
rev. 0.3 291 si102x/3x 22.7. flash error reset if a flash read/write/era se or program read targets an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to 1 and a movx write operation targets an address above the lock byte address. ? a flash read is attempted above user code space. this occurs when a movc operation targets an address above the lock byte address. ? a program read is attempted above user code space. this occurs when user code attempts to branch to an address above the lock byte address. ? a flash read, write or erase attempt is rest ricted due to a flash security setting (see section ?18.3. security options? on page 253 ). ? a flash write or erase is attempted while the v dd monitor is disabled. the ferror bit (rstsrc.6) is set following a fla sh error reset. the state of the rst pin is unaffected by this reset. 22.8. smartclock (real time clock) reset the smartclock can generate a syst em reset on two events: smar tclock oscillator fail or smart - clock alarm. the smartclock oscillator fail event occu rs when the smar tclock missing clock detector is enabled and the smartclock clock is below approximately 20 khz. a smartclock alarm event occurs whe n the smartclock alarm is enabled and the smartclock timer value matches the alarmn regis - ters. the smartclock can be configured as a reset source by writing a 1 to the rtc0re flag (rst - src.7). the smartclock re set r emains functional even when the device is in the low power suspend or sleep mode. the state of the rst pin is unaffected by this reset. 22.9. software reset software may force a reset by wr iting a 1 to the swrsf bit (rstsr c.4). the swrsf bit will read 1 fol - lowing a software forced reset. the state of the rst pin is unaffected by this reset.
si102x/3x 292 rev. 0.3 sfr page = 0x0; sfr address = 0xef. sfr definition 22.2. rstsrc: reset source bit 7 6 5 4 3 2 1 0 name rtc0re ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf type r/w r r/w r/w r r/w r/w r reset varies varies varies varies varies varies varies varies bit name description write read 7 rtc0re smartclock reset enable and flag 0: disable smartclock as a reset source. 1: enab le smartclock as a reset so urce. set to 1 if smartclock alarm or oscillator fail caus ed the last reset. 6 ferror flash error reset flag. n/a set to 1 if flash read/w rite/erase error caus ed the last reset. 5 c0rsef comparator0 reset enable and flag . 0 : disable comparator0 as a reset so urce. 1: enable comparator0 as a reset so urce. set to 1 if comparator0 caused the last reset . 4 swrsf software reset force and flag. writing a 1 forces a sys - tem reset. set to 1 if last reset was cau s ed by a write to swrsf. 3 wdtrsf watchdog timer reset flag. n/a set to 1 if watchdog timer o v erflow caused the last reset. 2 mcdrsf missing clock detector (mcd) ena b le and flag. 0: disable the mcd. 1: enable the mcd. the mcd triggers a reset if a mis sing clock condition is d etected. set to 1 if missing clock detector time out caused the last reset. 1 porsf power-on / power-fail re se t flag, and power-fail reset enable. 0: disable the vdd supply monitor as a reset source. 1: enable the vdd supply monitor as a reset source. 3 set to 1 anytime a power- on or v dd monitor reset occurs. 2 0 pinrsf hw pin reset flag. n/a set to 1 if rst pin caused the last reset. notes: 1. it is safe to use read-mod ify-write opera tions (orl, anl, etc.) to ena ble or disable specific interrupt sources. 2. if porsf read back 1, the value read from all ot her bits in this register are indeterminate. 3. w riting a 1 to porsf before the vdd supp ly monitor is stabilized may generate a system reset.
rev. 0.3 293 si102x/3x 23. clocking sources si102x/3x devices include a programmable precision intern al oscillator, an external oscillator drive circuit, a low power internal o scillator, and a smartclock real time clo ck oscillator. the prec ision internal oscilla - tor can be enabled/disabled and calibrated using the oscicn and oscicl re gisters, as shown in figure 23.1 . the external oscillator can be configured usin g the oscxc n register. the low power internal oscillator is automatically enabled and disabled w h en sele cted and deselected as a clock source. smart - clock operation is described in the smar tclock osc illator chapter. the system clock (sysclk) can be der ived from the precision internal oscil lator , external oscillator, low power internal oscillator, low power internal oscillato r divided by 8, or smartc lock oscillator. the global clock divider can generate a system clock that is 1, 2, 4, 8, 16, 32, 64, or 128 times slower that the selected input clock source. oscillator electric al specifications can be found in the electrical specifications chapter. figure 23.1. clocking sources block diagram the proper way of changing the system clock when bo th the clock source and the clock divide value are being changed is as follows: if switching from a fast ?undivided? clock to a slower ?undivided? clock: 1. change the clock divide value. 2. poll for clkrdy > 1. 3. change the clock source. if switching from a slow ?undivided? clock to a faster ?undivided? clock: 1. change the clock source. 2 . change the clock divide value. 3. poll for clkrdy > 1. external oscillator drive circuit xtal1 xtal2 option 2 vdd xtal2 option 1 10m ? option 4 xtal2 oscxcn xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 precision internal oscillator en oscicl oscicn ioscen ifrdy sysclk clksel clkdiv2 clkdiv1 clkdiv0 clkrdy clksl1 clksl0 smartclock oscillator clock divider n low power internal oscillator low power internal oscillator smartclock oscillator external oscillator precision internal oscillator clkrdy option 3 xtal2 8 low power internal oscillator divided by 8
si102x/3x 294 rev. 0.3 23.1. programmable precisi on internal oscillator all si102x/3x devices inclu de a programmable precision internal osc illator that may be selected as the sys - tem clock. oscicl is factor y ca libr ated to obtain a 24.5 mhz frequency. see section ?4. electrical charac - teristics? on page 50 for complete oscilla tor specifications. the precision oscillator supports a spread spectrum mode which modulates the out put frequency in order to reduce the emi generated by t he system. when enabled (sse = 1), the oscillator output frequency is modulated by a stepped triangle wave whose frequenc y is equal to the oscillato r frequency divided by 384 (63.8 khz using the factory calibration). the dev i ation from the nominal oscillator frequen cy is +0%, ?1.6%, and the step size is typically 0.26% of the nominal fr equency. when using this mode, the typical average oscillator frequency is lowered from 24.5 mhz to 24.3 mhz. 23.2. low power in ternal oscillator all si102x/3x devices include a low power internal os cillator that defaults as the system clock after a sys - tem reset. the low po wer internal osc illa tor frequency is 20 mhz 10% and is automatically enabled when select ed as the system clock and disabled when not in use. see section ?4. electrical characteristics? on page 50 for complete oscilla tor specific ations. 23.3. external osci llator drive circuit all si102x/3x devices include an external oscillator ci rcuit that may drive an exte rnal crystal, ceramic reso - nator, capacitor, or rc network. a cmos clock may also provide a clock input. figure 23.1 shows a block diagram of the four external oscillator options. the ex ternal oscillator is enabled and conf igured using the oscxcn register. the external oscillato r output may be se lected as the system clock or used to clock some of the digital peripherals (e.g., timers, pca, etc.). see the data sheet chapters for each digital peripheral for details. see section ?4. electrical characteristics? on page 50 for complete oscilla tor specifications. 23.3.1. external crystal mode if a crystal or ceramic resonator is used as the ex ternal oscillator , the crystal/resonator and a 10 m ??resis - tor must be wired across the xtal1 and xtal2 pins as shown in figure 23.1 , option 1. appropriate load - ing capacitors should be added to xtal1 and xtal2, and both pins should be configured for analog i/o with th e dig ital output drivers disabled. figure 23.2 shows the external oscillator circuit for a 20 mhz quartz crystal with a manufacturer recom - mended load capacitance of 12.5 pf. loading capacitors are "in series" as seen by the crystal and "in par - allel" with the stray capacitance of the xtal1 and xtal2 pins. the total value of the each loading cap a citor and the stray capacitance of each xtal pin should equal 12.5 pf x 2 = 25 pf. with a stray cap a citance of 10 pf per pin, the 15 pf capacitors yield an equivale nt se rie s capacitance of 12.5 pf across the cry stal. note: the recommended load capacitance depends upon the crystal and the manufacturer. please refer to the crystal data sheet when completing these calculations.
rev. 0.3 295 si102x/3x figure 23.2. 25 mhz external crystal example important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces which could introduce noise or interference. when using an external crystal, the external oscillator drive circuit must be configured by software for crys - tal oscillator mode or cryst al oscillator mode with divide by 2 stage . the divide by 2 stage ensures that the clock derived from the external o scillator has a duty cycle of 50%. t he external oscillator frequency con - trol value (xfcn) must also be specified based on th e cr ystal frequency. the selection should be based on ta b l e 23.1 . for example, a 25 mhz crystal requires an xfcn setting of 111b. when the crystal oscillator is first enabled, the external osc illator valid detector allo ws software to deter - mine when the external system clock has stabilized. s witching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior . the recommended procedu re for starting the crystal is as follows: 1. configure xtal1 and xtal2 for analog i /o a nd disable the digital output drivers. 2. configure and enable the external oscillator. 3. poll for xtlvld => 1. 4. switch the syste m clock to the external oscillator. table 23.1. recommended xfcn settings for crystal mode xfcn crystal frequency bias current typical supply current (vdd = 2.4 v) 000 f ? 20 khz 0.5 a 3.0 a, f = 32.768 khz 001 20 khz ?? f ?? 58 khz 1.5 a 4.8 a, f = 32.768 khz 010 58 khz ? f ?? 155 khz 4.8 a 9.6 a, f = 32.768 khz 011 155 khz ? f ?? 41 5 kh z 14 a 28 a, f = 400 khz 100 415 khz ? f ?? 1.1 mhz 40 a 71 a, f = 400 khz 101 1.1 mhz ? f ?? 3.1 mhz 120 a 193 a, f = 400 khz 110 3.1 mhz ? f ?? 8.2 mhz 550 a 940 a, f = 8 mhz 111 8.2 mhz ? f ?? 25 mhz 2.6 ma 3.9 ma, f = 25 mhz 15 pf 15 pf 25 mhz xtal1 xtal2 10 mohm
si102x/3x 296 rev. 0.3 23.3.2. external rc mode if an rc network is used as the external oscillator, the circuit should be configured as shown in figure 23.1 , option 2. the rc network should be added to xtal2, and xtal2 should be configured for analog i/o with the digital output drivers disabled. xtal1 is not affected in rc mode. the capacitor should be no greater than 100 pf; however for very small cap acitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. the resistor should be no smaller than 10 k ? . the osc illation frequency can be de termined by the following equation: where ? f = frequency of clock in mhzr = pu ll-up resistor value in k ? ? v dd = power supply voltage in voltsc = capacitor value on the xtal2 pin in pf to determine the required external oscillator frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to produce the desired frequ ency of oscillation. for example, if the fre - quency desired is 100 khz, let r = 246 k ? an d c = 50 pf: where ? f = frequency of clock in mhz r = pull-up resistor value in k ? ? v dd = power supply voltage in volts c = capacitor value on the xtal2 pin in pf referencing table 23.2 , the recommended xfcn setting is 010. when the rc oscillator is first enabled , the external os cillator valid detect or allows software to determine when oscillation has stabilized. the recommended procedure fo r starting the rc oscillator is as follows: 1. configure xtal2 for analog i/o and disable the digital output drivers. 2. configure and enable the external oscillator. 3. poll for xtlvld > 1. 4. switch the syste m clock to the external oscillator. table 23.2. recommended xfcn settings for rc and c modes xfcn approximate freque ncy range (rc and c mode) k factor (c mode) typical supply current/ actual measu red frequency (c mode, vdd = 2.4 v) 000 f ?? 25 khz k factor = 0.87 3.0 a, f = 11 khz, c = 33 pf 001 25 khz ?? f ?? 50 khz k factor = 2.6 5.5 a, f = 33 khz, c = 33 pf 010 50 khz ?? f ?? 10 0 khz k factor = 7.7 13 a, f = 98 khz, c = 33 pf 011 100 khz ?? f ?? 200 khz k factor = 22 32 a, f = 270 khz, c = 33 pf 100 200 khz ?? f ?? 400 khz k factor = 65 82 a, f = 310 khz, c = 46 pf 101 400 khz ?? f ?? 800 khz k factor = 180 242 a, f = 890 khz, c = 46 pf 110 800 khz ?? f ?? 1.6 mhz k factor = 664 1.0 ma, f = 2.0 mhz, c = 46 pf 111 1.6 mhz ?? f ?? 3.2 mhz k factor = 1590 4.6 ma, f = 6.8 mhz, c = 46 pf f 1.23 10 3 ? rc ? ------------------------ - = f 1.23 10 3 ? rc ? ------------------------ - 1.23 10 3 ? 246 50 ? ------------------------ - 100 khz ===
rev. 0.3 297 si102x/3x 23.3.3. external capacitor mode if a capacitor is used as the external oscillator, the circuit should be configured as shown in figure 23.1 , option 3. the capacitor should be added to xtal2, a nd xt al2 should be configured for analog i/o with the digital output drivers disabled. xtal1 is not affected in rc mode. the capacitor should be no greater than 100 pf; however, for very small capa citors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. the oscillation fr equency and th e required external oscillator frequency control value (xfcn) in the os cxcn register can be determined by the following equation: where ? f = frequency of clock in mhzr = pu ll-up resistor value in k ? ? v dd = power supply voltage in voltsc = capacitor value on the xtal2 pin in pf below is an example of selecting the capacitor an d finding the frequency of oscillation assume v dd = 3.0 v and f = 150 khz: since a frequency of roughly 150 khz is desired, select the k factor from ta b l e 23.2 as kf = 22: therefore, the xfcn value to use in this exam ple is 011 and c is approximately 50 pf. the recommended startup procedure for c mode is the same as rc mode. 23.3.4. external cmos clock mode if an external cmos clock is used as the external oscillator , the clock shou ld be directly routed into xtal2. the xtal2 pin should be configured as a digital input. xtal1 is not used in external cmos clock mode. the external oscillator valid detector will always return zero w hen the external oscilla tor is configured to external cmos clock mode. f kf cv dd ? --------------------- = f kf cv dd ? --------------------- = 0.150 mhz kf c3.0 ? ----------------- = 0.150 mhz 22 c 3.0 v ? ----------------------- = c 22 0.150 mhz 3.0 v ? ---------------------------------------------- - = c 48.8 pf =
si102x/3x 298 rev. 0.3 23.4. special function regi sters for selecting and conf iguring the system clock the clocking sources on si102x/3x devices are e nabled and configured us ing the oscicn, oscicl, oscxcn and the smartclock internal registers. see section ?24. smartclock (real time clock)? on page 302 for smartclock register descriptions. the syst em c l ock source for the mcu can be selected using the clksel register. to minimize active mode curren t, th e oneshot timer whic h sets flash read time should by bypassed when the system clock is greater than 10 mhz. see the flscl register description for det a ils. the clock selected as the system cloc k can be divided by 1, 2, 4, 8, 16 , 32, 64, or 128. when switching between two clock divide values, the transition may ta ke up to 128 cycles of th e undivided clock source. the clkrdy flag can be polled to determine when the new clock divide value has been applied. the clock divider must be set to "divide by 1" when entering suspend or sleep mode. the system clock source may also be switched on-the -f ly . the switchover takes effect after one clock period of the sl ower oscillator. sfr page = 0x0 and 0xf; sfr address = 0xa9 sfr definition 23.1. clksel: clock select bit 7 6 5 4 3 2 1 0 name clkrdy clkdiv[2:0] clksel[2:0] type r r/w r/w r/w reset 00010010 bit name function 7 clkrdy system clock divider clock ready flag. 0: the selected clock divide setting has not be en applied to the system clock. 1: the selected clock divide setting has been applied to the system clock. 6:4 clkdiv[2:0] system clock divider bits. selects the clock division to be applie d to the undivided sy stem clock source. 000: system clock is divided by 1. 001: system clock is divided by 2. 010: system clock is divided by 4. 011: system clock is divided by 8. 100: system clock is divided by 16. 101: system clock is divided by 32. 110: system clock is divided by 64. 111: system clock is divided by 128. 3 unused read = 0b. must write 0b. 2:0 clksel[2:0] system clock select. selects the oscillator to be used as the undivided sy stem clock source. 000: precision internal oscillator. 001: external oscillator. 010: low power osc illator divided by 8. 011: smartclock oscillator. 100: low power oscillator. all other values reserved.
rev. 0.3 299 si102x/3x sfr page = 0x0; sfr address = 0xb2 sfr definition 23.2. oscicn: internal os cillator control bit 7 6 5 4 3 2 1 0 name ioscen ifrdy type r/w r r/w r/w r/w r/w r/w r/w reset 0 0 varies varies varies varies varies varies bit name function 7 ioscen internal oscill at o r enable. 0: internal oscillator disabled. 1: internal oscillator enabled. 6 ifrdy internal oscillator frequency ready flag. 0: internal oscillator is not r unning at it s programmed frequency. 1: internal oscillator is runn ing at it s programmed frequency. 5:0 reserved must perform read-modify-write. notes: 1. rea d-modify-write operations such as orl and anl must be use d to set or clear the enable bit of this register. 2. oscbias (reg0cn.4) must be set to 1 before enabling the precision internal oscillator.
si102x/3x 300 rev. 0.3 sfr page = 0xf; sfr address = 0xb3 sfr definition 23.3. oscicl: internal oscillator calibration bit 7 6 5 4 3 2 1 0 name sse oscicl [6:0] type r/w r r/w r/w r/w r/w r/w r/w reset 0 varies varies varies var ies v aries varies varies bit name function 7 sse spread spectrum enable. 0: spread spectrum clock dithering disabled. 1: spread spectrum clock dithering enabled. 6:0 oscicl internal oscillator calibration. factory calibrated to obtain a frequency of 24.5 mhz. incrementing this register decreases the osc illator frequency and de crementing this regi ster increases the oscillator frequency. the step size is approximately 1% of the calibra ted frequency. the recommended calibration frequency range is between 16 and 24.5 mhz. note: if the precision internal oscillator is selected as the system clock, the following proc edure should be used when changing the value of the internal oscillator calibration bits. ? 1. switch to a different clock source. ? 2. disable the oscillator by writing oscicn.7 to 0. ? 3. change oscicl to the desired setting. ? 4. enable the oscillator by writing oscicn.7 to 1.
rev. 0.3 301 si102x/3x sfr page = 0x0; sfr address = 0xb1 sfr definition 23.4. oscxcn: external oscillator control bit 7 6 5 4 3 2 1 0 name xclkvld xoscmd[2:0] xfcn[2:0] type r r r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 xclkvld external oscilla tor va lid flag. provides external oscillator status and is valid at all times for a ll modes of operation except external cmos clock mode and external cmos clock mode with divide by 2. in these modes, xclkvld always returns 0. 0: external oscillator is unus e d or not yet stable. 1: external oscillator is running and stable. 6:4 xoscmd external oscillator mode bits. configures the external oscillato r circuit to the selected mode. 00x: external oscillat or circu it disabled. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mode w ith divide by 2 stage. 3 reserved read = 0b. must write 0b. 2:0 xfcn external oscillator frequency control bits. controls the external oscillator bias c urrent. 000-111: see ta b l e 23.1 on page 295 (crystal mode) or ta b l e 23.2 on page 296 (rc or c mode) for recommended settings.
si102x/3x 302 rev. 0.3 24. smartclock (real time clock) si102x/3x devices include an ultra low power 32-bit smartclock peripheral (real time clock) with alarm. the smartclock has a dedicated 32 khz oscillator that can be configured for us e w ith or without a crystal. no external resistor or loading capacitors are requi red. the on-chip loading capacitors are programmable to 16 discrete levels allowing compatibility with a wide range of cr ystals. the smartclock can operate directly from a 1.8?3.6 v battery voltage and remains operational even when the device goes into its low - est power down mode. the smartclock output can be buffered and routed to a gpio pin to provide an ac curate, low frequency clock to other devices while the mcu is in its lowest power down mode ( see ?pmu0md: power management unit mode? on page 274 for more details). si102x/3x devices also support an ultra low power internal lfo that reduces sleep mode current. the smartclock allows a maximum of 36 hour 32-bit independent time-keeping when used with a 3 2 .768 khz watch crystal. the smartclock provides an alarm and missing smartclock events, which cou l d be used as reset or wakeup sources. see section ?22. reset sources? on page 285 and section ?19. power management? on page 264 for details on reset sources and low power mode wake-up sources, respectively. figure 24.1. smartclock block diagram smartclock oscillator smartclock cip-51 cpu xtal4 xtal3 rtc0cn capturen rtc0xcf rtc0xcn rtc0cf rtc0key rtc0adr rtc0dat interface registers internal registers smartclock state machine w/ 3 independent alarms wake-up 32-bit smartclock timer programmable load capacitors power/ clock mgmt interrupt rtcout lfo alarmnbn
rev. 0.3 303 si102x/3x 24.1. smartclock interface the smartclock interface consists of three regist ers: rtc0key, rtc0adr, and rtc0dat. these inter - face registers are located on the cip-51?s sfr map and provide access to the smartclock internal regis - ters listed in ta b l e 24.1 . the smartclock internal registers can on ly b e accessed indirectly through the smartclock interface. table 24.1. smartclock internal registers smartclock address smartclock register register name description 0x00?0x03 capturen smartclock capture r e gisters four registers used for setting the 32-bit smartclock timer or reading its current value. 0x04 rtc0cn smartclock control re gi ster controls the operation of the smar tclock state machine. 0x05 rtc0xcn smartclock oscillator c o ntrol register controls the operation of the smartclock oscillator. 0x06 rt c0xcf smartclock oscillator co nfigur ation register controls the value of the progammable oscillator load capacitance and enables/disables autostep. 0x07 rtc0cf smartclock co nfigur ation register contains an alarm enable and flag for each smartclock a larm. 0x08?0x0b alarm0bn smartclock alarm r e gisters four registers used for setting or reading the 32-bit smar tclock alarm value. 0x0c?0x0f alarm1bn smartclock alarm r e gisters four registers used for setting or reading the 32-bit smar tclock alarm value. 0x10?0x13 alarm2bn smartclock alarm r e gisters four registers used for setting or reading the 32-bit smar tclock alarm value.
si102x/3x 304 rev. 0.3 24.1.1. smartclock lock and key functions the smartclock interface has an rt c0key register for legacy reasons, however, a ll writes to this regis - ter are ignored. the smartclock interface is always unlocked on si102x/3x. 24.1.2. using rtc0adr and rtc0dat to ac cess smar tclock internal registers the smartclock internal registers can be read and written using rtc0adr and rtc0dat. the rt c0adr register selects the smartclo ck internal register th at will be targeted by subsequent reads or writes. a smartclock write operation is initiated by writing to the rtc0dat register. below is an example of writing to a smartclock internal register. 1. write 0x05 to rtc0adr. this selects the inte r n al rtc0cn register at smartclock address 0x05. 2. write 0x00 to rtc0dat. this operation wr ites 0x00 to the internal rtc0cn register. a smartclock read operation is initiated by writing the register address to rtc0adr and reading from rtc0dat. below is an example of reading a smartclock internal register. 1. write 0x05 to rtc0adr. this selects the inte rn al rtc0cn register at smartclock address 0x05. 2. read data from rtc0dat. this data is a copy of the rtc0cn register. 24.1.3. smartclock interface autoread feature when autoread is enabled, each read from rtc0dat initiates the next indirect read operation on the sma r tclock internal register select ed by rtc0adr. software should set the register address once at the beginning of each series of consecutive reads. auto read is enabled by setting autord (rtc0adr.6) to logic 1. 24.1.4. rtc0adr auto incr ement feature for ease of reading and writing the 32-bit capture and alarm values, rtc0adr automatically incre - ments after each read or write to a capturen or alarmn re gister . this speeds up the process of setting an alarm or reading the current smartclock timer value. autoincrement is always enabled. recommended instruction timing for a multi-byte register read with auto read enabled: mov rtc0adr, #040h mov a, rtc0dat mov a, rtc0dat mov a, rtc0dat mov a, rtc0dat recommended instruction timing for a multi-byte register write: mov rtc0adr, #010h mov rt c0dat, #05h mov rt c0dat, #06h mov rtc0dat, #07h mov rtc0dat, #08h
rev. 0.3 305 si102x/3x sfr page = 0x0; sfr address = 0xae sfr page = 0x0; sfr address = 0xac sfr definition 24.1. rtc0key: smartclock lock and key bit 7 6 5 4 3 2 1 0 name rtc0st[7:0] type r/w reset 00000000 bit name function 7:0 rtc0st smartclock interface status. provides lock status when read. read: 0x02: smar tclock in terface is unlocked. write: writes to rtc0key have no effect. sfr definition 24.2. rtc0adr: smartclock address bit 7 6 5 4 3 2 1 0 name autord addr[4:0] type r r/w r r/w reset 00000000 bit name function 7 reserved read = 0; write = don?t care. 6 autord smartclock interface autoread enable. enables/disables autoread. 0: autoread disabled. 1: autoread enabled. 5 unused read = 0b; write = don?t care. 4:0 addr[4:0] smartclock indirect register address. sets the currently selected smartclock register. see ta b l e 24.1 for a listing of all smartclock indirect registers. note: the addr bits increment after each indirect read/write opera tion that targets a capturen or alarmnbn internal smartclock register.
si102x/3x 306 rev. 0.3 sfr page= 0x0; sfr address = 0xad sfr definition 24.3. rtc0dat: smartclock data bit 7 6 5 4 3 2 1 0 name rtc0dat[7:0] type r/w reset 00000000 bit name function 7:0 rtc0dat smartclock data bits. holds data transferred to/from the internal smartclock register selected by rt c0adr. note: read-modify-write instructions (orl, anl, etc.) should not be used on this register.
rev. 0.3 307 si102x/3x 24.2. smartclock clocking sources the smartclock peripheral is clocked from its ow n timebase, independent of the system clock. the smartclock timebase can be derived from an external cmos clock, the internal lfo, or the smart - clock oscillator circuit, wh ich has tw o modes of operation: cryst al mode, and self-oscillate mode. the oscillation frequency is 32.768 khz in crystal mode and can be programmed in the range of 10 khz to 40 khz in self-oscillate mode. the internal lfo fr equenc y is 16.4 khz 20%. the frequency of the smartc lock oscillator can be measured with respect to another oscillator usin g an on-chip timer. see section ?33. timers? on page 491 for more information on how this can be accomplished. note: the smartclock timebase can be selected as the system clock and routed to a port pin. see section ?23. clocking sources? on page 293 for information on selecting the system clock source and section ?2 7. port input/output? on page 358 for information on how to route the system clock to a port pin. the smartclock timebase can also be routed to a port pin while the device is in its ultra low power sleep mode. see the pmu0md register description for details. 24.2.1. using the smartclock oscillator with a crystal or external cmos clock when using crystal mode, a 32.768 khz crystal should be connected between xtal3 and xtal4. no ot her external components are required. the following steps show how to start the smartclock crystal oscillator in software: 1. configure the xtal3 and xtal4 pins for analog i/o. 2. set s martclock to cryst al mode (xmode = 1). 3. disable automatic gain control (agcen) and enable bias doubling (biasx2) for fast crystal startup. 4. set the desired loading capacitance (rtc0xcf). 5. enable power to t he smartclock oscillator circuit (rtc0en = 1). 6. wait 20 ms. 7. poll the smartclock clock valid bit (clk vld) until the crystal oscillator stabilizes. 8. poll the smartclock load capacitance ready bi t (loadrdy) until the load capacitance reaches its programmed value. 9. enable automatic ga in control (agcen) and disable bias doubling (biasx2) for maximum power savings. 10. enable the smartclock missing clock detector. 11. wait 2 ms. 12. clear the pmu0cf wake-up source flags. ? in crystal mode, the smartclock osc illator may be driven by an extern al cmos clock. the cmos clock should be applied to xtal3. xtal34 should be left fl oating. in this mode, the ex ternal cmos clock is ac coupled into the smartclock and should have a minimum voltage swing of 400 mv. the cmos clock sig - nal voltage should not exceed vdd or drop below gnd . bias levels clos er to vdd will result in lower i/o power consumption be cause the xtal3 pin has a built-in weak pull-up. the smartclock oscillator should be configured to its lowest bias setting with agc disabled. the clkvld bit is indeterminate when using a cmos clock, however, the oscfail bit may be checked 2 ms after smartclock os c illator is pow ered on to ensure that there is a valid cl ock on xtal3. the clkvld bit is fo rced low when biasx2 is disabled.
si102x/3x 308 rev. 0.3 24.2.2. using the smartclock os cillator in self-oscillate mode when using self-oscillate mode, the xtal3 and xtal4 pins are inte rnally shorted toge ther. the following steps show how to configure smartclo ck for use in self-oscillate mode: 1. configure the xtal3 and xtal4 pins for analog i/o and disable the digital driver. 2. set smartclock to self-o scillate mode (xmode = 0). 3. set the desired oscillation frequency: ? for oscillation at about 20 khz, set biasx2 = 0. ? for oscillation at about 40 khz, set biasx2 = 1. 4. the oscillator starts oscillating instantaneously. 5. fine tune the oscillation frequency by adjusting the load capacitance (rtc0xcf). 24.2.3. using the low frequency oscillator (lfo) the low frequency oscillator provides an ultra low power , on-chip clo ck source to the smartclock. the typical frequency of oscillation is 16.4 khz 20%. no external components are required to use the lfo and the xtal3 and xtal4 pins may be used for general purpose i/o without any effect on the lfo. the following steps show how to configure smartclock for use with the lfo: 1. enable and select the low frequency osc illator (lfoen = 1). 2. the lfo starts oscillating instantaneously. when the lfo is enabled, the smartclock oscillator increm ents bit 1 of the 32-bit timer (instead of bit 0). this effectively multiplies the lfo frequency by 2, making the rtc timebase behave as if a 32.768 khz cr yst al is connected at the output. 24.2.4. programmable load capacitance the programmable load capacitance has 16 values to support cryst al osc illators with a wide range of rec - ommended load capacitance. if automatic load capaci t a nce stepping is enabled, the crystal load capaci - tors start at the smallest setting to a llow a fast startup time, then slowly increase the capacitance until the final programmed value is reached. the final programme d loading capacitor value is specified using the loadcap bits in the rtc0xcf register. the loadc ap setting specifies the amount of on-chip load capacitance and does not include any stray pcb capa citance. once the final programmed loading capaci - tor value is reached, the loadrdy flag will be set by hardware to logic 1. when using the smartclock oscillato r in self-oscillate mode, the prog rammable load capacitance can be used to fine tune the oscillation fr equency. in most cases, increasing the load capacitor value will result in a decrease in oscillation frequency. ta b l e 24.2 shows the crystal load capaci t a nce for various settings of loadcap.
rev. 0.3 309 si102x/3x 24.2.5. automatic gain control (crystal mode only) and smartclock bias doubling automatic gain control allows the sm artclock oscillator to trim the osc illation amplitude of a crystal in order to achieve the lowest possible power consumpt ion. automatic gain control automatically detects when the oscillation amplitude has r eached a point where it safe to redu ce the drive current, therefore, it may be enabled during crystal startup. it is recomm ended to enable automatic gain control in most sys - tems which use the smartclock oscillator in crystal mode. the follow ing are rec ommended crystal spec - ifications and operating c ond iti ons when automatic gain control is enabled: ? esr < 50 k: ? load capacitance < 10 pf ? supply voltage < 3.0 v ? temperature > ?20 c when using automatic gain control, i t is recommended to perform an osc illation robustness test to ensure that the chosen crystal will oscillate under the worst case condition to which th e system will be exposed. the worst case condition that should result in the least robust oscilla tion is at the following system condi - tions: lowest temperature, highest sup p ly voltage, highest esr, highest load capacitance, and lowest bias current (agc enabled, bias double disabled). to perform the oscillation robustness test, the smartc lock oscillator should be enabled and selected as the system clock source. next, the sysclk signal should be routed to a po rt pin configured as a push-pull digital output. the positive duty cycle of the output clock can be used as an indi cator of oscillation robust - table 24.2. smartclock load capacitance settings loadcap crystal load capacitance equivalent capacitance seen on xtal3 and xtal4 0000 4.0 pf 8.0 pf 0001 4.5 pf 9.0 pf 0010 5.0 pf 10.0 pf 0011 5.5 pf 11.0 pf 0100 6.0 pf 12.0 pf 0101 6.5 pf 13.0 pf 0110 7.0 pf 14.0 pf 0111 7.5 pf 15.0 pf 1000 8.0 pf 16.0 pf 1001 8.5 pf 17.0 pf 1010 9.0 pf 18.0 pf 1011 9.5 pf 19.0 pf 1100 10.5 pf 21.0 pf 1101 11.5 pf 23.0 pf 1110 12.5 pf 25.0 pf 1111 13.5 pf 27.0 pf
si102x/3x 310 rev. 0.3 ness. as shown in figure 24.2 , duty cycles less than tb d% indicate a robust oscillation. as the duty cycle approaches tbd%, oscillation becomes less reliable and the ris k of clock failure increases. increasing the bias current (by disabling agc) will always improv e oscillation robustness a nd will reduce the output clock?s duty cycle. this test should be performed at th e worst case system conditions, as results at very low temperatures or high supply voltage will vary from results taken at room temperature or low supply voltage. figure 24.2. interpreting oscillation robustness (duty cycle) test results as an alternative to performing the oscilla tion robustness test, automatic ga in control may be disabled at the cost of increased power consumption (approximately 200 na). disabling automatic gain control will provide the cry s tal oscillator with higher immunity against exte rnal factors which may lead to clock failure. automatic gain control must be di sabled if using the smartclock os cillator in self-oscillate mode. ta b l e 24.3 shows a summary of the oscillator bias settings . the smar tc lock bias doubling feature allows the self-oscillation frequency to be inc r eased (alm ost doubled) and allo ws a higher crystal drive strength in crystal mode. high crystal drive strength is recommend ed when the crystal is exposed to poor environmen - tal conditions such as excessive moisture. smar tc l ock bias doubling is en abled by setting biasx2 (rtc0xcn.5) to 1. . table 24.3. smartclock bias settings mode setting power consump tion crystal bias double off, agc on lowest bias double off, agc off low bias double on, agc on high bias double on, agc off highest self-oscillate bias double off low bias double on high duty cycle 25% tbd% tbd% safe operating zone low risk of clock failure high risk of clock failure
rev. 0.3 311 si102x/3x 24.2.6. missing sm artclock detector the missing smartclock detector is a one-shot circ uit enabled by setting mc lken (rtc0cn.6) to 1. when the smartclock missing clock detector is enabled, oscfail (rtc 0cn.5) is set by hardware if smartclock oscillator remains high or low for more than 100 s. a smartclock missing clock detector timeout can trigger an interrupt, wake the device from a low power mo de , or reset the device. see section ?17. interrupt handler? on page 238 , section ?19. power manage - ment? on page 264 , and section ?22. reset sources? on page 285 for more information. note: the smartclock missing clock detector should be disabled when making changes to the oscillator settings in rtc0xcn. 24.2.7. smartclock oscillat or crystal valid detector the smartclock oscillator crystal valid detector is an os cillation amplit ude detector circuit used during crystal startup to dete rmine when oscillation has started and is ne arly stable. the output of this detector can be read from the clkvld bit (rtx0xcn.4). notes: 1. the clkvld bit has a blanking interval of 2 ms. during the first 2 ms after turning on the crystal oscillator, the output of clkvld is not valid. 2. th is smartclock crystal valid detector (clkvld) is n ot intended for detecting an oscillator failure. the missing smartclock detector (clkfail) should be used for this purpose. 3. the clkvld bit output is driven low when biasx2 is disabled. 24.3. smartclock time r and alarm function the smartclock timer is a 32-bit counter that, when running (rtc0tr = 1), is incremented every smartclock oscillator cycle. the timer has an alarm f unction that can be set to generate an interrupt, wake the device from a low power mode, or reset the device at a specific time. see section ?17. interrupt handler? on page 238 , section ?19. power management? on page 264 , and section ?22. reset sources? on page 285 for more information. the smartclock timer includes an auto reset feature, which autom atically resets the timer to zero one smartclock cycle after the alarm 0 signal is deasse rted. when using auto reset, the alarm match value should always be set to 2 counts less than the desired match value. when using the lfo in combination with auto reset, the right-justified alarm match value should be set to 4 counts less than the desired match value. auto reset can be enabled by writing a 1 to alrm (rtc0cn.2). 24.3.1. setting and reading t h e smartclock timer value the 32-bit smartclock timer can be set or read using the six capturen internal registers. note that the timer does not need to be stopped before reading or setting its value. the following steps can be used to set the timer value: 1. write the desired 32-bit set value to the capturen registers. 2. w r ite 1 to rtc0set. this will tr ansfer the contents of the capt uren registers to the smartclock timer. 3. operation is complete when rtc0set is cleared to 0 by hardware. the following steps can be used to read the current timer value: 1. write 1 to rtc0cap. this will transfer the c ontent s of the timer to the capturen registers. 2. poll rtc0cap until it is cleared to 0 by hardware. 3. a snapshot of the timer value can be read from the capturen registers notes: 1. if the system clock is faster than 4x the smartclock, then the hsmode bi t should be set to allow the set and capture operations to be concluded qui ckly (system clock used for transfers). 2. if th e system clock is slower than 4x the smartclock, then hsmode should be set to zero, and rtc must be
si102x/3x 312 rev. 0.3 running (rtc0tr = 1) in order to set or capture the ma in timer. the transfer can take up to 2 smartclock cycles to complete. 24.3.2. setting a smartclock alarm the smartclock alarm function compares the 32-bit value of smartclock timer to the value of the alarmnbn registers. an al arm event is triggered if the smartclock timer is equal to the alarmnbn registers. if auto reset is enabled, the 32-bit timer will be cleared to zero one smartclock cycle after the alarm 0 event. the smartclock alarm event can be configured to reset the mcu, wake it up from a low power mode, or ge n erate an interrupt. see section ?17. interrupt hand ler? on p age 238 , section ?19. power management? on page 264 , and section ?22. reset sources? on page 285 for more information. the following steps can be used to set up a smartclock alarm: 1. disable smartclock alar m event s (rtc0aen = 0). 2. set the alarmn registers to the desired value. 3. enable smartclock alar m events (rtc0aen = 1). ? notes: 1. the alrm bit, which is used as the smartclock alarm ev ent fla g, is cleared by disabling smartclock alarm events (rtc0aen = 0). 2. if autorese t is disab led, disabling (rtc0aen = 0) then re-enabling alarm events (rtc0aen = 1) after a smartclock alarm without modifying alarmn registers w ill automatically schedule the next alarm after 2^32 smartclock cycles (approximately 36 hours using a 32.768 khz crystal). 24.3.3. software consider ations for using the smartclock timer and alarm the smartclock timer and alarm have two operating mode s to suit varying applications. the two modes are described below: mode 1: ? the first mode uses the smartclock timer as a perpet ual tim eba se which is never reset to zero. every 36 hours, the timer is allowed to overflow without being stopped or disrupted. the alarm interval is software managed and is added to the alrmnbn registers by so ftware after each alarm. this allows the alarm match value to always stay ahead of the timer by one software managed interval. if software uses 32-bit unsigned addition to increment the alarm match value, then it does not need to handle overflows since both the timer and the alarm match va lue will overflow in the same manner. this mode is ideal for applications which have a long alarm interval (e.g., 24 or 36 hours) and/or have a n eed for a perpetual timebase. an example of an application that needs a perpetual timebase is one whose wake-up interval is constant ly changing. for these applications, software can keep track of the number of timer overflows in a 16-bit variable, extendi ng the 32-bit (36 hour) timer to a 48-bit (272 year) perpetual timebase. mode 2: ? the second mode uses the smartclock timer as a general pu rp ose up counter which is auto reset to zero by hardware after each alarm 0 event. the alarm interval is managed by hardware and stored in the alrm0bn registers. software only needs to set the alarm interval once during device initialization. after each alarm 0 event, software should keep a count of the number of alarms that have occurred in order to keep track of time. alarm 1 and alarm 2 events do not trigger the auto reset. this mode is ideal for applications th at require minimal software intervention and/or have a fixed alarm interval. this mode is the most power effici ent since it requires less cpu time per alarm.
rev. 0.3 313 si102x/3x smartclock address = 0x04 internal register definition 24.4. rtc0cn: smartclock control bit 7 6 5 4 3 2 1 0 name rtc0en mclken oscfail rtc0tr hsmode rtc0set rtc0cap type r/w r/w r/w r/w r/w r/w r/w r/w reset 00varies00000 bit name function 7 rtc0en smartclock enable. enables/disables the smartclock osc illator and associat ed bias current s. 0: smar tclock oscillator disabled. 1: smartclock oscillator enabled. 6 mclken missing smartclock detector enable. enables/disables the missing smartclock detector. 0: missing smartclock detector disabled. 1: missing smartclock detector enabled. 5 oscfail smartclock oscillator fail event flag. set by hardware when a missing smartclock detector timeout occurs. must be clea re d by software. the value of this bit is not defined when the smartclock ? oscillator is disabled. 4 rtc0tr smartclock timer run control. controls if the smartclock timer is running or stopped (holds current value). 0: smartclock timer is stopped. 1: smartclock timer is running. 3 reserved read = 0b; must write 0b. 2 hsmode high speed mode enable. should be set to 1 if the system clock is faster than 4x the smartclock frequency. 0: high speed mode is disabled. 1: high speed mode is enabled. 1 rtc0set smartclock timer set. writing 1 initiates a smartclock timer set oper atio n. this bit is cleared to 0 by hard - ware to indicate that the ti me r set operation is complete. 0 rtc0cap smartclock timer capture. writing 1 initiates a smartclock timer capture op er ation. this bit is cleared to 0 by hardware to indicate that the timer capture operation is complete.
si102x/3x 314 rev. 0.3 smartclock address = 0x05 internal register definition 24.5. rtc0xcn: smartclock oscillator control bit 7 6 5 4 3 2 1 0 name agcen xmode biasx2 clkvld lfoen type r/w r/w r/w r r/w r r r reset 00000000 bit name function 7 agcen smartclock oscillator automatic gain control (agc) enable. 0: agc disabled. 1: agc enabled. 6 xmode smartclock oscillator mode. selects crystal or self oscillate mode. 0: self-oscillate mode selected. 1: crystal mode selected. 5 biasx2 smartclock oscillator b i as double enable. enables/disables the bia s do uble feature. 0: bias double disabled. 1: bias double enabled. 4 clkvld smartclock oscillator crystal valid indicator. indicates if oscillation amplitude is sufficie nt for maint aining osc illation. this bit always reads 0 when biasx2 is disabled. 0: oscillation has not s t arted or oscillation amplitude is too low to maintain oscillation. 1: sufficient oscillati on amplitude detected. 3 lfoen lo w frequency oscillator enable and select. overrides xmode and selects the internal low frequenc y oscillator (lfo) as the smartclock osc illator source. 0: xmode determines smartclock oscillator source. 1: lfo enabled and selected as s m artclock oscillator source. 2:0 unused read = 000b; write = don?t care.
rev. 0.3 315 si102x/3x smartclock address = 0x06 internal register definition 24.6. rtc0xcf: smartclock osc illator configuration bit 7 6 5 4 3 2 1 0 name autostp loadrdy loadcap type r/w r r r r/w reset 0 0 0 0 varies varies varies varies bit name function 7 autostp automatic load capacitance stepping enable. enables/disables automatic load capacitance stepping. 0: load capacitance stepping disabled. 1: load capacitance stepping enabled. 6 loadrdy load capacitance ready indicator. set by hardware when the load capacitance matches the programmed value. 0: load capacitance is currently stepping. 1: load capacitance has reached it programmed value. 5:4 unused read = 00b; write = don?t care. 3:0 loadcap load capacitance programmed value. holds the user?s desired value of the load capacitance. see ta b l e 24.2 on page 309 .
si102x/3x 316 rev. 0.3 smartclock address = 0x07 internal register definition 24.7. rtc0cf: smartclock configuration bit 7 6 5 4 3 2 1 0 name alrm2 alrm1 alrm0 autorst rtc2en rtc1en rtc0en type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 reserved read = 0b; must write 0b. 6 alrm2 event flag for alarm 2. this bit must be cleared by software. writing a ?1? to this bit has no effect. 0: an alarm 2 event has not occured since the last time the flag was cleared. 1: an alarm 2 event has occured. 5 alrm1 event flag for alarm 1. this bit must be cleared by software. writing a ?1? to this bit has no effect. 0: an alarm 1 event has not occured since the last time the flag was cleared. 1: an alarm 1 event has occured. 4 alrm0 event flag for alarm 0. this bit must be cleared by software. writing a ?1? to this bit has no effect. 0: an alarm 0 event has not occured since the last time the flag was cleared. 1: an alarm 0 event has occured. 3 autorst auto reset enable. enables the auto reset function to clear th e co un ter when an alarm 0 event occurs. 0: auto reset is disabled 1: auto reset is enabled. 2 alrm2en alarm 2 enable. 0: alarm 2 is disabled. 1: alarm 2 is enabled. 1 alrm1en alarm 1 enable. 0: alarm 1 is disabled. 1: alarm 1 is enabled. 0 alrm0en alarm 0 enable. 0: alarm 0 is disabled. 1: alarm 0 is enabled.
rev. 0.3 317 si102x/3x smartclock addresses: capture0 = 0x00; capture1 = 0x01; capture2 =0x02; capture3: 0x03. smartclock address: alarm0b0 = 0x08; alarm0b1 = 0x09; alarm0b2 = 0x0a; alarm0b3 = 0x0b internal register definition 24.8. capturen: smartclock timer capture bit 7 6 5 4 3 2 1 0 name capture[31:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 capture[31:0] smartclock timer capture. these 4 registers (capture3?capture0) are used to read or set the 32-bit smartc lock timer. data is transferred to or from the smartclock timer when the rtc0set or rtc0cap bits are set. note: the least significant bit of the timer capture value is capture0.0. internal register definition 24.9. alarm0bn: smartclock alarm 0 ma tch value bit 7 6 5 4 3 2 1 0 name alarm0[31:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 alarm0[31:0] smartclock alarm 0 programmed value. these 4 registers (alarm0b3?alarm0b0) are used to set an alarm event for the smartclock timer. the smartclock alarm should be disabled (alrm0en=0) when updating these registers. note: the least significant bit of the alarm programmed value is alarm0b0.0.
si102x/3x 318 rev. 0.3 smartclock address: alarm1b0 = 0x0c; alarm1b1 = 0x0d; alar m1b2 = 0x0e; alarm1b3 = 0x0f smartclock address: alarm2b0 = 0x10; alarm2b1 = 0x11; alarm2b2 = 0x12; alarm2b3 = 0x13 internal register definition 24.10. alarm1bn: smartclock alarm 1 match value bit 7 6 5 4 3 2 1 0 name alarm1[31:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 alarm1[31:0] smartclock alarm 1 programmed value. these 4 registers (alarm1b3?alarm1b0) are used to set an alarm event for the smartclock timer. the smartclock alarm should be disabled (alrm1en=0) when updating these registers. note: the least significant bit of the al arm programmed value is ialarm1b0.0. internal register definition 24.11. alarm2bn: smartclock alarm 2 match value bit 7 6 5 4 3 2 1 0 name alarm2[31:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 alarm2[31:0] smartclock alarm 2 programmed value. these 4 registers (alarm2b3?alarm2b0) are used to set an alarm event for the smartclock timer. the smartclock alarm should be disabled (alrm2en=0) when updating these registers. note: the least significant bit of the alarm programmed value is alarm2b0.0.
rev. 0.3 319 si102x/3x 25. low-power pulse counter the si102x/3x family of microcontrollers contains a low-power pulse counter module with advanced fea - tures, such as ultra low power input comparators with pr og rammable thresholds, a wide range of pull up values with a self calibration engine, asymmetrical integrators for low pa ss filtering and switch debounce, single, dual, and quadrature modes of operation, two 24-bit counters, and a variety of interrupt and sleep wake-up capabilities. this combination of featur es provides water, gas, and heat metering system design - ers with an optimal tool for saving power while collecting meter usage data. figure 25.1. pulse counter block diagram the low-power pulse counter is a low-power sleep-mode peripheral designed primarily to work meters using reed switches, including water and gas meters. the pulse counter is very flexible and can count pulses from many different types of sources. the pulse counter operates in sleep mode to enable ultra-low power metering systems. the mcu does not h a ve to wake up on every edge or transition and can remain in sleep mode while the pulse counter counts pulses for an extended period of time. the pulse count er includes two 24-bit counters. these counters can count up to 16,777,215 (2 24 -1) transitions in sleep mode before overflowing. the pulse counter can wake up the mcu when one of the counters overflows. th e pulse counter also has two 24-bit digital compara - tors. the comparators have the ability to wake up the mcu when th e one of the counte rs reaches a prede - termined count. the pulse counter uses the rtc clock for sampling, de-bouncing, and managing the low-power pull-up r e sistors. the rtc must be enabled when counting pulses. the rtc alarms can wake up the mcu peri - odically to read the pulse counters instead of using the pulse counter digital comparators. for example, the r tc can wake up the mcu every five minutes. the mc u can then read the pulse counter and transmit the information using the uart or a wireless transceiver. pc0 pc1 pc0ctr0h:m:l pc0ctr1h:m:l comparator 0 comparator 1 24 24 vbat pc0md pc0pcf debounce debounce pc0th pc0dch pc0dcl counter 0 counter 1 pc0cmp1h:m:l pc0cmp0h:m:l logic pc0int0
si102x/3x 320 rev. 0.3 25.1. counting modes the pulse counter supports three different counting modes: single counter mode, dual counter mode, and quadrature counter mode. figure 25.2 illustrates the th ree c o unter modes. figure 25.2. mode examples the single counter mode uses only one pulse counter pin pc0 (p1.0) to count pulses from a single input channel. this mode uses only counter 0 and compar ator 0. (counter 1 and comparator 1 are not used.) the single counter mode supports only one meter-en coder with a single-channel output. a single-channel encoder is an effective solution when the metered fluid flows only in one direction. a single-channel encoder does not provide any direction information and does not support bidi rectional fluid metering. the dual counter mode supports two independent sing le -c hannel meters. each meter has its own indepen - dent counter and comparator. some of the global configu r ation settings apply to both channels, such as pull-up current, sampling rate, and debounce time. the dual mode may also be used for a redundant count using a two-channel non-quadrature encoder. quadrature counter mode supports a single two-channel quadrature meter encoder. the quadrature coun - ter mode supports bidirectional encoders and applicatio n s with bidirectional fluid flow. in quadrature coun - ter mode, clockwise counts will increment counter 0, while counterclockwis e coun ts will increment counter 1. subtracting counter 1 from counter 0 will yield the net position. if the normal fluid flow is clockwise, then quadrature counter mode example pc1 pc0 clockwise counter-clockwise clockwise single counter mode example pc0 dual counter mode example pc1 pc0
rev. 0.3 321 si102x/3x the counterclockwise counter 1 value represents the cumulative backflow. firmware may use the backflow counter with the corresponding comparator to implement a backflow alarm. the clockwise sequence is (ll-hl-hh-lh), and the counterclockwise sequence is (ll-lh-hh-hl). (for this sequence lh means pc1 = low and pc0 = high.) firmware cannot write to the counters. the counter s are reset when pc0md is written and have their counting enabled when the pc0md[7: 6] mode bits are set to either single, dual, or quadrature modes. the counters only incr ement and will roll over to 0x000000 after reaching 0xffffff. for single mode, the pc0 input connects to counter 0. in dual mode, the pc0 input connects to counter 0 while the pc1 input con - nects to counter 1. in quadrature mode, clockwise co unt s are sent to counter 0 while counterclockwise counts are sent to counter 1. 25.2. reed switch types the pulse counter works with both form-a and form-c reed switches. a form-a switch is a normally- open single-pole single-throw (no spst) switch. a form-c re ed switch is a sing le-pole double-throw (spdt) switch. figure 25.3 illustrates some of the common reed swit ch c onfigurations for a single-channel meter. the form-a switch requires a pull-up resistor. the ene rg y used by the pull-up resistor may be a substantial portion of the energy budget. to minimize energy usage, the pulse counter has a programmable pull-up resistance and an automatic calibration engine. the calibration engine can automatically determine the smallest usable pull-up stre ngth setting. a form-c switch does no t require a pull-up resistor and will pro - vide a lower power solution. however, the form-c sw itche s are more expensive and require an additional wire for vbat. figure 25.3. reed switch configurations form a pc0 form c pc0 vbat vbat pull-up required no pull-up
si102x/3x 322 rev. 0.3 25.3. programmable pull-up resistors the pulse counter features low-power pull-up resistor s with a programmable resistance and duty-cycle. the average pull-up current will depend on the selected resistor, sample rate, and pull-up duty-cycle multi - plier. example code is available th at will calculate the values for the pull-up configurat ion sfr (pc0pcf). ta b l e 25.1 through ta b l e 25.3 are used with equation 25.1 to calculate the average pull-up resistor current. ta b l e 25.4 through ta b l e 25.7 give the average current for all combinations. equation 25.1. average pull-up current where: i r = pull-up resistor current selected by pc0pcf[4:2]. d sr = sample rate duty cycle mult iplier selected by pc0md[5:4]. d pu = pull-up duty cycle multip lier selected by pc0pcf[4:2]. table 25.1. pull-up resistor current table 25.2. sample rate duty-cycle multiplier table 25.3. pull-up duty-cycle multiplier pc0pcf[4:2] i r 000 0 001 1 ? a 010 4 ? a 011 16 ? a 100 64 ? a 101 256 ? a 110 1 ma 111 4 ma pc0md[5:4] d sr 00 1 01 1/2 10 1/4 11 1/8 pc0pcf[1:0] d pu 00 1/4 01 3/8 10 1/2 11 3/4 i pull-up i r d sr ? d pu ? =
rev. 0.3 323 si102x/3x table 25.4. average pull-up current (sample rate = 250 s) pc0pcf[4:2] duty cycle pc0pcf[1:0] 000 001 010 011 100 101 110 111 00 disabled 250 na 1.0 a 4.0 a 16 a 64 a 250 a 1000 a 25% 01 disabled 375 na 1.5 a 6.0 a 24 a 96 a 375 a 1500 a 37.5% 10 disabled 500 na 2.0 a 8.0 a 32 a 128 a 500 a 2000 a 50% 11 disabled 750 na 3.0 a 12.0 a 48 a 192 a 750 a 3000 a 75% table 25.5. average pull-up current (sample rate = 500 s) pc0pcf[4:2] duty cycle pc0pcf[1:0] 000 001 010 011 100 101 110 111 00 disabled 125 na 0.50 a 2.0 a 8 a 32 a 125 a 500 a 12.5% 01 disabled 188 na 0.75 a 3.0 a 12 a 48 a 188 a 750 a 18.8% 10 disabled 250 na 1.0 a 4.0 a 16 a 64 a 250 a 1000 a 25% 11 disabled 375 na 1.5 a 6.0 a 24 a 96 a 375 a 1500 a 37.5% table 25.6. average pull-up current (sample rate = 1 ms) pc0pcf[4:2] duty cycle pc0pcf[1:0] 000 001 010 011 100 101 110 111 00 disabled 63 na 250 na 1.0 a 4 a 16 a 63 a 250 a 6.3% 01 disabled 94 na 375 na 1.5 a 6 a 24 a 94 a 375 a 9.4% 10 disabled 125 na 500 na 2.0 a 8 a 32 a 125 a 500 a 12.5% 11 disabled 188 na 750 na 3.0 a 12 a 48 a 188 a 750 a 18.8% table 25.7. average pull-up current (sample rate = 2 ms) pc0pcf[4:2] duty cycle pc0pcf[1:0] 000 001 010 011 100 101 110 111 00 disabled 31 na 125 na 0.50 a 2.0 a 8 a 31 a 125 a 3.1% 01 disabled 47 na 188 na 0.75 a 3.0 a 12 a 47 a 188 a 4.7% 10 disabled 63 na 250 na 1.0 a 4.0 a 16 a 63 a 250 a 6.3% 11 disabled 94 na 375 na 1.5 a 6.0 a 24 a 94 a 375 a 9.4%
si102x/3x 324 rev. 0.3 25.4. automatic pull-u p resistor calibration the pulse counter includes an automatic calibration engine which can automatically determine the mini - mum pull-up current for a particular application. the au t o matic calibration is especially useful when the load capacitance of field wiring varies from one installation to another. the automatic calibration uses one of the pulse counter inputs (pc0 or pc1) for calibration. the cal - port bit in the pc0pcf sfr selects either pc0 or pc1 for calibration. the reed switch on the selected in put sh ould be in the open state to allow the node to charge during calibration. the calibration engine can calibrate the pull-ups with the meter connected normally, provided that the reed switch is open during cali - bration. during calibration , the integrators will ignore the input co mparators, and the counters will not be incremented. using a 250 s sample rate and a 32 khz rtcclk, the calibration time will be 21 ms (28 tests @ 750 s each) or shorter de pending on the pull up strength selected. the calibration will fail if the reed switch remains closed during this entire period. if the reed switch is both opened and closed during the calibration period, the va lue written into pccf [4:0] may be larger than what is actually required. the transition flag in the pc0int1 can detect when th e reed switch opens, and most systems with a wheel rotation of 10 hz or slower should have sufficient high time for the calibration to complete before the next closing of the reed switch. slowing the sample rate will also increase t he calibration time . the same drive strength will used for both pc0 and pc1. the example code for the pulse co unter includ es code for managing the automatic calibration engine. 25.5. sample rate the pulse counter has a programmable sampling rate. the pulse counter samples the state of the reed switches at discrete time intervals based on the rtc clock. the pc0md sfr sets the sampling rate. the system designer should carefully consider the maximum pulse rate for the particular application when set - ting the sampling rate and debounce time. sample rates from 250 s to 2 ms can be selected to either fur - ther reduce power consum ption or work with shorter pulse wid ths. the slowest sampling rate (2 ms) will provide the lowest possible power consumption. 25.6. debounce like most mechanical switches, reed switches exhibit switch bouncing that could po tentially result in false counts or quadrature errors. the pulse counter include s digital debounce logic using a digital integrator that can eliminate false counts due to switch bounce. the input of the integrator connects to the pulse counter inputs with the programmable pull-ups. the output connects to the counters. the debounce integrator has two independent prog ra mmable thresholds: one for the rising edge (debounce high) and one for the falling edge (debounce low). the pc 0dch (pc0 debounce config high) sfr sets the threshold for the rising edge. this sfr sets the number of cumulative high samples required to output a logic high to the counter. the pc0dcl (pc0 debounce config low) sfr sets the threshold for the falling edge. this sfr sets the number of cumula tive low samples required to output a logic low to the counter. note that the debounce does count co nsecutive samp les. requiring consecutive samples would be sus - ceptible to noise. the digital integrator inherently filters out noise. the system designer should carefully consider the maximu m a nticipated counte r frequency and duty-cycle when setting the debounce time. if the debounce configuration is set too large, the pu lse counter will not count short pulses. the debounce-high configuration should be set to less than one-half the minimum input pulse high-time. similarly, the debounce-low c onfiguration should be set to less than one-half the minimum input pulse low-time. figure 25.4 illustrates the operation of the debounc e integrat or. the top waveform is the representation of the reed switch (high: open, low: closed) which shows so me r andom switch bounce. the bottom waveform is the final signal that goes into the counter which has the switch bounce removed. based on the actual reed switch used and sample rate, the switch bounce time may appear shorter in duration than the exam - ple in figure 25.4 . the second waveform is the pull-up resistor enable signal. the enable signal enables
rev. 0.3 325 si102x/3x the pull-up resistor when high and disables when low. pc0 is the line to the reed switch. on the right side of pc0 waveform, the line voltage is decreasing towa rds ground when the pull-up resistors are disabled. beneath the charging waveform, the arrows represent the sample points. the pulse counter samples the pc0 voltage once the charging completes. the sensed ones and zeros are the sampled data. finally the integrator wavefo rm illustrates the output of the digital integrat or. the integrator is set to 4 initially and counts to down to 0 before toggling the output low. once the integrator reaches the low state, it needs to count up to 4 before toggling its output to the high state. the debounce logic filters out switch bounce or noise that appears for a short duration. figure 25.4. debounce timing 25.7. reset behavior unlike most mcu peripherals, an mcu reset does not completely reset the pulse counter. this includes a power on reset and all other reset so urces. an mcu reset does not clear the counter values. the pulse counter sfrs do not reset to a default value upon re set. the 24-bit counter values are persistent unless cleared manually by writing to the pc0md sfr. note that if the vbat voltage ever drops below the mini - mum operating voltage, this may comp ro mise co ntents of the counters. the pc0md register should normally be written only once af ter reset. the pc0md sfr is the master mode register. this register sets the counter mode and sample rate. writing to the pc0md sfr also resets the other pc0xxx sfrs. note that the rtc clock will reset on an mcu reset, s o counting ca nnot resume until the rtc clock has been re-started. firmware should read the reset sources sfr rstsrc to de te rmine the source of th e last reset and initial - ize the pulse counter accordingly. when the pulse counter resets, it takes some time (t ypically two r tc clock cycl es) to synchronize between internal clock domains. the counters do not increment during this synchronization time. 25.8. wake up and interrupt sources the pulse counter has multiple interrupt and wake-up source conditions. to enable an interrupt, enable the source in the pc0int0/1 sfrs and enable the pulse coun ter interrupt using bit 4 of the eie2 register. the pulse counter interrupt service routine should read the interrupt flags in pc0int0/1 to determine the source of the interrupt and clear the interrupt flags. sensed 1 1 0 1 1 0 0 0 0 1 0 1 1 1 1 switch charging integrator output debounce debounce pc0 integrator (set to 4) integrator 4 4 3 4 4 3 2 1 0 1 0 1 2 3 4 samples
si102x/3x 326 rev. 0.3 to enable the pulse counter as a wake up source, enable the source in the pc0int0/1 sfrs and enable the pulse counter as a wake-up source by setting bit 0 (pc0wk) to 1 in the pmu0fl sfr. upon waking, firmware should read the pmcu0cf and pmu0fl sfrs to determine the wake-up source. if the pc0wk bit is set indicating that the pulse counter has woke th e mcu, firmware should read the flag bits pc0int0/1 sfrs to determine the pulse counter wake-up source and clear the flag bits before going back to sleep. pc0int0 includes the more common interrupt and wake -up sources. these include comparator match, counter overflow, and quadrature direction change. pc0int1 includes interrupt and wake-up sources for the advanced features, including flutter detection and quadrature error. 25.9. real-tim e register access several of the pulse counter registers values change in real-time synchronous to the rtc clock. hardware synchronization between the rtc clock domain and t he system clock domain ha rdware would result in long delays when reading real-time regi sters. instead, real-time regist er values are available instanta - neously, but the read must be qualified using the read valid bit (pc0th bit 0). if the register value does not change during the read access, the read valid bit will be set indicating the last was valid. if the value of the real-time register changes during the read access, the re ad valid bit is 0, indica ting the read was invalid. after an invalid read, firmware must read the register and check the read valid bit again. these 8-bit counter registers need to be qualified using the read valid bit: ? pc0stat ? pc0hist ? pc0int0 ? pc0int1 ? pc0ctr0l ? pc0ctc1l the 24-bit counters are three-byte real-time read-only reg isters that require a special access method for reading. firmware must read the low-byte (pc0ctr0l and pc0ctr1l) first and qualify using the read valid bit. reading the low-byte latches the middle and high bytes. if the read valid bit is 0, the read is invalid and firmware must read the low-byte and check the read va lid bit again. if the read valid bit is set, the read is valid and the middle and high bytes are also safe to read. firmware should read the middle and high bytes only after reading the low byte and qualifying with the read valid bit. the 24-bit compators are three-byte real-time read-writ e r e gisters that require a special access method for writing. firmware must write the low- byte last. after writing the low-byte, it might take up to two rtc clock cycles for the new comparator value to take effect. system designers should consider the synchronization delay when setting the comparator value. the counter may be incremented before new comparator value takes effect. setting the comparator to at least 2 counts ab ove the current count w ill eliminate the chance of missing the comparator match during synchronization. example code is provided with accessor function s for all the real-time pulse counter registers. 25.10. advanced features 25.10.1. quadrature error the quadrature encoder must only send valid quadratur e codes. a valid quadrature sequence consists of four valid states. the quadrature codes are only permitted to transition to one of the adjacent states, and an invalid transition will result in a quadrature error. note that a quadrature error is lik ely to occur when first enabling the quadrature counter mode, since the pulse counter state machine starts at the ll state and the initial state of the quadrature is arbitrary. it is safe to ignore the first quadrature error immediately after ini - tialization.
rev. 0.3 327 si102x/3x 25.10.2. flutter detection t he flutter detection can be used with either quadratu re counter mode or dual counter mode when the two inputs are expected to be in step. flutter refers to the case where one input c ontinues toggling while the other input stops toggling. this may indicate a broken reed switch or a pressure oscillation when the wheel magnet stops at just the right distance from the reed switch. if a pressure oscilla tion causes a slight rota - tional oscillation in the wheel, it could cause a number of pulses on one of the inputs, but not on the other. all four edges are checked by the flutter detection fe ature (pc1 positive, pc1 negative, pc0 positive, and pc0 negative).when enabled, flu tter detection may be used as an interrupt or wake-up source. figure 25.5. flutter example for example, flutter detected on th e pc0 positive edge means that 4 e dges (positive or negative) were detected on pc1 since the last pc0 positive edge. ea ch pc0 positive edge resets the flutter detection counter while either pc1 edge increments the counte r. there are similar counters for all four edges. the flutter detection circuit provides inter r upts or wake-up sources, but firmware must also read the pulse counter registers to determine what corrective action, if any, must be taken. on the start of flutter event, the firmware should sa ve both counter value s and the pc0hist register. once the end of flutter event occurs the firmware should also save both counter values and the pc0hist regis - ter. the stop count on flutter, stpcntfltr (pcmd[2]), be u s ed to stop the counters when flutter is occur - ring (quadrature mode only). for quadrature mode, the opp osite counter should be decremented by one. in other words, if the di rection was clockwise, the counterclockw ise counter (counter 1) should be decre - mented by one to correct for one increment before flutter was de tected. for dual mode, two reed switches can be used to get a redundant count. if flutter starts during dual mode, both counters should be saved by firmware. after flutter stops, both counters should be read again. the counter that incremented the most was the one that picked up the flutter. there is also a mode to switch from quadrature to dual (pc0md[1]) when flutter occurs. this changes the counter style from quadrature (count on any edge of pc1 or pc0) to dual to allow all counts to be recorded. once flutter ends, this mode switches th e counters back to quadra - ture mode. stpcntfltr does not function when pc0md[1] is set. pc1 pc0 next expected pulse next expected pulse with direction change flutter detected 0+1 +2 +3 +4
si102x/3x 328 rev. 0.3 sfr address = 0xd9; sfr page = 0x2 note that writin g to this register will clea r the counter registers pc0c tr0h:m:l and pc0ctr1h:m:l. sfr definition 25.1. pc0md: pc0 mode configuration bit 7 6 5 4 3 2 1 0 name pcmode[1:0] pcrate[1:0] dualcmpl stpcntfltr dualstch type r/w r/w r/w r r/w r reset 0 0 0 0 0 1 0 0 bit name function 7:6 pcmode[1:0] counter mode 00: pulse counter disabled. 01: single counter mode. 10: dual counter mode. 11: quadrature counter mode. 5:4 pcrate[1:0] pc sample rate 00: 250 s 01: 500 s 10: 1 ms 11: 2 ms 3 reserved 2 stpcntfltr stop counting on flutter (only valid for quadrature counter mode and dualstch off.) 0: disabled. 1: enabled. 1 dualstch dual mode switch during flutter (only valid for quadrature counter mode.) 0: disabled?quadrature mode remains set during flutter. 1: enabled?quadrature mode changes to dual during flutter. 0 reserved
rev. 0.3 329 si102x/3x sfr address = 0xd7; sfr page = 0x2 sfr definition 25.2. pc0pcf: pc0 mode pull-up configuration bit 7 6 5 4 3 2 1 0 name pucal calres calport res[2:0] duty[1:0] type r/w r r/w r/w r/w r/w r/w r/w reset 0 1 0 0 0 1 0 0 bit name function 7 pucal pull-up driver calibration 0: calibration complete or not running. 1: start calibration of pull up (self clearing). ? calibration determi nes th e lowest usable pull-up strength. 6 calres calibration result 0: fail (switch may be closed pr eventing detection of pull ups). ? writes value of 0x11111 to pc0pcf[4:0] 1: pass (writes calibrated value into pc0pcf[4:0]). 5 calport calibration port 0: calibration on pc0 only. 1: calibration on pc1 only. 4:2 res[2:0] pull-up resistor select current with force pull-up on bit set (pc0th.2=1) and vbat=3.6v. 000: pull-up disabled. 001: 1 ? a.* 010: 4 ? a.* 011: 16 ? a.* 100: 64 ? a.* 101: 256 ? a.* 110: 1 ma.* 111: 4 ma.* *the effective average pull-up current depends on selected resistor, pull-up r e sistor duty-cycle multiplier, and sample rate duty-cycle multiplier. 1:0 duty[1:0] pull-up resistor duty cycle multiplier 000: 1/4 (25%)* 001: 3/8 (37.5%)* 010: 1/2 (50%)* 011: 3/4 (75%)* *the final pull-up resistor duty cycle is the sample rate duty-c ycle multiplier times the pull-up duty-cycle multiplier.
si102x/3x 330 rev. 0.3 sfr address = 0xe4; sfr page = 0x2 sfr definition 25.3. pc0th: pc0 thres hold configuration bit 7 6 5 4 3 2 1 0 name pctthreshi[1:0] pcthreslo [1:0] pdown pup rdvalid type r/w r/w r/w r/w r r/w reset 0 0 0 0 0 0 0 1 bit name function 7:6 pctthreshi[1:0] pulse counter input comparator vih threshold (percentage of vio.) 10: 50% 11: 55% 00: 59% 01: 63% 5:4 pcthreslo [1:0] pulse counter input comparator vil threshold (percentage of vio.) 10: 34% 11: 38% 00: 42% 01: 46% 3 pdown force pull-down on 0: pc0 and pc1 pull-down not forced on. 1: pc0 and pc1 grounded. 2 pup force pull-up 0: pc0 and pc1 pull-up not forced on continuously. see pc0pcf[1:0] for duty cyc le. 1 : pc0 and pc1 pulled high continuo usly to the pc0pcf[4:2] s etting. pdown overrides pup setting. 1 reserved 0 rdvalid read valid holds the status of the last read for real-time registers pc0stat, pc0hist, pc0ctr0l , pc0ctr1l , pc 0int0, and pc0int1. 0: the last read was invalid. 1: the last read was valid. rdvalid is set back to 1 upon reading.
rev. 0.3 331 si102x/3x sfr address = 0xc1; sfr page = 0x2 sfr definition 25.4. pc0stat: pc0 status bit 7 6 5 4 3 2 1 0 name flutter direction state[1:0] pc1prev pc0prev pc1 pc0 type ro ro ro ro ro ro ro reset 0 0 0 0 0 0 0 0 bit name function 7 flutter flutter during quadrature mode, a disparity may occur between the number of neg - ative edges of pc1 and pc0 or the nu mber of positive edges of pc1 and pc0. this could indicate flutter on on e reed switch or one reed switch may be faulty. 0: no flutter detected. 1: flutter detected. 6 direction direction only applicable for quadrature mode. (first letter is pc1; second letter is pc0) 0: counter clock-wise - (ll-lh-hh-hl) 1: clock-wise - (ll-hl-hh-lh) 5:4 state[1:0] pc0 state current state of internal state machine. 3 pc1prev pc1 previous previous output of pc1 integrator. 2 pc0prev pc0 previous previous output of pc0 integrator. 1 pc1 pc1 current output of pc1 integrator. 0 pc0 pc0 current output of pc0 integrator.
si102x/3x 332 rev. 0.3 sfr address = 0xfa; sfr page = 0x2 sfr definition 25.5. pc0dch: pc0 debounce configuration high bit 7 6 5 4 3 2 1 0 name pc0dch[7:0] type r/w reset 0 0 0 0 0 1 0 0 bit name function 7:0 pc0dch[7:0] pulse counter debounce high number of cumulative good samples seen by the integrator before recogniz - ing the input as high. sampling a lo w will decrement the count while sam - pling a high will increment the count. th e ac tual value us ed is pc0dch plus one. switch bounce produces a random looking signal. the worst case would be to bounce low at each sample point and not start incrementing the integrator until the switch bounce sett led. therefore, minimum pulse width should account for twice the debounce time. for example, using a sample rate of 250 s and a pc0dch value of 0x13 w ill look for 20 cumulative highs before recognizing the input as high (250 s x (16+3+1) = 5 ms).
rev. 0.3 333 si102x/3x sfr address = 0xf9; sfr page = 0x2 sfr definition 25.6. pc0dcl: pc0 debounce configuration low bit 7 6 5 4 3 2 1 0 name pc0dcl[7:0] type r/w reset 0 0 0 0 0 1 0 0 bit name function 7:0 pc0dcl[7:0] pulse counter debounce low number of cumulative good samples seen by the integrator before recogniz - ing the input as low. setting pc0dcl to 0x 00 will dis able in tegrators on both pc0 and pc1. the actual value used is pc0dcl plus one. sampling a low decrements while sampling a high increments the count. switch bounce produces a random looking signal. the worst case would be to bounce high at each sample point and not start decrementing the integrator until the switch bounce settled. therefore, minimum pulse width should account for twice the debounce time. for example, using a sample rate of 1 ms and a pc0 dcl value of 0x09 will look for 10 cumulative lows before recognizing the input as low (1 ms x 10 = 10 ms). the minimum pulse width should be 20 ms or greater for this example. if pc0 d cl has a value of 0x03 and the sample rate is 500 s, the integrator would need to see 4 cumulative lows before rec o gnizing the low (500 s x 4 = 2 ms). the minimum pulse width sh ou ld be 4 ms for this example.
si102x/3x 334 rev. 0.3 sfr address = 0xdc; sfr page = 0x2 sfr address = 0xd8; sfr page = 0x2 sfr address = 0xda; sfr page = 0x2 note: pc0ctr0l must be read before pc0ctr0m and pc0ctr 0h to latch the count for reading. pc0ctrl must be qualified using the rdvalid bit (pc0th[0]). sfr definition 25.7. pc0ctr0h: pc0 counter 0 high (msb) bit 7 6 5 4 3 2 1 0 name pc0ctr0h[23:16] type r reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0ctr0h[23:16] pc0 counter 0 high byte bits 23:16 of counter 0. sfr definition 25.8. pc0ctr0m: pc0 c ounter 0 middle bit 7 6 5 4 3 2 1 0 name pc0ctr0m[15:8] type r reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0ctr0m[15:8] pc0 counter 0 middle byte bits 15:8 of counter 0. sfr definition 25.9. pc0ctr0l: pc0 counter 0 low (lsb) bit 7 6 5 4 3 2 1 0 name pc0ctr0l[7:0] type r reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0ctr0l[7:0] pc0 counter 0 low byte bits 7:0 of counter 0.
rev. 0.3 335 si102x/3x sfr address = 0xdf; sfr page = 0x2 sfr address = 0xde; sfr page = 0x2 sfr address = 0xdd; sfr page = 0x2 note: pc0ctr1l must be read before pc0ctr1m and pc0ctr1h to latch the count for reading. sfr definition 25.10. pc0ctr1h: pc0 count er 1 high (msb) bit 7 6 5 4 3 2 1 0 name pc0ctr1h[23:16] type r reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0ctr1h[23:16] pc0 counter 1 high byte bits 23:16 of counter 1. sfr definition 25.11. pc0ctr1m: pc0 counter 1 middle bit 7 6 5 4 3 2 1 0 name pc0ctr1m[15:8] type r reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0ctr1m[15:8] pc0 counter 1 middle byte bits 15:8 of counter 1. sfr definition 25.12. pc0ctr1l: pc0 count er 1 low (lsb) bit 7 6 5 4 3 2 1 0 name pc0ctr1l[7:0] type r reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0ctr1l[7:0] pc0 counter 1 low byte bits 7:0 of counter 1.
si102x/3x 336 rev. 0.3 sfr address = 0xe3; sfr page = 0x2 sfr address = 0xe2; sfr page = 0x2 sfr address = 0xe1; sfr page = 0x2 note: pc0cmp0l must be written last after writing pc 0cmp0m and pc0cmp0h. after writing pc0cmp0l, the synchronization into the pc clock dom ain can take 2 rt c clock cycles. sfr definition 25.13. pc0cmp0h: pc0 compar ator 0 high (msb) bit 7 6 5 4 3 2 1 0 name pc0cmp0h[23:16] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0cmp0h[23:16] pc0 comparator 0 high byte bits 23:16 of counter 0. sfr definition 25.14. pc0cmp0m: pc0 comparator 0 middle bit 7 6 5 4 3 2 1 0 name pc0cmp0m[15:8] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0cmp0m[15:8] pc0 comparator 0 middle byte bits 15:8 of counter 0. sfr definition 25.15. pc0cmp0l: pc0 compar ator 0 low (lsb) bit 7 6 5 4 3 2 1 0 name pc0cmp0l[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0cmp0l[7:0] pc0 comparator 0 low byte bits 7:0 of counter 0.
rev. 0.3 337 si102x/3x sfr address = 0xf3; sfr page = 0x2 sfr address = 0xf2; sfr page = 0x2 sfr address = 0xf1; sfr page = 0x2 note: pc0cmp1l must be written last after writing pc 0cmp1m and pc0cmp1h. after writing pc0cmp1l the synchronization into the pc clock dom ain can take 2 rt c clock cycles. sfr definition 25.16. pc0cmp1h: pc0 compar ator 1 high (msb) bit 7 6 5 4 3 2 1 0 name pc0cmp1h[23:16] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0cmp1h[23:16] pc0 comparator 1 high byte bits 23:16 of counter 0. sfr definition 25.17. pc0cmp1m: pc0 comparator 1 middle bit 7 6 5 4 3 2 1 0 name pc0cmp1m[15:8] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0cmp1m[15:8] pc0 comparator 1 middle byte bits 15:8 of counter 0. sfr definition 25.18. pc0cmp1l: pc0 compar ator 1 low (lsb) bit 7 6 5 4 3 2 1 0 name pc0cmp1l[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0cmp1l[7:0] pc0 comparator 1 low byte bits 7:0 of counter 0.
si102x/3x 338 rev. 0.3 sfr address = 0xf4; sfr page = 0x2 sfr definition 25.19. pc0hist: pc0 history bit 7 6 5 4 3 2 1 0 name pc0hist[7:0] type r reset 0 0 0 0 0 0 0 0 bit name function 7:0 pc0hist[7:0] pc0 history. contains the last 8 recorded directions (1 : clock-wise, 0: counter clock-wise) on the previous 8 counts. values of 0x55 or 0xaa may indicate flutter during quadrature mode.
rev. 0.3 339 si102x/3x sfr address = 0xfb; sfr page = 0x2 sfr definition 25.20. pc0int0: pc0 interrupt 0 bit 7 6 5 4 3 2 1 0 name cmp1f cmp1en cmp0f cmp0en ovrf ovren dirchgf dirchgen type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 cmp1f comparator 1 flag 0: counter 1 did not match comparator 1 value. 1: counter 1 matched comparator 1 value. 6 cmp1en comparator 1 interrupt/wake-up source enable 0:cmp1f not enabled as interrupt or wake-up source. 1:cmp1f enabled as interrupt or wake-up source. 5 cmp0f comparator 0 flag 0: counter 0 did not match comparator 0 value. 1: counter 0 matched comparator 0 value. 4 cmp0en comparator 0 interrupt/wake-up source enable 0:cmp0f not enabled as interrupt or wake-up source. 1:cmp0f enabled as interrupt or wake-up source. 3 ovrf counter overflow flag 1:neither of the counters has overflowed. 1:one of the counters has overflowed. 2 ovren counter overflow interrupt/wake-up source enable 0:ovrf not enabled as interrupt or wake-up source. 1:ovrf enabled as interrupt or wake-up source. 1 dirchgf direction change flag direction changed for quadrature mode only. 0:no change in direction detected. 1:direction change detected. 0 dirchgen direction change interrupt/wake-up source enable 0:dirchgf not enabled as interrupt or wake-up source. 1:dirchgf enabled as inte rr upt or wake-up source.
si102x/3x 340 rev. 0.3 sfr address = 0xfc; sfr page = 0x2 sfr definition 25.21. pc0int1: pc0 interrupt 1 bit 7 6 5 4 3 2 1 0 name fltrstrf fltrstren fltrstpf fltrstpen errorf erroren transf transen type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 fltrstrf flutter start flag flutter detection fo r qu adrature mode or dual mode only. 0: no flutter detected. 1: start of flutter detected. 6 fltrstren flutter start interrupt/w ak e-u p source enable 0:fltrstrf not enabled as interrupt or wake-up source. 1:fltrstrf enabled as interrupt or wake-up source. 5 fltrstpf flutter stop flag flutter detection fo r qu adrature mode or dual mode only. 0: no flutter stop detected. 1: flutter stop detected. 4 fltrstpen flutter stop interrupt/wake-up source enable 0:fltrstpf not enabled as interrupt or wake-up source. 1:fltrstpf enabled as interrupt or wake-up source. 3 errorf quadrature error flag 0: no quadrature error detected. 1: quadrature error detected. 2 erroren quadrature error interrupt/wake-up source enable 0:errorf not enabled as interrupt or wake-up source. 1:errorf enabled as interrupt or wake-up source. 1 transf transition flag 0: no transition detected. 1: transition detected on pc0 or pc1. 0 transen transition interrupt/wake-up source enable 0: transf not enabled as interrupt or wake-up source. 1: transf enabled as interrupt or wake-up source.
rev. 0.3 341 si102x/3x 26. lcd segment driver (si102x only) si102x devices contain an lcd segment driver and on-c hip bias generation that supports static, 2-mux, 3- mux and 4-mux lcds with 1/2 or 1/3 bias. the on-c hip charge pump with programmable output voltage allows software contrast control wh ich is independent of the supply voltage. lcd timing is derived from the smartclock oscillator to allow precise control over the refresh rate. the si102x uses special function registers (sfrs) to stor e the enabled/disabled state of individual lcd segments. all lcd waveforms are generated on-chip based on the contents of the lcd0dn registers. an lcd blinking function is also supported. a blo ck diagram of the lcd segment driver is shown in figure 26.1 . figure 26.1. lcd segment driver block diagram 26.1. configuring th e lcd segment driver the lcd segment driver supports multiple mux option s: static, 2-mux, 3-mux, and 4-mux mode. it also supports 1/2 and 1/3 bias options. the desired mux mode and bias is configured through the lcd0cn reg - ister. a divide value may also be applied to the smar tclo ck o utput before being used as the lcd0 clock source. the following procedure is recommended for using the lcd segment driver: 1. initialize the smartclock and configure the lcd clo c k divide settings in the lcd0cn register. 2. determine the gpio pins which will be used for the lcd function. 3. configure the port i/o pins to be used for lcd as analog i/o. 4. configure the lcd size, mux mode, and bias using the lcd0cn register. 5. enable the lcd bias and clock gate by writing 0x50 to the lcd0mscn register. 6. configure the device for the desired contrast control mode. 7. if vio is internally or extern ally shorted to vbat, disable the vlcd/vio supply comparator using the lcd segment driver vlcd 10 uf bias generator data registers port drivers 32 segment pins 4 com pins lcd state machine configuration registers vbat charge pump power management clock divider smartclock lcd clock
si102x/3x 342 rev. 0.3 lcd0cf register. 8. set the lcd contrast using the lcd0cntrst register. 9. set the desired threshold for the vbat supply monitor. 10. set the lcd refresh rate usi ng the lcd0divh:lcd0divl registers. 11. write a pattern to the lcd0dn registers. 12. enable the lcd by setting bit 0 of lcd0mscn to logic 1 (lcd0mscn |= 0x01). 26.2. mapping data registers to lcd pins the lcd0 data registers are organized as 16 byte-wide special function registers (lcd0dn), each half- byte or nibble in these registers controls 1 lcd output pin. there are 32 nibbbles used to control the 32 segment pins. each lcd0 segment pin can control 1, 2, 3, or 4 lcd segments depending on the selected mux mode. th e least significant bit of each ni bble controls the segment connect ed to the backplane signal com0. the next to least significant bit controls the segment associated with com1, the next bit controls the segment associated with com2, and the most si gnificant bit in the 4-bit nibble controls the segment associated with com3. in static mode, only the least significant bit in each nibb le is used and the three remaining bits in each nib - ble are ignored. in 2-mux mode, only the two least significant bits are used; in 3-mux mode, only the three le ast sign ificant bits are used, and in 4-mux mode, each of the 4 bits in the nibble controls one lcd seg - ment. bits with a value of 1 turn on the associated s egm ent an d bits with a value of 0 turn off the associ - ated segment. sfr page: 0x2 addresses: lcd0d0 = 0x89, lcd0d1 = 0x 8a, lcd0d2 = 0x8b, lcd0d3 = 0x8c, ? lcd0d4 = 0x8d, lcd0d5 = 0x8e, lcd0d6 = 0x91, lcd0d7 = 0x92, ? lcd0d8 = 0x93, lcd0d9 = 0x94, lcd0da = 0x95, lcd0db = 0x96, ? lcd0dc = 0x97, lcd0dd = 0x99, lcd0de = 0x9a, lcd0df = 0x9b. sfr definition 26.1. lcd0dn: lcd0 data bit 7 6 5 4 3 2 1 0 name lcd0dn type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 lcd0dn lcd data. each nibble controls one lcd pin. see ?26.2. mapping data registers to lcd pins? on page 342 for additonal informatoin.
rev. 0.3 343 si102x/3x figure 26.2. lcd data register to lcd pin mapping lcd0df (pins: lcd31, lcd30) lcd0de (pins: lcd29, lcd28) lcd0dd (pins: lcd27, lcd26) lcd0dc (pins: lcd25, lcd24) lcd0db (pins: lcd23, lcd22) lcd0da (pins: lcd21, lcd20) lcd0d9 (pins: lcd19, lcd18) lcd0d8 (pins: lcd17, lcd16) lcd0d7 (pins: lcd15, lcd14) lcd0d6 (pins: lcd13, lcd12) lcd0d5 (pins: lcd11, lcd10) lcd0d4 (pins: lcd9, lcd8) lcd0d3 (pins: lcd7, lcd6) lcd0d2 (pins: lcd5, lcd4) lcd0d1 (pins: lcd3, lcd2) lcd0d0 (pins: lcd1, lcd0) com0 com1 com2 com3 com0 com1 com2 com3 01234567 bit:
si102x/3x 344 rev. 0.3 sfr page = 0x2; sfr address = 0x9d sfr definition 26.2. lcd0cn: lcd0 control register bit 7 6 5 4 3 2 1 0 name clkdiv[1:0] blank size muxmd[1:0] bias type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 reserved read = 0. must write 0b. 6:5 clkdiv[1:0] lcd0 clock divider. divides the smartclock output for use by the lcd0 module. see table 4.18 on page 68 for lcd clock frequency range. 00: the lcd clock is the smartclock divided by 1. 01: the lcd clock is the smartclock divided by 2. 10: the lcd clock is the smartclock divded by 4. 11: reserved. 4 blank blank all segments. blanks all lcd segments using a single bit. 0: all lcd segments are controlled by the lcd0dn registers. 1: all lcd segments are blank (turned off). 3 size lcd size select. selects whether 16 or 32 segment pi ns will be used for the lcd function. 0: p0 and p1 are used as lcd segment pins. 1: p0, p1, p2, and p3 are used as lcd segment pins. 2:1 muxmd[1:0] lcd bias power mode. selects the mux mode. 00: static mode selected. 01: 2-mux mode selected. 10: 3-mux mode selected. 11: 4-mux mode selected. 0 bias bias select . selects between 1/2 bias and 1/3 bias. th is bit is ignored if static mode is selected. 0: lcd0 is configured for 1/3 bias. 1: lcd0 is configured for 1/2 bias.
rev. 0.3 345 si102x/3x 26.3. lcd contrast adjustment the lcd bias voltages which determine the lcd contra st are generated using the vbat supply voltage or the on-chip charge pump. there are four contrast control modes to accomodate a wide variety of applica - tions and supply voltages. the target co ntrast vo ltage is programmable in 60 mv steps from 1.9 to 3.72 v. the lcd co ntrast voltage is controlled by the lcd0 cntrst register and the contrast control mode is selected by setting the appropriate bits in the lcd0mscn, lcd0mscf, lcd0pwr, and lcd0vbmcn registers. note: an external 10 f decoupling capacitor is required on the vlcd pin to crea te a charge reservoir at the output of the charge pump. 26.3.1. contrast contro l mode 1 (bypass mode) in contrast control mode 1, the contrast control circuitry is disabled and the vlcd voltage follows the vbat sup ply voltage, as shown in figure 26.3 . this mode is useful in syst ems w here the vbat voltage always remains constant and will pr ov ide the lowest lcd power consum ption. bypass mode is selected using the following procedure: 1. clear bit 2 of the lcd0mscn register to 0b (lcd0mscn &= ~0x04) 2. set bit 0 of the lcd0mscf register to 1b (lcd0mscf |= 0x01) 3. clear bit 3 of the lcd0pwr regi ster to 0b (lcd0pwr &= ~0x08) 4. clear bit 7 of the lcd0vbmcn register to 0b (lcd0vbmcn &= ~0x80) figure 26.3. contrast control mode 1 table 26.1. bit configurations to select contrast control modes mode lcd0mscn.2 lcd0mscf.0 lcd0pwr.3 lcd0vbmcn.7 1 0 1 0 0 2 0 1 1 1 3 1* 0 1 1 4 1* 0 0 1 * may be set to 0 to support increased load currents. vlcd vbat
si102x/3x 346 rev. 0.3 26.3.2. contrast co ntrol mode 2 (minimum contrast mode) in contrast control mode 2, a minimum cont rast voltage is maintained, as shown in figure 26.4 . the vlcd supply is powered directly from vbat as long as vba t is higher than the programmable vbat mon - itor threshold voltage. as soon as the vbat supply monitor detects that vbat has dropped below the pro - grammed value, the charge pump will be automatic ally enabled in order to acheive the desired minimum contrast voltage on vlcd. minimum contrast mode is selected using the following procedure: 1. clear bit 2 of the lcd0mscn register to 0b (lcd0mscn &= ~0x04) 2. set bit 0 of the lcd0mscf register to 1b (lcd0mscf |= 0x01) 3. set bit 3 of the lcd0pwr regi ster to 1b (lcd0pwr |= 0x08) 4. set bit 7 of the lcd0vbmcn register to 1b (lcd0vbmcn |= 0x80) figure 26.4. contrast control mode 2 26.3.3. contrast co ntrol mode 3 (constant contrast mode) in contrast control mode 3, a constant contrast volt age is maint ained. the vlcd s upply is regulated to the programmed contrast voltage using a variable resistor between vbat and vlcd as long as vbat is higher than the programmable vbat monitor threshold voltage. as soon as the vbat supply monitor detects that vbat has dropped be low the programmed valu e, the charge pump will be automatically enabled in order to acheive the desired contrast vo ltage on vlcd. constant co ntrast mode is selected using the following procedure: 1. set bit 2 of the lcd0mscn register to 1b (lcd0mscn |= 0x04) 2 . clear bit 0 of the lcd0mscf register to 0b (lcd0mscf &= ~0x01) 3. set bit 3 of the lcd0pwr regi ster to 1b (lcd0pwr |= 0x08) 4. set bit 7 of the lcd0vbmcn register to 1b (lcd0vbmcn |= 0x80) figure 26.5. contrast control mode 3 vlcd vbat vlcd vbat
rev. 0.3 347 si102x/3x 26.3.4. contrast control mode 4 (auto-bypass mode) in contrast control mode 4, behavior is identical to constant contrast mode as long as vbat is greater than the vbat monitor threshold voltage. when vbat drops below the programmed threshold, the device automatically enters bypass mode powering vlcd directly from vbat. the charge pump is always dis - abled in this mode. auto-bypass mode is selected using the following procedure: 1. set bit 2 of the lcd0mscn register to 1b (lcd0mscn |= 0x04) 2 . clear bit 0 of the lcd0mscf register to 0b (lcd0mscf &= ~0x01) 3. clear bit 3 of the lcd0pwr regi ster to 0b (lcd0pwr &= ~0x08) 4. set bit 7 of the lcd0vbmcn register to 1b (lcd0vbmcn |= 0x80) figure 26.6. contrast control mode 4 vlcd vbat
si102x/3x 348 rev. 0.3 sfr page = 0x2; sfr address = 0x9c sfr definition 26.3. lcd0cntrst: lcd0 contrast adjustment bit 7 6 5 4 3 2 1 0 name reserved reserved reserved cntrst type r/w r/w r/w r/w reset 00000000 bit name function 7:5 reserved read = 000. write = must write 000. 4:0 cntrst contrast setpoint. determines the setpoint for the vlcd voltage necessary to achieve the desired cont rast. 000 00: 00001: 00010: 00011: 00100: 00101: 00110: 00111: 01000: 01001: 01010: 01011: 01100: 01101: 01110: 01111: 10000: 10001: 10010: 10011: 10100: 10101: 10110: 10111: 11000: 11001: 11010: 11011: 11100: 11101: 11110: 11111: 1.90 1.96 2.02 2.08 2.13 2.19 2.25 2.31 2.37 2.43 2.49 2.55 2.60 2.66 2.72 2.78 2.84 2.90 2.96 3.02 3.07 3.13 3.19 3.25 3.31 3.37 3.43 3.49 3.54 3.60 3.66 3.72
rev. 0.3 349 si102x/3x sfr page = 0x2; sfr address = 0xab sfr definition 26.4. lcd0mscn: lcd0 master control bit 7 6 5 4 3 2 1 0 name biasen dcbiasoe clkoe lowdrv lcdrst lcden type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 1 0 0 0 0 0 bit name function 7 reserved read = 0b. must write 0b. 6 biasen lcd0 bias enable. lcd0 bias may be disabled when using a static lcd (single ba ckplane), contrast control mode 1 (bypass mode) is selected, and the vlcd/vio supply comparator is disabled (lcd0cf.5 = 1). it is required for all other modes. 0: lcd0 bias is disabled. 1: lcd0 bias is enabled 5 dcbiasoe dcdc converter bias output enable. (note 1) 0: the bias for the dcdc converter is gated off. 1: lcd0 provides the bi as for the d cdc converter. 4 clkoe lcd clock output enable. 0: the clock signal to the lcd0 module is gated off. 1: the smartclock provides the undivided clock to the lcd0 module. 3 reserved read = 0b. must write 0b. 2 lowdrv charge pump reduced drive mode. this bit should be set to 1 in contrast control mode 3 and mode 4 for minimum p o wer consumption. this bit may be set to 0 in these modes to support higher load current requirements. 0: the charge pump operates at full power. 1: the charge pump operates at reduced power. 1 lcdrst lcd0 reset. writing a 1 to this bit will clear all the lc d0dn r egisters to 0x00. this bit must be cleared by software. 0 lcden lcd0 enable. 0: lcd0 is disabled. 1: lcd0 is enabled. note 1: to same bias generator is shared by the dc-dc converter and lcd0.
si102x/3x 350 rev. 0.3 sfr page = 0x2; sfr address = 0xac sfr page = 0x2; sfr address = 0xa4 sfr definition 26.5. lcd0mscf: lcd0 mast er configuration bit 7 6 5 4 3 2 1 0 name dcenslp chpbyp type r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 1 1 1 1 0 bit name function 7:2 reserved read = 111111b. must write 111111b. 1 dcenslp dcdc converter enable in sleep mode 0: dcdc is disabled in sleep mode. 1: dcdc is enabled in sleep mode. 0 chpbyp lcd0 charge pump bypass this bit should be set to 1b in contrast control mode 1 and mode 2. 0: lcd0 charge pump is not bypassed. 1: lcd0 charge pump is bypassed. sfr definition 26.6. lcd0pwr: lcd0 power bit 7 6 5 4 3 2 1 0 name mode type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 1 0 0 1 bit name function 7:4 unused read = 0000b. write = don?t care. 3 mode lcd0 contrast control mode selection. 0: lcd0 contrast control mode 1 or mode 4 is selected. 1: lcd0 contrast control mode 2 or mode 3 is selected. 2:0 reserved read = 001b. must write 001b.
rev. 0.3 351 si102x/3x 26.4. adjusting the vbat monitor threshold the vbat monitor is used primarily for the contrast c ontrol function, to detect when vbat has fallen below a specific threshold. the vbat monitor threshold may be set independently of the contrast setting or it may be linked to the contrast setting. when the vbat monito r threshold is linked to the contrast setting, an off - set (in 60mv steps) may be configured so that the vba t mo nitor generates a vbat low condition prior to vbat dropping below the programmed contrast voltage. the lcd0vbmcn register is used to enable and configure the vbat monitor. the vbat monitor may be enabled as a wake-up source to wake up the device from sleep mode when the battery is getting low. see ?19. power management? on page 264 for more details. sfr page = 0x2; sfr address = 0xa6 sfr definition 26.7. lcd0vbmcn: lcd0 vbat monitor control bit 7 6 5 4 3 2 1 0 name vbatmen offset thrld[4:0] type r/w r/w r/w r/w reset 00000000 bit name function 7 vbatmen vbat monitor enable the vbat monitor should be enabled in contrast control mode 2, mode 3, and mod e 4. 0: the vbat monitor is disabled. 1: the vbat monitor is enabled. 6 offset vbat monitor offset enable 0: the vbat monitor threshold is in d epe ndent of the contrast setting. 1: the vbat monitor threshold is linked to the contrast setting. 5 unused read = 0. write = don?t care. 4:0 thrld[4:0] vbat monitor threshold if offset is set to 0b, this bit field ha s the same defintion as the cntrst bit field and can be programmed independently of the contrast. if offset is set to 1b, this bit field is in terpreted as an offset to the currently pro - grammed contrast setting. t h e lcd0cntrst register should be written before setting offset to logic 1 and should not be changed as long as vbat moni - tor offset is enabled. wh en thrld[4:0] is set to 00000b, the vbat monitor threshold is equal to the contrast voltage. when thrld[4:0] is set to 00001b, the vbat monitor threshold is one step higher t han the contrast voltage. the step size is equal to the step size of the cntrst bit field.
si102x/3x 352 rev. 0.3 26.5. setting the lcd refresh rate the clock to the lcd0 module is derived from the smartclock and may be divided down according to the settings in the lcd0cn register. the lcd refresh rate is derived from the lcd0 clock and can be pro - grammed using the lcd0divh:lcd0divl registers. t h e lcd mux mode must be taken into account when determining the prescaler value. see the l cd0divh/lcd0divl register descriptions for more details. for maximum power savings, choose a slow lcd refresh rate and the minimum lcd0 clock fre - quency. for the least flicker, choose a fast lcd refresh rate. sfr page = 0x2; sfr address = 0xaa sfr page = 0x2; sfr address = 0xa9 sfr definition 26.8. lcd0clkdivh: lcd0 refresh rate prescaler high byte bit 7 6 5 4 3 2 1 0 name lcd0div[9:8] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:2 unused read = 000000. write = don?t care. 1:0 lcd0div[9:8] lcd refresh rate prescaler . sets the lcd refresh rate according to the following equation: sfr definition 26.9. lcd0clkdivl: lcd refresh rate prescaler low byte bit 7 6 5 4 3 2 1 0 name lcd0div[7:0] type r/w reset 00000000 bit name function 7:0 lcd0div[7:0] lcd refresh rate prescaler . sets the lcd refresh rate according to the following equation: lcd refresh rate lcd0 clock frequency 4 mux_mode ? lcd 0 div 1+ ?? ? ----------------------------------------------------------------------------------- = lcd refresh rate lcd0 clock frequency 4 mux_mode ? lcd 0 div 1+ ?? ? ----------------------------------------------------------------------------------- =
rev. 0.3 353 si102x/3x 26.6. blinking lcd segments the lcd driver supports blinking lcd applications such as clock applications where the ?:? separator tog - gles on and off once per second. if the lcd is only disp la yin g the hours and minutes, then the device only needs to wake up once per minute to update the display. the once per second blinking is automatically handled by the si102x/3x. the lcd0blink register can be used to enable blinki ng on any lcd segment connected to the lcd0 or lcd1 segment pin. in static mode, a maximum of 2 segments can blink. in 2-mux mode, a maximum of 4 segments can blink; in 3-mux mode, a maximum of 6 segments can blink; and in 4-mux mode, a maximum of 8 segments can blink. the lcd0blink mask register targets the same lcd segments as the lcd0d0 register. if an lcd0blink bit correspo nding to an lcd segment is set to 1, then that segment will toggle at the frequency set by the lcd0togr register without any software intervention. sfr page = 0x2; sfr address = 0x9e sfr definition 26.10. lcd0blink: lcd0 blink mask bit 7 6 5 4 3 2 1 0 name lcd0blink[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 lcd0blink[7:0] lcd0 blink mask. each bit maps to a specific lcd segment connected to the lcd0 and lcd1 seg m ent pins. a value of 1 indicates that the segment is blinking. a value of 0 indicates that the segment is not blinki ng. this bit to segment mapping is the same as the lcd0d0 register.
si102x/3x 354 rev. 0.3 sfr page = 0x2; sfr address = 0x9f sfr definition 26.11. lcd0togr: lcd0 toggle rate bit 7 6 5 4 3 2 1 0 name togr[3:0] type r/w r/w r/w r/w r/w reset 00000000 bit name function 7:4 unused read = 0000. write = don?t care. 3:0 togr[3:0] lcd toggle rate divider. sets the lcd toggle rate according to the following equation: 0000: reserved. 0001: reserved. 0010: toggle rate divider is set to divide by 2. 0011: toggle rate divider is set to divide by 4. 0100: toggle rate divider is set to divide by 8. 0101: toggle rate divider is set to divide by 16. 0110: toggle rate divider is set to divide by 32. 0111: toggle rate divider is set to divide by 64. 1000: toggle rate divider is set to divide by 128. 1001: toggle rate divider is set to divide by 256. 1010: toggle rate divider is set to divide by 512. 1011: toggle rate divider is set to divide by 1024. 1100: toggle rate divider is set to divide by 2048. 1101: toggle rate divider is set to divide by 4096. all other values reserved. lcd toggle rate refresh rate mux_mode 2 ? ? toggle rate divider ------------------------------------------------------------------------- =
rev. 0.3 355 si102x/3x 26.7. advanced lcd optimizations the special function registers described in this section should be left at their re set value for most systems. some systems with specific low power or large load requirments will benefit from tweaking the values in these registers to achieve minimum power consumption or maximum drive level. sfr page = 0x2; sfr address = 0xa5 sfr page = 0x2; sfr address = 0xb5 sfr definition 26.12. lcd0cf: lcd0 configuration bit 7 6 5 4 3 2 1 0 name cmpbyp type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 : 6 reserved read = 00b. must write 00b. 5 cmpbyp vlcd/vio supply comparator disable. setting this bit to ?1? disables the supply voltage comparator which determines if the vio supply is lower than vlcd. this co mparator should only be disabled, as a power saving measure, if vio is internally or exte rnally shorted to vbat. 4 : 0 reserved read = 00b. must write 00000b. sfr definition 26.13. lcd0chpcn: lcd0 charge pump control bit 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 0 0 1 0 1 1 bit name function 7 : 0 reserved must write 0x4b.
si102x/3x 356 rev. 0.3 sfr page = 0x2; sfr address = 0xad sfr page = 0x2; sfr address = 0xae sfr page = 0xf; sfr address = 0x9c sfr definition 26.14. lcd0chpcf: lcd0 charge pump configuration bit 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 1 0 0 0 0 0 bit name function 7 : 0 reserved must write 0x60. sfr definition 26.15. lcd0chpmd: lcd0 charge pump mode bit 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w reset 1 1 1 0 1 0 0 1 bit name function 7 : 0 reserved must write 0xe9. sfr definition 26.16. lcd0bufcn: lcd0 buffer control bit 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 0 0 0 1 0 0 bit name function 7 : 0 reserved must write 0x44.
rev. 0.3 357 si102x/3x sfr page = 0xf; sfr address = 0xac sfr page = 0x2; sfr address = 0xb6 sfr page = 0x2; sfr address = 0xaf sfr definition 26.17. lcd0bufcf: lcd0 buff er configuration bit 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 1 1 0 0 1 0 bit name function 7 : 0 reserved must write 0x32. sfr definition 26.18. lcd0bufmd: lcd0 buffer mode bit 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 0 0 1 0 1 0 bit name function 7 : 0 reserved must write 0x4a. sfr definition 26.19. lcd0vbmcf: lcd0 vbat monitor configuration bit 7 6 5 4 3 2 1 0 name type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 1 0 1 1 bit name function 7 : 0 reserved must write 0x0b.
si102x/3x 358 rev. 0.3 27. port input/output digital and analog resources are available through 53 i/o pins. port pins are organized as eight byte-wide ports. port pins can be defined as digital or analog i/o. digital i/o pins can be assigned to one of the inter - nal digital resources or used as general purpose i/o (g pio). an alo g i/o pins are used by the internal ana - log resources. p7.0 can be used as gpio and is shar ed with the c2 interface data signal (c2d). see section ?35. c2 interface? on page 533 for more details. the designer has complete control over which digital and a nalog functions are assigned to individual port pins. this resource assignment flexib ility is achieved through the use of a priority crossbar decoder. see section 27.3 for more information on the crossbar. for port i/os configured as push-pull outputs, current is sourced from the vio or viorf supply pin. see section 27.1 for more information on port i/o operating mode s an d the electrical specifications chapter for detailed electrical specifications. figure 27.1. port i/o functional block diagram xbr0, xbr1, xbr2, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 port match p0mask, p0mat p1mask, p1mat uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 7 pca 4 cp0 cp1 outputs spi0 spi1 4 (port latches) p0 (p6.0-p6.7) 8 8 p6 p7 (p7.0) 1 pnmdout, pnmdin registers to analog peripherals (adc0, cp0, and cp1 inputs, vref, iref0, agnd) to lcd external interrupts ex0 and ex1 p1 i/o cells p1.0 p1.7 p2 i/o cells p2.0 p2.7 p3 i/o cells p3.0 p3.7 p4 i/o cells p4.0 p4.7 p5 i/o cells p5.0 p5.7 p6 i/o cells p6.0 p6.7 p7 p7.0 8 8 8 8 8 8 8 1 to emif
rev. 0.3 359 si102x/3x 27.1. port i/o m odes of operation port pins p0.0?p6.7 use the port i/o cell shown in figure 27.2 . the supply pin for p1.4 - p2.3 is viorf and the supply for all other gpios is vio. each port i/o cell ca n b e configured by software for analog i/o or digital i/o using the pnmdin registers. p7.0 can only be used for digital functtons and is shared with the c2d signal. on reset, all port i/o ce lls default to a digital high impedance state with weak pull-ups enabled. 27.1.1. port pins conf igu red f or analog i/o any pins to be used as comparator or adc input, external oscillator input/outpu t, or agnd , vref, or cur - rent reference output should be c onfigu r ed for analog i/o (pnmdin.n = 0). when a pin is configured for analo g i/o, its weak pullup and digital receiver are disa bled. in most cases, software should also disable the digital output drivers. port pi ns configured for analo g i/o will always read back a value of 0 regardless of the actual voltage on the pin. configuring pins as analog i/o saves power and isolat e s the port pin from digital interference. port pins configured as digital inputs may still be used by analog peripherals; howe ver, this practice is not recom - mended and may result in measurement errors. 27.1.2. port pins configured for digital i/o any pins to be used by digital peripherals (uart, sp i, sm bus, etc.), external digital event capture func - tions, or as gpio should be co nfigu r ed as digital i/o (pnmdin.n = 1). for digital i/o pins, one of two output mode s (push-pull or open-drain) must be selected using the pnmdout registers. push-pull outputs (pnmdout.n = 1) drive the port pad to the supply or gnd rails based on the output logic value o f the port pin. open-drain ou tputs have the high side driver disabl ed; therefore, they only drive the port pad to gnd when the output logic value is 0 and become high impedance inputs (both high and low drivers turned off) when the output logic value is 1. when a digital i/o cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to the su pply voltage to ensure the digital input is at a defined logic state. weak pull-ups are disabled when the i/o cell is driven to gnd to minimize power c onsumption and may be globally disabled by setting weakpud to 1. the user must ensure th at digital i/o are always internally or externally pu lled or driven to a valid logic state. port pins configured for digital i/ o always read back the logic state of the port pad, regardless of the output logic value of the port pin. figure 27.2. port i/o cell block diagram gnd supply supply (weak) port pad to/from analog peripheral pnmdin.x (1 for digital) (0 for analog) pn.x ? output logic value (port latch or crossbar) xbare (crossbar enable) pn.x ? input logic value (reads 0 when pin is configured as an analog i/o) pnmdout.x (1 for push-pull) (0 for open-drain) weakpud (weak pull-up disable)
si102x/3x 360 rev. 0.3 27.1.3. interfacing port i/o to high voltage logic all port i/o configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage up to vio + 2 v. an external pull-up resistor to the higher supply voltage is typically required for mos t systems. 27.1.4. increasing port i/o drive strength port i/o output drivers support a high and low drive st r e ngth; the default is low drive strength. the drive strength of a port i/o can be configur ed using the pndrv registers. see section ?4. electrical characteris - tics? on page 50 for the difference in output drive strength between the two modes. 27.2. assigning port i/o pins to analog and digital functions port i/o pins p0.0?p2.6 can be assigned to various a nalog, digital, and external interrupt functions. the port pins assigned to analog functions should be config ured for analog i/o, and port pins assigned to digital or external interrupt functions should be configured for digital i/o. 27.2.1. assigning port i/o pins to analog functions ta b l e 27.1 shows all available analog function s that ne ed port i/o assignments. port pins selected for these analog functions should have their digital dr iv ers disabled (pnmdout.n = 0 and port latch = 1) and their corresponding bit in pnskip set to 1. this reserves the pin for use by the analog function and does not allow it to be claimed by the crossbar. ta b l e 27.1 shows the potential mapping of port i/o to each analog function. table 27.1. port i/o assignment for analog functions analog function potentially assignab le port pins sfr(s) used for assignmen t adc input p0.0?p0.7, p1.4?p2.3 adc0mx, pnskip comparator0 input p0.0?p0.7, p1.4?p2.3 cpt0mx, pnskip comparator1 input p0.0?p0.7, p1.4?p2.3 cpt1mx, pnskip lcd pins (lcd0) p2.4?p6.7 pnmdin, pnskip pulse counter (pc0) p1.0, p1.1 p1mdin, pnskip voltage reference (vref0) p0.0 ref0cn, pnskip analog ground reference (agnd) p0.1 ref0cn, pnskip current reference (iref0) p0.7 iref0cn, pnskip external oscillator input (xtal1) p0.2 oscxcn, pnskip external oscillato r output (xt al2) p0.3 oscxcn, pnskip smartclock input (xtal3) p1.2 p1mdin, pnskip smartclock output (xtal4) p1.3 p1mdin, pnskip
rev. 0.3 361 si102x/3x 27.2.2. assigning port i/o pins to digital functions any port pins not assigned to analog functions may be assigned to digital functions or used as gpio. most digital functions rely on the crossbar for pin assignme nt; however, some digital functions bypass the cross - bar in a manner similar to the analog functions listed above. port pin s used by these digital functions and any port pins selected for use as gpio should have their corresponding bit in pnskip set to 1. ta b l e 27.2 shows all available digital functions and the potential mapping of port i/o to each digital func - tion. 27.2.3. assigning port i/o pins to external digital event capture functions external digital event captur e fu nctions ca n be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital i/o pin. the digital event capture functions do not require dedicated pins and will function on both gpio pins (p nskip = 1) and pins in use by the crossbar (pnskip = 0). external digital even capture functions cannot be used on pins configured for analog i/o. ta b l e 27.3 shows all available external digital event capture functions. table 27.2. port i/o assignment for digital functions digital function potentially assignable port pins sfr(s) used for assignmen t uart0, spi0, spi1, smbus, cp0 an d cp1 outputs, sys - tem clock output, pca0, t i mer0 and timer1 external inputs. any port pin available for assig nment by the crossbar. this includes p0.0?p2.7 pins which have their pnskip bit set to 0. note: the crossbar will always assign uart0 and spi1 pins to fixed locations. xbr0, xbr1, xbr2 any pin used for gpio p0.0?p7.0 p0skip, p1skip, p2sk ip external memory interface p3.6?p6.7 emi0cf table 27.3. port i/o assignment for external digital event capture functions digital function potentially assignable port pins sfr(s) used for assignmen t external interrupt 0 p0.0?p0.5, p1.6, p1.7 it01cf external interrupt 1 p0.0?p0.4, p1.6, p1.7 it01cf port match p0.0?p1.7 p0mask, p0mat p1mask, p1mat
si102x/3x 362 rev. 0.3 27.3. priority crossbar decoder the priority crossbar decoder assigns a port i/o pin to each software selected digital function using the fixed peripheral priority order shown in figure 27.3 . the registers xbr0, xbr1, and xbr2 defined in sfr definition 27.1 , sfr definition 27.2 , and sfr definition 27.3 are used to select digital functions in the crossbar. the port pins available for assignment by th e crossbar include all po rt pins (p0.0?p2.6) which have their corresponding bit in pnskip set to 0. from figure 27.3 , the highest priority peripheral is uart0. if uart 0 is selected in the crossbar (using the xbrn registers), then p0.4 and p0.5 will be ass i gned to uart0. the next highest priority peripheral is spi1. if spi1 is selected in the crossbar, then p2.0?p2.2 will be assigned to spi1. p2.3 will be assigned if spi1 is configured for 4-wire mode. the user should ensure that the pins to be assigned by the crossbar have their pnskip bits set to 0. for all remaining digital functions selected in the crossbar, starting at the top of figure 27.3 going down, the least-significant unskipped, unassign ed po rt pin(s) are assigned to that function. if a port pin is already assigned (e.g., uart0 or spi1 pins), or if its pnskip bit is set to 1, then the crossbar will skip over the pin and find next available unskipped, unassigned port pin. all port pins used for analog functions, gpio, or dedicated digital functions such as the emif should have their pnskip bit set to 1. figure 27.3 shows the crossbar decoder priority with no port pins skipped (p0skip, p1skip, p2skip = 0x00); figure 27.4 shows the crossbar decoder priority with the external osc illator pins (xtal1 and xtal2) skipped (p0skip = 0x0c). important notes: ? the crossbar must be enabled (xbare = 1) before any port pin is used as a digital outp ut. port output drivers are disabled while the crossbar is disabled. ? when smbus is selected in the crossbar, the pins associated wit h sda and scl will automatically be forced into open-drain output mode regardless of the pnmdout setting. ? spi0 can be operated in either 3-wire or 4-wir e modes, depending on the state of the nssmd1- nssmd0 bits in register spi0cn. the nss signal is only routed to a port pin when 4-wire mode is selected. when spi0 is selected in the crossbar, the spi0 mode (3-wir e or 4-wire) will affect the pinout of all digital functions lower in priority than spi0. ? for given xbrn, pnskip, and spincn register sett ings, one can determine the i/o pin-out of the device using figure 27.3 and figure 27.4 .
rev. 0.3 363 si102x/3x figure 27.3. crossbar priority decoder with no pins skipped vref agnd xtal1 xtal2 cnvstr iref0 012345670123456701234567 sck (spi1) miso (spi1) mosi (spi1) nss* (spi1) (*4-wire spi only) sck (spi0) miso (spi0) mosi (spi0) nss* (spi0) (*4-wire spi only) cp0 cp0a cp1 cp1a /sysclk cex0 cex1 cex2 cex3 cex4 cex5 eci t0 t1 000000000000000000000000 sf signals pin i/o tx0 p2 p2skip[0:7] p0 p1 p1skip[0:7] sda p0skip[0:7] scl rx0
si102x/3x 364 rev. 0.3 figure 27.4. crossbar priority decoder with crystal pins skipped vref agnd xtal1 xtal2 cnvstr iref0 012345670123456701234567 sck (spi1) miso (spi1) mosi (spi1) nss* (spi1) (*4-wire spi only) sck (spi0) miso (spi0) mosi (spi0) nss* (spi0) (*4-wire spi only) cp0 cp0a cp1 cp1a /sysclk cex0 cex1 cex2 cex3 cex4 cex5 eci t0 t1 000000000000000000000000 sda p0skip[0:7] scl p2 p2skip[0:7] p0 p1 p1skip[0:7] rx0 sf signals pin i/o tx0
rev. 0.3 365 si102x/3x sfr page = 0x0 and 0xf; sfr address = 0xe1 sfr definition 27.1. xbr0: port i/o crossbar register 0 bit 7 6 5 4 3 2 1 0 name cp1ae cp1e cp0ae cp0e syscke smb0e spi0e urt0e type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 cp1ae comparator1 asynchronous output enable. 0: asynchronous cp1 output unavailable at port pin. 1: asynchronous cp1 output routed to port pin. 6 cp1e comparator1 output enable. 0: cp1 output unavailable at port pin. 1: cp1 output routed to port pin. 5 cp0ae comparator0 asynchronous output enable. 0: asynchronous cp0 output unavailable at port pin. 1: asynchronous cp0 output routed to port pin. 4 cp0e comparator0 output enable. 0: cp1 output unavailable at port pin. 1: cp1 output routed to port pin. 3 syscke sysclk output enable. 0: sysclk output unavailable at port pin. 1: sysclk output routed to port pin. 2 smb0e smbus i/o enable. 0: smbus i/o unavailable at port pin. 1: sda and scl routed to port pins. 1 spi0e spi0 i/o enable 0: spi0 i/o unavailable at port pin. 1: sck, miso, and mosi (for spi0) routed to port pins. nss (for spi0) routed to port pin only if spi0 is configured to 4-wire mode. 0 urt0e uart0 output enable. 0: uart i/o unavailable at port pin. 1: tx0 and rx0 routed to port pins p0.4 and p0.5. note: spi0 can be assigned either 3 or 4 port i/o pins.
si102x/3x 366 rev. 0.3 sfr page = 0x0 and 0xf; sfr address = 0xe2 sfr definition 27.2. xbr1: port i/o crossbar register 1 bit 7 6 5 4 3 2 1 0 name spi1e t1e t0e ecie pca0me[2:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 unused read = 0b; write = don?t care. 6 spi1e spi0 i/o enable. 0: spi1 i/o unavailable at port pin. 1: sck (for spi1) routed to p2.0. miso (for spi1) routed to p2.1. mosi (for spi1) routed to p2.2. nss (for spi1) routed to p2.3 only if spi1 is configured to 4-wire mode. 5 t1e timer1 input enable. 0: t1 input unavailable at port pin. 1: t1 input routed to port pin. 4 t0e timer0 input enable. 0: t0 input unavailable at port pin. 1: t0 input routed to port pin. 3 ecie pca0 external counter input (eci) enable. 0: pca0 external counter input unavailable at port pin. 1: pca0 external counter input routed to port pin. 2:0 pca0me pca0 module i/o enable. 000: all pca0 i/o unavailable at port pin. 001: cex0 routed to port pin. 010: cex0, cex1 routed to port pins. 011: cex0, cex1, cex2 routed to port pins. 100: cex0, cex1, cex2 cex3 ro uted to port pins. 101: cex0, cex1, cex2, cex3, c ex4 routed to port pins. 110: cex0, cex1, cex2, cex3, cex4 , cex5 routed to port pins. 111: reserved. note: spi1 can be assigned either 3 or 4 port i/o pins.
rev. 0.3 367 si102x/3x sfr page = 0x0 and 0xf; sfr address = 0xe3 sfr definition 27.3. xbr2: port i/o crossbar register 2 bit 7 6 5 4 3 2 1 0 name weakpud xbare type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0000000 bit name function 7 weakpud port i/o weak pullup disable 0: weak pullups enabled (except for port i/o pins configured for analog mode). 6 xbare crossbar enable 0: crossbar disabled. 1: crossbar enabled. 5:0 unused read = 000000b; write = don?t care. note: the crossbar must be enabled (xbare = 1) to use any port pin as a digital output.
si102x/3x 368 rev. 0.3 27.4. port match port match functionality allows system events to be tr iggered by a logic value change on p0 or p1. a soft - ware controlled value stored in the pnmat registers sp e c ifies the expected or normal logic values of p0 and p1. a port mismatch event occurs if the logic leve ls of the port?s input pins no longer match the soft - ware controlled value. this allows so f t ware to be notified if a certain change or pattern occurs on p0 or p1 input pins regardless of the xbrn settings. the pnmask registers can be used to individually select which p0 a nd p1 pins should be compared against the pnmat registers. a port mismatch event is generated if (p0 & p0mask) does not equal (pn m at & p0mask) or if (p1 & p1mask) does not equal (pnmat & p1mask). a port mismatch event may be used to generate an interrupt or wake the device from a low power mode. see section ?17. interrupt handler? on page 238 and section ?19. power management? on page 264 for more details on interrupt and wake-up sources. sfr page= 0x0; sfr address = 0xc7 sfr page= 0x0; sfr address = 0xd7 sfr definition 27.4. p0mask: port0 mask register bit 7 6 5 4 3 2 1 0 name p0mask[7:0] type r/w reset 00000000 bit name function 7:0 p0mask[7:0] port0 mask value. selects the p0 pins to be compared with the corresponding bits in p0mat. 0: p0.n pin pad logic value is ignored an d ca nnot cause a port mismatch event. 1: p0.n pin pad logic value is compared to p0mat.n. sfr definition 27.5. p0mat: port0 match register bit 7 6 5 4 3 2 1 0 name p0mat[7:0] type r/w reset 11111111 bit name function 7 : 0 p0mat[7:0] port 0 match value. match comparison value used on port 0 for bits in p0mask which are set to 1. 0: p0.n pin logic value is compared with logic low. 1: p0.n pin logic value is compared with logic high.
rev. 0.3 369 si102x/3x sfr page= 0x0; sfr address = 0xbf sfr page = 0x0; sfr address = 0xcf sfr definition 27.6. p1mask: port1 mask register bit 7 6 5 4 3 2 1 0 name p1mask[7:0] type r/w reset 00000000 bit name function 7:0 p1mask[7:0] port 1 mask value. selects p1 pins to be compared to the corresponding bits in p1mat. 0: p1.n pin logic value is ignored and ca nno t cause a port mismatch event. 1: p1.n pin logic value is compared to p1mat.n. note: sfr definition 27.7. p1mat: port1 match register bit 7 6 5 4 3 2 1 0 name p1mat[7:0] type r/w reset 11111111 bit name function 7:0 p1mat[7:0] port 1 match value. match comparison value used on port 1 for bit s in p1mask which are set to 1. 0: p1.n pin logic value is compared with logic low. 1: p1.n pin logic value is compared with logic high. note:
si102x/3x 370 rev. 0.3 27.5. special function re gisters for accessing an d configuring port i/o all port i/o are accessed through corresponding spec ial function registers (sfrs) that are both byte addressable and bit addressable. when writing to a por t, the value written to the sfr is latched to maintain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corresponding port i/o pin). the exception to this is the execution of the read-modify-write instructions that target a port latch register as th e destination. the read-modify-write instructions when operating on a port sfr are the fo llowing: anl, orl, xrl, jb c, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an indivi dual bit in a port sfr. for these instructions, the value of the latch register (not the pin) is read, modified, and written back to the sfr. each port has a corresponding pnskip register which a llows it s in dividual port pins to be assigned to digi - tal functions or skipped by the crossbar. all port pins u s ed for analog functions, gpio, or dedicated digital functions such as the emif shou ld have their pnskip bit set to 1. the port input mode of the i/o pins is defined using the por t input mode registers (pnmdin). each port cell can be configured for analog or digital i/o. this selectio n is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is p2.7, which can only be used for digital i/o. the output driver characteristics of the i/o pins ar e d e fined using the port output mode registers (pnmd - out). each port output driver can be configured as eithe r open drain or push-pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. the drive strength of the output driv ers a r e controlled by the port drive strength (pndrv) registers. the default is low drive strength. see section ?4. electrical characteristics? on page 50 for the difference in out - put drive strength between the two modes.
rev. 0.3 371 si102x/3x sfr page = all pages; sfr address = 0x80; bit-addressable sfr page= 0x0; sfr address = 0xd4 sfr definition 27.8. p0: port0 bit 7 6 5 4 3 2 1 0 name p0[7:0] type r/w reset 11111111 bit name description write read 7:0 p0[7:0] port 0 data. sets the port latch logic valu e or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic lo w . 1: set output latch to logic high. 0: p0.n port pin is logic low. 1 : p0.n port pin is logic high . sfr definition 27.9. p0skip: port0 skip bit 7 6 5 4 3 2 1 0 name p0skip[7:0] type r/w reset 00000000 bit name function 7:0 p0skip[7:0] port 0 crossbar skip enable bits. these bits select port 0 pins to be skip pe d by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar.
si102x/3x 372 rev. 0.3 sfr page= 0x0; sfr address = 0xf1 sfr page = 0x0; sfr address = 0xa4 sfr definition 27.10. p0mdin: port0 input mode bit 7 6 5 4 3 2 1 0 name p0mdin[7:0] type r/w reset 11111111 bit name function 7:0 p0mdin[7:0] analog configuration bits for p0.7?p0.0 (respectively). port pins configured for analog mode have their weak pullup, and digital receiver disabled. the digital driver is not explicitly disabled. 0: corresponding p0.n pin is configured for analog mode. 1: corresponding p0.n pin is not configured for analog mode. sfr definition 27.11. p0mdout: port0 output mode bit 7 6 5 4 3 2 1 0 name p0mdout[7:0] type r/w reset 00000000 bit name function 7:0 p0mdout[7:0] output configuration bits for p0.7?p0.0 (respectively). these bits control the digital driver even whe n the corresponding bit in register p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull.
rev. 0.3 373 si102x/3x sfr page = 0xf; sfr address = 0xa4 sfr page = all pages; sfr address = 0x90; bit-addressable sfr definition 27.12. p0drv: port0 drive strength bit 7 6 5 4 3 2 1 0 name p0drv[7:0] type r/w reset 00000000 bit name function 7:0 p0drv[7:0] drive strength configuration bits for p0.7?p0.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p0.n output has low output drive strength. 1: corresponding p0.n output has high output drive strength. sfr definition 27.13. p1: port1 bit 7 6 5 4 3 2 1 0 name p1[7:0] type r/w reset 11111111 bit name description write read 7:0 p1[7:0] port 1 data. sets the port latch logic valu e or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic lo w . 1: set output latch to logic high. 0: p1.n port pin is logic low. 1 : p1.n port pin is logic hi gh .
si102x/3x 374 rev. 0.3 sfr page = 0x0; sfr address = 0xd5 sfr page = 0x0; sfr address = 0xf2 sfr definition 27.14. p1skip: port1 skip bit 7 6 5 4 3 2 1 0 name p1skip[7:0] type r/w reset 00000000 bit name function 7:0 p1skip[7:0] port 1 crossbar skip enable bits. these bits select port 1 pins to be skip pe d by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. sfr definition 27.15. p1mdin: port1 input mode bit 7 6 5 4 3 2 1 0 name p1mdin[7:0] type r/w reset 11111111 bit name function 7:0 p1mdin[7:0] analog configuration bits for p1.7?p1.0 (respectively). port pins configured for analog mode have their we ak pullup and digital receiver disabled. the digital driver is not explicitly disabled. 0: corresponding p1.n pin is configured for analog mode. 1: corresponding p1.n pin is not configured for analog mode.
rev. 0.3 375 si102x/3x sfr page = 0x0; sfr address = 0xa5 sfr page = 0xf; sfr address = 0xa5 sfr definition 27.16. p1mdout: port1 output mode bit 7 6 5 4 3 2 1 0 name p1mdout[7:0] type r/w reset 00000000 bit name function 7:0 p1mdout[7:0] output configuration bits for p1.7?p1.0 (respectively). these bits control the digital driver even whe n the corresponding bit in register p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. sfr definition 27.17. p1drv: port1 drive strength bit 7 6 5 4 3 2 1 0 name p1drv[7:0] type r/w reset 00000000 bit name function 7:0 p1drv[7:0] drive strength configuration bits for p1.7?p1.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p1.n output has low output drive strength. 1: corresponding p1.n output has high output drive strength.
si102x/3x 376 rev. 0.3 sfr page = all pages; sfr ad dress = 0xa0; bit-addressable sfr page = 0x0; sfr address = 0xd6 sfr definition 27.18. p2: port2 bit 7 6 5 4 3 2 1 0 name p2[7:0] type r/w reset 11111111 bit name description read write 7:0 p2[7:0] port 2 data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic lo w . 1: set output latch to logic high. 0: p2.n port pin is logic low. 1 : p2.n port pin is logic high . sfr definition 27.19. p2skip: port2 skip bit 7 6 5 4 3 2 1 0 name p2skip[7:0] type r/w reset 00000000 bit name description read write 7:0 p2skip[7:0] port 1 crossbar skip enable bits. these bits select port 2 pins to be skipped by the cr ossbar decode r. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p2.n pin is not skipped by the crossbar. 1: corresponding p2.n pin is skipped by the crossbar.
rev. 0.3 377 si102x/3x sfr page = 0x0; sfr address = 0xf3 sfr page = 0x0; sfr address = 0xa6 sfr definition 27.20. p2mdin: port2 input mode bit 7 6 5 4 3 2 1 0 name p2mdin[6:0] type r/w reset 11111111 bit name function 7 reserved read = 1b; must write 1b. 6:0 p2mdin[6:0] analog configuration bits for p2.6?p2.0 (respectively). port pins configured for analog mode have their weak pullup and digital receiver d i sabled. the digital driver is not explicitly disabled. 0: corresponding p2.n pin is configured for analog mode. 1: corresponding p2.n pin is not configured for analog mode. sfr definition 27.21. p2mdout: port2 output mode bit 7 6 5 4 3 2 1 0 name p2mdout[7:0] type r/w reset 00000000 bit name function 7:0 p2mdout[7:0] output configuration bits for p2.7?p2.0 (respectively). these bits control the digital driver even whe n the corresponding bit in register p2mdin is logic 0. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull.
si102x/3x 378 rev. 0.3 sfr page = 0x0f; sfr address = 0xa6 sfr page = all pages; sfr ad dress = 0xb0; bit-addressable sfr definition 27.22. p2drv: port2 drive strength bit 7 6 5 4 3 2 1 0 name p2drv[7:0] type r/w reset 00000000 bit name function 7:0 p2drv[7:0] drive strength configuration bits for p2.7?p2.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p2.n output has low output drive strength. 1: corresponding p2.n output has high output drive strength. sfr definition 27.23. p3: port3 bit 7 6 5 4 3 2 1 0 name p3[7:0] type r/w reset 11111111 bit name description read write 7:0 p3[7:0] port 3 data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic lo w . 1: set output latch to logic high. 0: p3.n port pin is logic low. 1 : p3.n port pin is logic high .
rev. 0.3 379 si102x/3x sfr page = 0xf; sfr address = 0xf1 sfr page = 0xf; sfr address = 0xb1 sfr definition 27.24. p3mdin: port3 input mode bit 7 6 5 4 3 2 1 0 name p3mdin[7:0] type r/w reset 11111111 bit name function 7:0 p3mdin[7:0] analog configuration bits for p3.7?p3.0 (respectively). port pins configured for analog mode have their weak pullup and digital receiver d i sabled. the digital driver is not explicitly disabled. 0: corresponding p3.n pin is configured for analog mode. 1: corresponding p3.n pin is not configured for analog mode. sfr definition 27.25. p3mdout: port3 output mode bit 7 6 5 4 3 2 1 0 name p3mdout[7:0] type r/w reset 00000000 bit name function 7:0 p3mdout[7:0] output configuration bits for p3.7?p3.0 (respectively). these bits control the digital driver even whe n the corresponding bit in register p3mdin is logic 0. 0: corresponding p3.n output is open-drain. 1: corresponding p3.n output is push-pull.
si102x/3x 380 rev. 0.3 sfr page = 0xf; sfr address = 0xa1 sfr page = 0xf; sfr address = 0xd9 sfr definition 27.26. p3drv: port3 drive strength bit 7 6 5 4 3 2 1 0 name p3drv[7:0] type r/w reset 00000000 bit name function 7:0 p3drv[7:0] drive strength configuration bits for p3.7?p3.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p3.n output has low output drive strength. 1: corresponding p3.n output has high output drive strength. sfr definition 27.27. p4: port4 bit 7 6 5 4 3 2 1 0 name p4[7:0] type r/w reset 11111111 bit name description read write 7:0 p4[7:0] port 4 data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic lo w . 1: set output latch to logic high. 0: p4.n port pin is logic low. 1 : p4.n port pin is logic high .
rev. 0.3 381 si102x/3x sfr page = 0xf; sfr address = 0xf2 sfr page = 0xf; sfr address = 0xf9 sfr definition 27.28. p4mdin: port4 input mode bit 7 6 5 4 3 2 1 0 name p4mdin[7:0] type r/w reset 11111111 bit name function 7:0 p4mdin[7:0] analog configuration bits for p4.7?p4.0 (respectively). port pins configured for analog mode have their weak pullup and digital receiver d i sabled. the digital driver is not explicitly disabled. 0: corresponding p4.n pin is configured for analog mode. 1: corresponding p4.n pin is not configured for analog mode. sfr definition 27.29. p4mdout: port4 output mode bit 7 6 5 4 3 2 1 0 name p4mdout[7:0] type r/w reset 00000000 bit name function 7:0 p4mdout[7:0] output configuration bits for p4.7?p4.0 (respectively). these bits control the digital driver even whe n the corresponding bit in register p4mdin is logic 0. 0: corresponding p4.n output is open-drain. 1: corresponding p4.n output is push-pull.
si102x/3x 382 rev. 0.3 sfr page = 0xf; sfr address = 0xa2 sfr page = 0xf; sfr address = 0xda sfr definition 27.30. p4drv: port4 drive strength bit 7 6 5 4 3 2 1 0 name p4drv[7:0] type r/w reset 00000000 bit name function 7:0 p4drv[7:0] drive strength configuration bits for p4.7?p4.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p4.n output has low output drive strength. 1: corresponding p4.n output has high output drive strength. sfr definition 27.31. p5: port5 bit 7 6 5 4 3 2 1 0 name p5[7:0] type r/w reset 11111111 bit name description read write 7:0 p5[7:0] port 5 data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic lo w . 1: set output latch to logic high. 0: p5.n port pin is logic low. 1 : p5.n port pin is logic high .
rev. 0.3 383 si102x/3x sfr page = 0xf; sfr address = 0xf3 sfr page = 0xf; sfr address = 0xfa sfr definition 27.32. p5mdin: port5 input mode bit 7 6 5 4 3 2 1 0 name p5mdin[7:0] type r/w reset 11111111 bit name function 7:0 p5mdin[7:0] analog configuration bits for p5.7?p5.0 (respectively). port pins configured for analog mode have their weak pullup and digital receiver d i sabled. the digital driver is not explicitly disabled. 0: corresponding p5.n pin is configured for analog mode. 1: corresponding p5.n pin is not configured for analog mode. note: sfr definition 27.33. p5mdout: port5 output mode bit 7 6 5 4 3 2 1 0 name p5mdout[7:0] type r/w reset 00000000 bit name function 7:0 p5mdout[7:0] output configuration bits for p5.7?p5.0 (respectively). these bits control the digital driver even whe n the corresponding bit in register p5mdin is logic 0. 0: corresponding p5.n output is open-drain. 1: corresponding p5.n output is push-pull. note:
si102x/3x 384 rev. 0.3 sfr page = 0xf; sfr address = 0xa3 sfr page = 0xf; sfr address = 0xdb sfr definition 27.34. p5drv: port5 drive strength bit 7 6 5 4 3 2 1 0 name p5drv[7:0] type r/w reset 00000000 bit name function 7:0 p5drv[7:0] drive strength configuration bits for p5.7?p5.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p5.n output has low output drive strength. 1: corresponding p5.n output has high output drive strength. sfr definition 27.35. p6: port6 bit 7 6 5 4 3 2 1 0 name p6[7:0] type r/w reset 11111111 bit name description read write 7:0 p6[7:0] port 6 data. sets the port latch logic value or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic lo w . 1: set output latch to logic high. 0: p6.n port pin is logic low. 1 : p6.n port pin is logic high .
rev. 0.3 385 si102x/3x sfr page = 0xf; sfr address = 0xf4 sfr page = 0xf; sfr address = 0xfb sfr definition 27.36. p6mdin: port6 input mode bit 7 6 5 4 3 2 1 0 name p6mdin[7:0] type r/w reset 11111111 bit name function 7:0 p6mdin[7:0] analog configuration bits for p6.7?p6.0 (respectively). port pins configured for analog mode have their weak pullup and digital receiver d i sabled. the digital driver is not explicitly disabled. 0: corresponding p6.n pin is configured for analog mode. 1: corresponding p6.n pin is not configured for analog mode. sfr definition 27.37. p6mdout: port6 output mode bit 7 6 5 4 3 2 1 0 name p6mdout[7:0] type r/w reset 00000000 bit name function 7:0 p6mdout[7:0] output configuration bits for p6.7?p6.0 (respectively). these bits control the digital driver even whe n the corresponding bit in register p6mdin is logic 0. 0: corresponding p6.n output is open-drain. 1: corresponding p6.n output is push-pull.
si102x/3x 386 rev. 0.3 sfr page = 0xf; sfr address = 0xaa sfr page = 0xf; sfr address = 0xdc sfr definition 27.38. p6drv: port6 drive strength bit 7 6 5 4 3 2 1 0 name p6drv[7:0] type r/w reset 00000000 bit name function 7:0 p6drv[7:0] drive strength configuration bits for p6.7?p6.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p6.n output has low output drive strength. 1: corresponding p6.n output has high output drive strength. sfr definition 27.39. p7: port7 bit 7 6 5 4 3 2 1 0 name p7.0 type r/w reset 11111111 bit name description read write 7:1 unused read = 0000000b; write = don?t care. 0 p7.0 port 7 data. sets the port latch logic valu e or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic lo w . 1: set output latch to logic high. 0: p7.0 port pin is logic low. 1 : p7.0 port pin is logic high .
rev. 0.3 387 si102x/3x sfr page = 0xf; sfr address = 0xfc sfr page = 0xf; sfr address = 0xab sfr definition 27.40. p7mdout: port7 output mode bit 7 6 5 4 3 2 1 0 name p7mdout type r/w reset 0000000 0 bit name function 7:1 unused read = 0000000b; write = don?t care. 0 p7mdout.0 output configuration bits for p7.0. these bits control the digital driver. 0: p7.0 output is open-drain. 1: p7.0 output is push-pull. sfr definition 27.41. p7drv: port7 drive strength bit 7 6 5 4 3 2 1 0 name p7drv type r/w reset 00000000 bit name function 7:1 unused read = 0000000b; write = don?t care. 0 p7drv.0 drive strength configuration bits for p7.0. configures digital i/o port cells to high or low output drive strength. 0: p7.0 output has low output drive strength. 1: p7.0 output has high output drive strength.
si102x/3x 388 rev. 0.3 28. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification version 1.1 and compatible with the i 2 c serial bus. reads and writes to the interface by the system controller are byte oriented with the smbus in terface auto nomously controlling the serial transfer of the data. data can be transferred at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or sla v e, and may function on a bus with multiple mas - ters. the smbus provides control of sda (serial data), scl ( s erial clock) generation and synchronization, arbitration logic, and start/stop control and genera tion. the smbus peripheral can be fully driven by software (i.e., software ac cepts/rejects slave addresses, and generat es acks), or hardware slave address recognition and automatic ack gener ation can be enabled to minimize software overhead. a block dia - gram of the smbus peripheral and the associated sfrs is shown in figure 28.1 . figure 28.1. smbus block diagram data path control smbus control logic c r o s s b a r scl filter n sda control scl control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n smb0adr s l v 4 s l v 2 s l v 1 s l v 0 g c s l v 5 s l v 6 s l v 3 smb0adm s l v m 4 s l v m 2 s l v m 1 s l v m 0 e h a c k s l v m 5 s l v m 6 s l v m 3 arbitration scl synchronization hardware ack generation scl generation (master mode) sda control hardware slave address recognition irq generation
rev. 0.3 389 si102x/3x 28.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including specifications), philips semiconductor. 2. the i 2 c-bus specification?version 2.0, philips semiconductor. 3. system management bus specification?version 1.1, sbs implementers forum. 28.2. smbus configuration figure 28.2 shows a typical smbus configuration. the smbu s sp ecification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. the bi-direc - tional scl (serial clock) and sda (serial data) lines mu st b e connected to a positive power supply voltage through a pullup resistor or similar circuit. every devi ce connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 28.2. typical smbus configuration 28.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitr ation. note that it is not necessary to specify one device as the master in a system ; any device who transmits a star t and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond itio n followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. bytes that are received (by a master or slave) are acknowledg ed (ack) with a low sda during a high scl (see figure 28.3 ). if the receiving device does not ac k, the transmitting device will read a nack (not acknowl - edge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit positio n of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. v dd = 5 v master device slave device 1 slave device 2 v dd = 3 v v dd = 5 v v dd = 3 v sda scl
si102x/3x 390 rev. 0.3 all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmits the slave address and direction bit. if the trans - action is a write operation from the ma ster to the slave, the master tr ansmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transaction and free the bus. figure 28.3 illustrates a typical smbus transaction. figure 28.3. smbus transaction 28.3.1. transmitter vs. receiver on the smbus communications interface, a device is the ?transmitter? when it is sending an address or da ta byte to another device on the bus. a device is a ?receiver? when an ad dress or data byte is being sent to it from another device on the bus. the transmitter controls the sda line during the address or data byte. after each byte of address or data information is sent by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, dur ing which time the receiver controls the sda line. 28.3.2. arbitration a master may start a transfer only if the bus is free. th e b u s is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?28.3.5. scl high (smbus free) timeout? on page 391 ). in the event that two or more d evices attempt to begin a transfer at the same time, an arbitra - tion scheme is employed to force one master to give u p the bus. the master devices continue transmitting until one attempts a high while the other transmits a low. since the bus is open-drain, the bus will be pulled low. the master attempting th e high will detect a low sda and lo se the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destru ctive: one device always wins, and no data is lost. 28.3.3. clock low extension smbus provides a clock synchron ization me ch anism, similar to i 2 c, which allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 28.3.4. scl low timeout if the scl line is held low by a slave device on the bus, n o further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi - cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to re load when scl is high, and allowed to count when scl is low. with timer 3 enabled and configured to sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop
rev. 0.3 391 si102x/3x overflow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable and r e-enable) the smbus in the event of an scl low timeout. 28.3.5. scl high (smbus free) timeout the smbus specification stipulates th at if the scl and sda lines remain high for more that 50 s, the bus is desi gnated as free. when the sm bfte bit in smb0cf is set, the bu s will be considered free if scl and sda remain high for more than 10 smbus clock source periods (as defined by the timer configured for the smbus clock source). if the smbus is waiting to generate a master start, the start will be generated following this timeout. a clock source is required for free timeout detection, even in a slave-only implemen - tation. 28.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con - trol for serial transfers; higher level protocol is dete rm in ed by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as defined by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information ? optional hardware recognition of slave address and automatic acknowledgement of address/data smbus interrupts are generated for each data byte or slave ad dress that is transferred. when hardware acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard - ware is acting as a data transmitter or receiver. wh e n a transmitter (i.e., sending address/data, receiving an ack), this interrupt is generated after the ack cycl e so that software may read the received ack value; when receiving data (i.e., receiving address/data, send ing an ack), this interrupt is generated before the ack cycle so that software may def ine the outgoing ack value. if har dware acknowledgement is enabled, these interrupts are always generated after the ack cycle. see section 28.5 for more details on transmis - sion sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus inte rrupt. the smb0cn register is described in section 28.4.2 ; ta b l e 28.5 provides a quick smb0cn decoding reference. 28.4.1. smbus conf ig u ration register the smbus configuration register (s mb0c f) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options . when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer).
si102x/3x 392 rev. 0.3 the smbcs1?0 bits select the smbus clock source, which is used only when operating as a master or when the free timeout detection is enabled. when op erating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 28.1 . the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uar t baud rates simultaneously. timer configuration is covered in section ?33. timers? on page 491 . equation 28.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equation 28.1 . when the interface is operating as a master ( a nd scl is not driven or extended by any other devices on the bus), the typica l smbus bit rate is app ro ximated by equation 28.1 . equation 28.2. typical smbus bit rate figure 28.4 shows the typical scl generation described by equation 28.2 . notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will neve r exceed the limits defined by equation 28.2 . figure 28.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. ta b l e 28.2 shows the min - imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mh z. table 28.1. smbus clock source selection smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow t highmin t lowmin 1 f clocksourceoverflow ---------------------------------- ----------- - == bitrate f clocksourceoverflow 3 --------------- ------------------------------ - = scl timer source overflows scl high timeout t low t high
rev. 0.3 393 si102x/3x with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low timeout s (see section ?28.3.4. scl low timeout? on page 390 ). the smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count when scl is low. the timer 3 interrupt service routine sho u ld be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is se t, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 28.4 ). table 28.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay* 3 system clocks 1 11 system clocks 12 system clocks *note: setup time for ack bit transmissions and the msb of all data transfers. when using software acknowledgement, the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero.
si102x/3x 394 rev. 0.3 sfr page = 0x0; sfr address = 0xc1 sfr definition 28.1. smb0cf: smbus clock/configuration bit 7 6 5 4 3 2 1 0 name ensmb inh busy exthold smbtoe smbfte smbcs[1:0] type r/w r/w r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ensmb smbus enable. this bit enables the smbus interface when se t to 1. when enabled, the interface constantly monitors the sda and scl pins. 6 inh smbus slave inhibit. when this bit is set to logic 1, the smbu s d oes no t generate an interrupt when slave events occur. this effectively removes the smbus slave from the bus. master mode interrupts are not affected. 5 busy smbus busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. 4 exthold smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to ta b l e 28.2 . 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. 3 smbtoe smbus scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus forces ti m er 3 to reload while scl is high and allows timer 3 to count when scl goes low. if t imer 3 is configured to split mode, only the high byte of the timer is held in reload while scl is high. t imer 3 should be programmed to generate interrupts at 25 ms, an d th e timer 3 interrupt service routine should reset smbus communication. 2 smbfte smbus free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if sc l and sda remain high for more than 10 smbus clock source periods. 1 : 0 smbcs[1:0] smbus clock source selection. these two bits select the smbus clock sour ce, which is used to generate the smbus bit rate. the selected device should be configured according to equation 28.1 . 00: timer 0 overflow 01: timer 1 overflow 10:timer 2 high byte overflow 11: timer 2 low byte overflow
rev. 0.3 395 si102x/3x 28.4.2. smb0cn control register smb0cn is used to control the interface and to provide status information (see sfr definition 28.2 ). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to ju mp to service routines. master indicates whether a device is the master or slave during the current transfer. txmode indicates whether the device is tr ansmitting or receiving data for the current byte. sta and sto indicate that a start and/or stop ha s bee n detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas - ter. writing a 1 to sta will cause the smbus interface to enter master mode and generate a start when th e bus becomes free (sta is not cleared by hardwar e after the start is generated). writing a 1 to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. the arblost bit indicates that the interface has lost an arb itration. this may occur anytime the interface is transmitting (master or slave). a lost arbitratio n while operating as a slave indicates a bus error condi - tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see ta b l e 28.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. 28.4.2.1. software ack generation when the ehack bit in register smb0 adm is clear ed to 0, the firmware on the device must detect incom - ing slave addresses and ack or nack the slave addres s and incoming dat a bytes. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received during the last ack cycle. ackrq is set each ti me a byte is received, indi cating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be g enerated if software does not write the ack bit before clearing si. sda will reflect the defined ack value immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave address is not acknowledged, further slave events will be ignored until the next start is detected. 28.4.2.2. hardwa re ac k generation when the ehack bit in register smb0adm is set to 1, automa tic slave address recognition and ack gen - eration is enabled. more detail about automatic slave address recognition can be found in section 28.4.3 . as a receiver, the value currently specified by the ac k bit w ill be automatically sent on the bus during the ack cycle of an incoming data byte. as a transmitter, reading the ack bit indicates the value received on the last ack cycle. the ackrq bit is not used when hardware ack generation is enabled. if a received slave address is nacked by hardware, further sl ave events will be ignored un til the next start is detected, and no interrupt will be generated. ta b l e 28.3 lists all sources for hardware changes to the smb0cn bits. refer to ta b l e 28.5 for smbus sta - tus decoding using the smb0cn register.
si102x/3x 396 rev. 0.3 sfr page = all pages; sfr ad dress = 0xc0; bit-addressable sfr definition 28.2. smb0cn: smbus control bit 7 6 5 4 3 2 1 0 name master txmode sta sto ackrq arblost ack si type rrr/wr/wrrr/wr/w reset 00000000 bit name description read write 7 master smbus master/slave in dic ator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mo de. 1: smbus ope rating in master mode. n/a 6 txmode smbus transmit mode indic ator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mo de. 1: smbus in t ransmitter mode. n/a 5 st a smbus start flag. 0: no start or repeated st art detected. 1: start or repeated start detected. 0: no start generated. 1: when configured as a mas t er, initiates a start or repeated start. 4 sto smbus stop flag. 0: no stop condition detect ed. 1: s top condition detected (i f in slave mode) or pend - ing (if in master mode). 0: no stop condition is transmitt e d. 1: when configured as a master , causes a stop condition to be transmit - ted after the next ack cy cle. cleared by hardware. 3 ackrq smbus ackno wledge re que st. 0: no ack requested 1: ack requested n/a 2 arblost smbus arbitration lost in dic ator. 0: no arbitration error. 1: arbitration lost n/a 1 ack smbus acknowledge. 0: nack received. 1: ack received. 0: send nack 1: send ack 0 si smbus interrupt flag. this bit is set by hardware und er the conditions listed in table 15.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. 0: no interrupt pending 1: interrupt pending 0: clear interrupt, and initi - ate next state machine even t. 1: force interrupt.
rev. 0.3 397 si102x/3x 28.4.3. hardware slave address recognition the smbus hardware has the capability to automatically recognize incoming slav e addresses and send an ack without software intervention. automatic slave address recognition is enabled by setting the ehack bit in register smb0adm to 1. this will enable both automatic slave address recognition and automatic hardware ack generation for received bytes (as a mast er or slave). more detail on automatic hardware ack generation can be found in section 28.4.2.2 . the registers used to define which address(es) ar e r ecogn ized by the hardware are the smbus slave address register ( sfr definition 28.3 ) and the smbus slave address mask register ( sfr definition 28.4 ). a single address or range of addresses (including the general call address 0x00) can be specified using th es e two registers. the most-significant seven bits of the two registers are used to define which addresses will be acked. a 1 in bit pos itions of the slave address mask slvm[6:0] enable a comparison between the received slave address and the hardware?s sl ave address slv[6:0] for those bits. a 0 in a bit of the slave address mask means that bit will be treated as a ?don?t care ? for comparison purposes. in this case, either a 1 or a 0 value are acceptable on the in coming slave address. additionally, if the gc bit in register smb0adr is set to 1, hardware will recognize the genera l call address (0x00). ta b l e 28.4 shows some example parameter settings and the slave ad dress e s that will be recogni zed by hardware under those conditions. table 28.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by hardware when: master ? a s tart is generated. ? a st op is generated. ? ar bitration is lost. txm ode ? st art is generated. ? sm b0dat is written before the start of an smbus frame. ? a st art is detected. ? ar bitration is lost. ? smb 0dat is not written before the st art of an smbus frame. sta ? a st art followed by an address byte is received. ? m ust be cleared by software. st o ? a stop is detected while addressed as a slave. ? ar bitration is lost due to a detected stop. ? a pe nding stop is generated. ackrq ? a byte has been received and an ack r esponse value is needed (only when hard - ware ack is not enabled). ? af ter each ack cycle. arb lost ? a repeated start is detected as a master when st a is low (unwanted repeated start). ? scl is sensed low while attempting to gener - at e a stop or repeated start condition. ? s da is sensed low wh ile transmit ting a 1 (excluding ack bits). ? each time si is clea re d. ack ? the incoming ack value is low ? (ac knowledge). ? the incoming ack value is high (not acknow ledge). si ? a start has been generated. ? l ost arbitration. ? a byte ha s been transmitted and an ack/nack received. ? a byte ha s been received. ? a st art or repeated start followed by a slave ad dress + r/w has been received. ? a stop has been received. ? m ust be cleared by software.
si102x/3x 398 rev. 0.3 sfr page = 0x0; sfr address = 0xf4 table 28.4. hardware address recognition examples (ehack = 1) hardware slave address slv[6:0] slave address mask slvm[6:0] gc bit slave addresses recognized by hardware 0x34 0x7f 0 0x34 0x34 0x7f 1 0x34, 0x00 (general call) 0x34 0x7e 0 0x34, 0x35 0x34 0x7e 1 0x34, 0x35, 0x00 (general call) 0x70 0x73 0 0x70, 0x74, 0x78, 0x7c sfr definition 28.3. smb0adr: smbus slave address bit 7 6 5 4 3 2 1 0 name slv[6:0] gc type r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 : 1 slv[6:0] smbus hardware slave address. defines the smbus slave address(es) for automatic hardware acknowledgement. only address bits which have a 1 in the corresponding bit position in slvm[6:0] are checked against the incoming address. this allows multiple addresses to be recognized. 0 gc general call address enable. when hardware address reco gnition is enabled (ehac k = 1), this bit will deter - mine whether the general call address (0 x0 0) is also recognized by hardware. 0: general call ad dr es s is ignored. 1: general call address is recognized.
rev. 0.3 399 si102x/3x sfr page = 0x0; sfr address = 0xf5 sfr definition 28.4. smb0adm: smbus slave address mask bit 7 6 5 4 3 2 1 0 name slvm[6:0] ehack type r/w r/w reset 1111111 0 bit name function 7 : 1 slvm[6:0] smbus slave address mask. defines which bits of register smb0adr are compared with an incoming address by te, and which bits are ignored. any bit set to 1 in slvm[6:0] enables compari - sons with the corresponding bit in slv[6:0]. bit s set to 0 are ignored (can be either 0 or 1 in the incoming address). 0 ehack hardware acknowledge enable. enables hardware acknowledgement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled.
si102x/3x 400 rev. 0.3 28.4.4. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, a s the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted ou t msb first. af ter a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi - tration, the transition from master transmitter to slave r e ceiver is made with the correct data or address in smb0dat. sfr page = 0x0; sfr address = 0xc2 28.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames. note that the position of the ack interrupt when operating as a receiver depends on whether hardware ack generation is enabled . as a receiver, the inte rrupt for an ack occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack genera - tion is enabled. as a transmitter, interrupts occur af ter the ack, regardless of whether hardware ack gen - eration is enabled or not. 28.5.1. write se quence (master) during a write sequence, an smbus master wr ites data to a slave device. the master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. the smbus interface gener - ates the start condition and transmits the first byte cont a ining the address of the target slave and the data direction bit. in this case th e data direction bit (r/w) will be logic 0 (write). the master then trans - mits one or more bytes of serial data. after each byte is tr an smitted, an acknowledge bit is generated by the slave. the transfer is ended wh en the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not written following a master transm itter interrupt. sfr definition 28.5. smb0dat: smbus data bit 7 6 5 4 3 2 1 0 name smb0dat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7 : 0 smb0dat[7:0] smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus seri al interface or a byte that has just b een received on the smbus serial interface. the cpu can read from or write to this regi ster whenever the si serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu shou ld not attempt to access this register.
rev. 0.3 401 si102x/3x figure 28.5 shows a typical master write sequence. two tr an smit data bytes are shown, though any num - ber of bytes may be transmitted. all ?data byte transferred? interrupts occur af t er the ack cycle in this mode, regardless of whether hard ware ack generation is enabled. figure 28.5. typical master write sequence 28.5.2. read sequence (master) during a read sequence, an smbus ma ster reads data from a slave devic e. the master in this transfer will be a transmitter during the address byte, and a receiv er during all data bytes. the smbus interface gener - ates the start condition and transmits the first byte cont a ining the address of the target slave and the data direction bit. in this case t he data direction bit (r/w) will be logic 1 (read). serial data is then r e ceived from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received by te. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardwa re will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. writing a 1 to the ack bit generates a n ack; writing a 0 generates a nack. software should write a 0 to the ack bit for the last data transfer, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. the interface will switch to master transmitter mode if smb0dat is written while an active master receiver. figure 28.6 shows a typical master read sequence. two received data bytes are shown, though any number of bytes ma y b e received. the ?data byte trans - ferred? interrupts occur at different places in the sequ ence , depending on whether hardware ack genera - tion is enabled. the interrupt occurs bef ore the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
si102x/3x 402 rev. 0.3 figure 28.6. typical master read sequence 28.5.3. write sequence (slave) during a write sequence, an smbus ma ster writes data to a slave device. the slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direc - tion bit (write in this case) is r e ceived. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ac krq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generation is enabled, the hardware will apply the ac k for a slave address which matches the criteria set up by smb0adr and smb0adm. the inte rrupt will occur after the ack cycle. if the received slave address is ignore d (by sof tware or hardware), slav e interrupts will be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received by te. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardwa re will autom atically generate the ack/nack, and then post the interrupt. the appropriate ack or nack value shou ld be set up by the software prior to receiving the byte when hardware ack generation is enabled. the interface exits slave re ceiver mode af ter receiving a stop. note that the interface will switch to slave transmitter mode if smb0 dat is written while an active slave receiver. figure 28.7 shows a typical slave write sequence. two received data bytes are shown, though any number of bytes may be received. notice tha t the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
rev. 0.3 403 si102x/3x figure 28.7. typical slave write sequence 28.5.4. read se quence (slave) during a read sequence, an smbus ma ster reads data from a slave device. the slave in this transfer will be a receiver during the address byte, and a transm itter during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generat ion is enabled, the hardware will apply the ack for a slave address which matches the criteria set up by smb0adr and smb0adm. the interrupt will occur after the ack cycle. if the received slave address is ignore d (by sof tware or hardware), slav e interrupts will be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are trans - mitted. if the received slave address is acknowledged, data should be written to smb0dat to be transmit - ted. the interface enters slave transmitter mode, and tr a n smits one or more bytes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowle dge bit is a nack, smb0dat should not be written to before si is cleared (an error condition may be gen erated if smb0dat is wr itten following a received nack while in slave transmitter mo de). the interface exits slave transmitter mode after receiving a stop. note that the interface will switch to slav e receiver mode if smb0dat is not written following a slave transmitter interrupt. figure 28.8 shows a typical slave read sequence. two transmitted data bytes are shown, though any number of bytes may be transmitted. all of the ?data byte transferred? interrupts oc cur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
si102x/3x 404 rev. 0.3 figure 28.8. typical slave read sequence 28.6. smbus status decoding the current smbus status can be easily decoded usin g the smb0cn register. the appropriate actions to take in response to an smbus event depend on whether hardware slave address recognition and ack generation is enabled or disabled. ta b l e 28.5 describes the typical actions when hardware slave address recognition and ack generation is disabled. ta b l e 28.6 describes the typical actions when hardware slave address recognition and ack generation is enabled. in the t a bles, status vector refers to the four upper bits of smb0cn: master, tx mode, sta, and sto. the shown response options are only the typ - ical responses; application-specific procedures are allowed as lon g as they conform to the smbus specifi - cation. highlighted responses are allowed by hardwar e bu t do not conform to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
rev. 0.3 405 si102x/3x table 28.5. smbus status decoding with hardware ack generation disabled (ehack = 0) mode values read current smbus state typical response options values to wr i te next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener - ated. load slave address + r/w into smb 0 dat. 00x1100 11 0 0 000 a master data or address byte w a s transmitted; nack received. set sta to restart transfer. 10x1110 abort transfer. 01x - 001 a master data or address byte was transmitted; ack receiv ed. load next data byte into smb 0 dat. 00x1100 end transfer with stop. 01x - end transfer with stop and start an ot her transfer. 11x - send repeated start. 10x1110 switch to master receiver mode ( c lear si without writing new data to smb0dat). 0 0 x 1000 master receiver 1000 1 0 x a master data byte was r e ceived; ack requested. acknowledge received byte; read smb0dat . 0 0 1 1000 send nack to indi ca te last byte, and send stop. 010 - send nack to indi ca te last byte, and send stop followed by start. 1101110 send ack followed by repeated st ar t. 1011110 send nack to indi ca te last byte, and send repeated start. 1001110 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 1100 send nack and switch to mas - ter transmitter mode (write to smb0dat before clearing si). 0 0 0 1100
si102x/3x 406 rev. 0.3 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop co ndition). 0 0 x 0001 001 a slave byte was transmitted; ac k received. load smb0dat with next data byte to transmit. 0 0 x 0100 01 x a slave b yte was transmitted; err o r detected. no action required (expecting ma ster to end transfer). 0 0 x 0001 01 01 0 x x an illegal stop or bus error wa s de tected while a slave transmission was in progress. clear sto. 00x - slave receiver 0010 10x a slave address + r/w was r e ceived; ack requested. if write, acknowledge received ad dr ess 0 0 1 0000 if read, load smb0dat with d a ta byte; ack received address 0 0 1 0100 nack received address. 000 - 11 x l ost arbitration as master; s l ave address + r/w received; ack requested. if write, acknowledge received ad dr ess 0 0 1 0000 if read, load smb0dat with d a ta byte; ack received address 0 0 1 0100 nack received address. 000 - reschedule failed transfer; nack received addres s. 10 01110 00 01 00 x a stop was detected while a d dressed as a slave trans - mitter or slave receiver. clear sto. 00x - 11 x lost arbitration while attempt- ing a stop. no action required (transfer com p lete/aborted). 000 - 00 00 1 0 x a slave byte was received; ack re que sted. acknowledge received byte; read smb0da t . 0 0 1 0000 nack received byte. 000 - bus error condition 0010 0 1 x lost arbitration while attempt - ing a repeated start. abort failed transfer. 00x - reschedule failed transfer. 10x1110 00 01 0 1 x lost arbitration due to a detected st op . abort failed transfer. 00x - reschedule failed transfer. 10x1110 00 00 1 1 x lost arbitration while transmit - ting a data byte as master. abort failed transfer. 000 - reschedule failed transfer. 1001110 table 28.5. smbus status decoding with hardware ack generation disabled (ehack = 0) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
rev. 0.3 407 si102x/3x table 28.6. smbus status decoding with hardware ack generation enabled (ehack = 1) mode values read current smbus state typical response options values to wr i te next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener - ated. load slave address + r/w into smb 0 dat. 00x1100 11 0 0 000 a master data or address byte w a s transmitted; nack received. set sta to restart transfer. 10x1110 abort transfer. 01x - 001 a master data or address byte was transmitted; ack receiv ed. load next data byte into smb 0 dat. 00x1100 end transfer with stop. 01x - end transfer with stop and start an ot her transfer. 11x - send repeated start. 10x1110 switch to master receiver mode ( c lear si without writing new data to smb0dat). set ack for initial data byte. 0 0 1 1000 master receiver 1000 001 a master data byte was received; ack sent. set ack for next data byte; read smb0dat. 0 0 1 1000 set nack to indicate next data by te as the last data byte; read smb0dat. 0 0 0 1000 initiate repeated start. 1001110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 000 a master data byte was received; nack sent (last byte). read smb0dat; send stop. 010 - read smb0dat; send stop follo wed by st art. 1101110 initiate repeated start. 1001110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100
si102x/3x 408 rev. 0.3 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop co ndition). 0 0 x 0001 001 a slave byte was transmitted; ac k received. load smb0dat with next data byte to transmit. 0 0 x 0100 01 x a slave b yte was transmitted; err o r detected. no action required (expecting ma ster to end transfer). 0 0 x 0001 01 01 0 x x an illegal stop or bus error wa s de tected while a slave transmission was in progress. clear sto. 00x ? slave receiver 0010 00x a slave address + r/w was received; ack sent. if w rite, set ack for first data by te. 0 0 1 0000 if read, load smb0dat with da t a byte 0 0 x 0100 01 x l ost arbitration as master; s l ave address + r/w received; ack sent. if write, set ack for first data by te. 0 0 1 0000 if read, load smb0dat with da t a byte 0 0 x 0100 reschedule failed transfer 10x1110 00 01 00 x a stop was detected while a d dressed as a slave trans - mitter or slave receiver. clear sto. 00x ? 01 x lost arbitration while attempt- ing a stop. no action required (transfer com p lete/aborted). 000 ? 00 00 0 0 x a slave byte was received. set ack for next data byte; read smb0dat. 0 0 1 0000 set nack for next data byte; read smb0dat. 0 0 0 0000 bus error condition 0010 0 1 x lost arbitration while attempt - ing a repeated start. abort failed transfer. 00x ? reschedule failed transfer. 10x1110 00 01 0 1 x lost arbitration due to a detected st op . abort failed transfer. 00x ? reschedule failed transfer. 10x1110 00 00 0 1 x lost arbitration while transmit - ting a data byte as master. abort failed transfer. 00x ? reschedule failed transfer. 10x1110 table 28.6. smbus status decoding with ha rdware ack generation enabled (ehack = 1) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
rev. 0.3 409 si102x/3x 29. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enha nced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?29.1. enhanced baud rate generation? on page 410 ). received data buffering allows uart0 to start reception of a second incoming data byte be fore software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0) , or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). figure 29.1. uart0 block diagram uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set qd clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch)
si102x/3x 410 rev. 0.3 29.1. enhanced ba ud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 29.2 ), which is not user- accessible. both tx and rx timer overflows are divid ed b y two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is de t e cted on the rx pin. th is allows a receive to begin any time a start is detected, independent of the tx timer state. figure 29.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload (see section ?33.1.3. mode 2: 8-bit coun - ter/timer with auto-reload? on page 494 ). the timer 1 reload value should be set so that overflows will occur at two times the desired uart b aud rate fr equency. note that timer 1 may be clocked by one of six sources: sysclk, sysclk / 4, sysclk / 12, sy sclk / 48, the external oscillator clock / 8, or an exter - nal input t1. for any given timer 1 clock source, the uart0 baud rate is determined by equation -a and equation -b. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the hig h byte of timer 1 (reload value). timer 1 clock frequency is sele cte d as described in section ?33.1. timer 0 and timer 1? on page 493 . a quick reference for typical baud rates and system clock frequencies is given in ta b l e 29.1 through ta b l e 29.2 . note that the internal osc illator may still generate the s ystem clock when the external oscillator is driving timer 1. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart uartbaudrate 1 2 -- - t1_overflow_rate ? = t1_overflow_rate t1 clk 256 th1 ? ------------------------- - = a) b)
rev. 0.3 411 si102x/3x 29.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown below. figure 29.3. uart interconnect diagram 29.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx0 pin a nd received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins wh en s o ftware writes a data byte to th e sbuf0 register. the ti0 transmit inter - rupt flag (scon0.1) is set at the end of the transmi ssion ( t he beginning of the stop-bit time). data recep - tion can begin any time after the ren0 rece ive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over - run, the first received 8 bits are latched into the sbuf0 receive register and the following overrun data bits ar e lost. if these conditions are met, the eight bits of data is stor ed in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. figure 29.4. 8-bit uart timing diagram 29.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma - ble ninth data bit, and a stop bit. the state of the nint h transmit dat a bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg - ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit g oes into rb80 (scon0 .2) and the stop bit is ignored. or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space
si102x/3x 412 rev. 0.3 data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enab le bit (scon0.4) is set to 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the state of the ninth data bit is unimportant). if these cond itions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 flag is set to 1. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to 1. a uart 0 interrupt will occur if enabled when either ti0 or ri0 is set to 1. figure 29.5. 9-bit uart timing diagram 29.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of t he ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select th e target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor co n f igures its uart such that when a stop bit is received, the uart will gener ate an interrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address by te has been received. in the uart interrupt handler, software will compare the received address with the slave's own assigned 8-bit addre ss. if the addresses match, the slav e will clear its mce0 bit to enable interrupts on the reception of the following data byte (s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addres sed slave resets its mce0 bit to ignore all transmis - sions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and /o r a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8
rev. 0.3 413 si102x/3x figure 29.6. uart multi-processor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
si102x/3x 414 rev. 0.3 sfr page = 0x0; sfr address = 0x98; bit-addressable sfr definition 29.1. scon0: serial port 0 control bit 7 6 5 4 3 2 1 0 name s0mode mce0 ren0 tb80 rb80 ti0 ri0 type r/w r r/w r/w r/w r/w r/w r/w reset 01000000 bit name function 7 s0mode serial port 0 operation mode. selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. 6 unused read = 1b. write = don?t care. 5 mce0 multiprocessor comm unic a tion enable. for mode 0 (8-bit uart): ch ecks for vali d stop bit. 0 : logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. for mode 1 (9-bit uart): multip rocessor communica tions e n able. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is gene ra te d only when the ninth bit is logic 1. 4 ren0 receive enable. 0: uart0 reception disabled. 1: uart0 reception enabled. 3 tb80 ninth transmission bit. the logic level of this bit will be sent as th e ninth transmission bi t in 9-bit uart mode (mode 1). unused in 8-bit mode (mode 0). 2 rb80 ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th da t a bit in mode 1. 1 ti0 transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8- bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. 0 ri0 receive interrupt flag. set to 1 by hardware when a byte of data has been received by uart0 (set at the st op bit sa mpling time). when the uart0 in terrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart0 in terrupt service routine. this bit must be cleared manually by software.
rev. 0.3 415 si102x/3x sfr page = 0x0; sfr address = 0x99 sfr definition 29.2. sbuf0: serial (uart0) port data buffer bit 7 6 5 4 3 2 1 0 name sbuf0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 sbuf0 serial data buffer bits 7:0 (msb?lsb). this sfr accesses two registers; a transmit shift r egister and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 initiates the transm ission. a read of sbuf0 returns the contents of the receive latch.
si102x/3x 416 rev. 0.3 table 29.1. timer settings for standard baud rates using the internal 2 4.5 mhz oscillator frequency: 24.5 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from internal osc. 230400 ?0.32% 106 sysclk xx 2 1 0xcb 115200 ?0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 ?0.32% 848 sysclk/4 01 0 0x96 14400 0.15% 1704 sysclk/12 00 0 0xb9 9600 ?0.32% 2544 sysclk/12 00 0 0x96 2400 ?0.32% 10176 sysclk/48 10 0 0x96 1200 0.15% 20448 sysclk/48 10 0 0x2b notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 33.1 . 2. x = don?t care. table 29.2. timer settings for standard baud rates using an external 2 2.1184 mhz oscillator frequency: 22.1184 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 96 sysclk xx 2 10xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysc lk / 48 10 0 0x40
rev. 0.3 417 si102x/3x sysclk from internal osc. 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70 notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 33.1 . 2. x = don?t care. table 29.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator frequency: 22.1184 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex)
si102x/3x 418 rev. 0.3 30. enhanced serial pe ripheral interface (spi0) the enhanced serial peripheral interface (spi0) prov ides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul - tiple masters and slaves on a single spi b u s. the slave-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen - eral purpose port i/o pins can be used to se lec t multiple slave dev ices in master mode. figure 30.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien
rev. 0.3 419 si102x/3x 30.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 30.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat - ing as a master and an input when spi0 is operating as a slave. dat a is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 30.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave d e vice and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat - ing as a master and an output when spi0 is operating a s a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance stat e when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not select ed. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 30.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mast er device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen - erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is n o t selected (nss = 1) in 4-wire slave mode. 30.1.4. slave select (nss) the function of the slave-select (nss) signal is d epe ndent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire sl av e mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slav e device, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on the bus in 3-wire mode. this is intended for point- to-point communication between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-master mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operat ing as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of the nss signal disabl es the master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 operates in 4-wire mode, and nss is enabled as an output. the setting of nssmd0 determines wh at logic level the nss pin will output. this configuration should only be used wh en operating spi0 as a master device. see figure 30.2 , figure 30.3 , and figure 30.4 for typical connection diagra m s of the various operational modes. note tha t the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ?27. port input/output? on page 358 for general purpose port i/o and crossbar information. 30.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag
si102x/3x 420 rev. 0.3 is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb-fi rst into the master's shift register. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another mast er is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) are set to 0 to disable the spi master device, and a mode fault is generate d (modf, spi0cn.5 = 1). mode fault will gen erate an inte rrupt if e nabled. spi0 must be manually re-enabled in soft ware under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas - ter mode, slave devices can be addressed individua lly (if ne ede d) using general-purpose i/o pins. figure 30.2 shows a connection diagram between two ma ster devic e s in mu ltiple-master mode. 3-wire single-master mode is active when nssmd1 (s pi0cn.3) = 0 and nssmd0 ( spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 30.3 shows a connection diagram between a master dev ice in 3- wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi0c n.3) = 1. in this mode, nss is configured as an output pin, and can be used as a slave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit nssm d0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 30.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices.
rev. 0.3 421 si102x/3x figure 30.2. multiple-master mode connection diagram figure 30.3. 3-wire single master and 3-wire single slave mode connection diagram figure 30.4. 4-wire single master mode and 4-wire slave mode connection diagram 30.3. spi0 slave mode operation when spi0 is enabled and not confi gured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig - nal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been shifted through the shift reg - ister, the spif flag is set to logic 1, and the byte is co pied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss
si102x/3x 422 rev. 0.3 the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edg e of the next (or current) spi transfer. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabl ed when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a falling edge of n ss. note that the nss sig - nal must be driven low at least 2 system clocks before th e first a ctive edge of sck for each byte transfer. figure 30.4 shows a connection diagram between two slav e de vice s in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0cn. 3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 30.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 30.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: all of the following bits must be cleared by software. ? the spi interrupt flag, spif (spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. ? the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the tr ansmit buffer will not be written.this flag can occur in all spi0 modes. ? the mode fault flag modf (spi0cn.5) is set to logi c 1 when spi0 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logic 0 to disable spi0 and allow another master device to access the bus. ? the receive overrun flag rxovrn (spi0cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the rece ive buffer still holds an unread byte from a prev ious transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost. 30.5. serial clock phase and polarity four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0cfg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 30.5 . for slave mode, the clock and data relationships are shown in figure 30.6 and figure 30.7 . note that ckpha should be set to 0 on both the master and slave spi when communicat ing between tw o silicon labs c8051 devices. the spi0 clock rate register (spi0ckr) a s shown in sfr definition 30.3 controls the master mode serial clock frequency. this register is ignored when o per ating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the s ystem clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues sck, nss (in 4-
rev. 0.3 423 si102x/3x wire slave mode), and the serial input data synchrono usly with the slave?s system clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master i ssues sck, nss, and the serial inpu t data synchronously with the slave?s system clock. figure 30.5. master mode data/clock timing figure 30.6. slave mode data/clock timing (ckpha = 0) sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0)
si102x/3x 424 rev. 0.3 figure 30.7. slave mode data/clock timing (ckpha = 1) 30.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data re gister, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi
rev. 0.3 425 si102x/3x sfr page = 0x0; sfr address = 0xa1 sfr definition 30.1. spi0cfg: spi0 configuration bit 7 6 5 4 3 2 1 0 name spibsy msten ckpha ckpol slvsel nssin srmt rxbmt type r r/w r/w r/w r r r r reset 0 0 0 0 0 1 1 1 bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in p rogress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5 ckpha spi0 clock phase. 0: data centered on first edge of sck period. * 1: data centered on second edge of sck period. * 4 ckpol spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating spi 0 is the selected slave. it is cleared to logic 0 when nss is high (slave not sele cted). this bit does not indicate the instantaneous value at th e nss pin, but rather a de-glitched ver - sion of the pin input. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is pr esent on the nss port pin at the time that the register is read. this input is not de-glitched. 1 srmt shift register empty (valid in slave mode only). this bit will be set to logic 1 when all dat a has been tran sferred in/out of the shift register, and there is no new information avai lable to read from the transmit buffer or write to the receive buffer . it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. srmt = 1 when in master mode. 0 rxbmt receive buffer empty (valid in slave mode only). this bit will be set to logic 1 when the re ceive buf f er has been read and contains no new information. if there is new informatio n available in the receive buffer that has not been read, this bit will return to logic 0. rxbmt = 1 when in master mode. note: in slave mode, data on mosi is sampl ed in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum settling time for the slave device. see table 30.1 for timing parameters.
si102x/3x 426 rev. 0.3 sfr page = 0x0; sfr address = 0xf8; bit-addressable sfr definition 30.2. spi0cn: spi0 control bit 7 6 5 4 3 2 1 0 name spif wcol modf rxovrn nssmd[1:0] txbmt spien type r/w r/w r/w r/w r/w r r/w reset 0 0 0 0 0 1 1 0 bit name function 7 spif spi0 interrupt flag. this bit is set to logic 1 by hardware at th e end of a data transfer. if spi interrupts are enabled, an inte rrupt will be gene rated. this bit is not automatically cleared by hardware, and must be cleared by software. 6 wcol write collision flag. this bit is set to logic 1 if a write to spi0 da t is attempted when txbmt is 0. when this occurs, the write to spi0dat will be i gnored, and th e transmit buffer will not be written. if spi interrupts are enabled, an in terrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 5 modf mode fault flag. this bit is set to logic 1 by hardware w hen a master mode co llision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). if spi interrupts are enabled, an interrupt will be generat ed. this bit is not automatica lly cleared by hardware, and must be cleared by software. 4 rxovrn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware w hen the rec eive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the spi0 shift register. if spi inte rrupts are enabled, an interrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 3:2 nssmd[1:0] slave select mode. selects between the following nss operation modes: (see section 30.2 and section 30.3 ). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efau lt). nss is an input to the device. 1x: 4-wire single-master mode. nss sign al is ma ppe d as an output from the device and will assume the value of nssmd0. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new da t a has been written to the transmit buffer. when data in the transmit buff er is transferred to the spi shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spien spi0 enable. 0: spi disabled. 1: spi enabled.
rev. 0.3 427 si102x/3x sfr page = 0x0; sfr address = 0xa2 sfr page = 0x0; sfr address = 0xa3 sfr definition 30.3. spi0ckr: spi0 clock rate bit 7 6 5 4 3 2 1 0 name scr[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 scr[7:0] spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is co nfigur ed for master mode operation. the sck clock frequency is a divided ver - sion of the system clock, and is given in the following equation, where sysclk is th e system clock fre quency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, sfr definition 30.4. spi0dat: spi0 data bit 7 6 5 4 3 2 1 0 name spi0dat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 spi0dat[7:0] spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0da t places the data into the transmi t buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. f sck sysclk 2 spi0ckr[7:0] 1 + ?? ? ------------------- --------------------------------------- - = f sck 2000000 241 + ?? ? -------------------------- = f sck 200 khz =
si102x/3x 428 rev. 0.3 figure 30.8. spi master timing (ckpha = 0) figure 30.9. spi master timing (ckpha = 1) sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis
rev. 0.3 429 si102x/3x figure 30.10. spi slave timing (ckpha = 0) figure 30.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz
si102x/3x 430 rev. 0.3 table 30.1. spi slave timing parameters parameter description min max units master mode timing (see figure 30.8 and figure 30.9 ) t mckh sck high time 1 x t sysclk ? ns t mckl sck low time 1 x t sysclk ? ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing (see figu re 30.10 and figure 30.11 ) t se nss falling to first sck edge 2 x t sysclk ? ns t sd last sck edge to nss rising 2 x t sysclk ? ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ? ns t ckl sck low time 5 x t sysclk ? ns t sis mosi valid to sck sample edge 2 x t sysclk ? ns t sih sck sample edge to mosi change 2 x t sysclk ? ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change ? (ckpha = 1 only) 6 x t sysclk 8 x t sysclk ns note: t sysclk is equal to one per iod of the device syst em clock (sysclk).
rev. 0.3 431 si102x/3x 31. ezradiopro ? serial interface the ezradiopro serial interface (spi1) provides access to the ezradiopro peripheral registers from software executing on the mcu core. the serial interface consists of two spi peripherals: a dedicated spi master accessible from the mcu core and a dedicated spi slave residing inside the ezradiopro peripheral. the spi1 peripheral on the mcu core side can only be used in master mode to communicate with the ezradiopro slave device in three-wire mode . nss for the ezradiopro is provided using port 2.3, which is internally rout ed to the ezradiopro peripheral. figure 31.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien
si102x/3x 432 rev. 0.3 31.1. signal descriptions the four signals used by spi1 (mosi, miso, sck, nss) are described below. 31.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output to the mcu core. data is transferred most-signi ficant bit first. mosi is driven by the msb of the shift register. 31.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave d e vice and an input to the master device. it is used to serially transfer data from the ezradi opro to the mcu core. this signal is an input when spi1 is operating as a master and an output when spi1 is operating as a slave. data is transferred most- significant bit first. the miso pin is placed in a high-impedance state when the spi1 module is disabled. 31.1.3. serial clock (sck) the serial clock (sck) signal is an output from the master de vice and an input to the ezradiopro. it is used to synchronize the transfer of data between th e master and slave on the mosi and miso lines. spi1 generates this signal. 31.1.4. slave select (nss) to interface to the ezradiopro, spi1 operates in th re e- wire mode. the nss func tionality built into the spi state machine is not used. instead, the port pin p2.3 must be configured to control the chip select on the ezradiopro peripheral under software control.
rev. 0.3 433 si102x/3x 31.2. spi1 master mode operation a spi master device initiates all data transfers on a spi bus. spi1 is placed in master mode by setting the master enable flag (msten, spi1cn.6). writing a byte of data to the spi1 data register (spi1dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi1 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi1cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spi1 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb-fi rst into the master's shift register. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spi1dat. 31.3. spi slave operation on the ezradiopro peripheral side the ezradiopro peripheral presents a standard 4-wi re spi interface: sck, miso, mosi , and nss. the spi master can read data from the device on the mosi output pin. an spi transaction is a 16-bit sequence that consists of a read-write (r/w) select bit followed by a 7-bit address field (addr) and an 8-bit data field (data), as demonstrated in figure 31.2 . the 7-bit address field is used to select on e of the 128, 8-bit control registers. the r/w select bit determines whether the spi transaction is a read or write transaction. if r/ w = 1, it s ignifies a write trans a ction, while r/w = 0 signifies a read transaction. the contents (addr or data) are latched into the transceiver ever y eight clock cycles. the timing parameters for the spi interface are shown in ta b l e 31.1 . the sck rate is flexible w i th a maximum rate of 10 mhz. 31.4. spi1 interrupt sources when spi1 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: all of the following bits must be cleared by software. ? the spi interrupt flag, spif (spi1cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi1 modes. ? the write collision flag, wcol (spi1cn.6) is set to logic 1 if a write to spi1dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi1dat will be ignored, and the tr ansmit buffer will not be written.this flag can occur in all spi1 modes. ? the mode fault flag modf (spi1cn.5) is set to logi c 1 when spi1 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi1cn are set to logic 0 to disable spi1 and allow another master device to access the bus. ? the receive overrun flag rxovrn (spi1cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the rece ive buffer still holds an unread byte from a prev ious transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost.
si102x/3x 434 rev. 0.3 31.5. serial clock phase and polarity four combinations of serial clock phase and polarity ca n be selected using the clock control bits in the spi configuration register (spi1cfg). the ckpha bit (spi1cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi1cfg.4) se lects between an active-high or active-low clock. both ckpol and ckpha must be set to zero in order to communicate with the ezradiopro peripheral. the spi1 clock rate register (spi1ckr), as shown in sfr definition 31.3, controls the master mode serial clock frequency. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 mhz, whichever is slower. figure 31.2. master mode data/clock timing sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode)
rev. 0.3 435 si102x/3x 31.6. using spi1 with the dma spi1 is a dma-enabled peripheral that can provide au tonomous data transfers when used with the dma. the spi requires two dma channels for a bidirectional da ta transfer and also supports unidirectional data transfers using a single dma channel. there are no additional control bits in the spi1 cont r o l and configuration sfrs. the configuration is the same in dma and non-dma mode. while the spif flag a nd/or spi interrupts are normally used for non- dma spi transfers, a dma transfer is managed us ing the dma enable and dma full transfer complete flags. more information on using the spi1 peripheral with dma can be found in the detailed example code for ezradiopro. 31.7. master mode spi1 dma transfers the spi interface does not normally have any handshaking or flow co ntrol. therefore, the master will transmit all of the output data without waiting on t he slave peripheral. the system designer must ensure that the slave peripheral can accept all of the data at the transfer rate. 31.8. master mode bidi rectional data transfer a bidirectional spi master mode dma transfer will transmit a specified number of bytes out on the mosi pin and receive the same number of bytes on the mi so pin. the mosi data must be stored in xram before initiating the dma transfers. the dma will also transfer all the miso data to xram, overwriting any data at the target location. a bidirectional transfer requires two dma channels. t he first dma chan nel transfers data from xram to the spi1dat sfr and the second dma channel transfe rs data from the spi1dat sfr to xram. the sec - ond channel dma interrupt indica tes spi transfer completion. the nss pin is an output, and the hardware does no t man a ge the nss pin automatically. firmware should assert the nss pin before the spi transfer and deassert it upon completion of the transfer. to initiate a master mode bidirectional data transfer: 1. configure the spi1 sfrs normally for master mode. a . enable master mode by setting bit 6 in spi1cfg. b. configure the clock polarity (ckpol = 0) and clock phase (ckpha = 0) as desired in spi1cfg. c. configure spi1ckr for the desired spi clock rate. d. configure 3-wire master mode in spi1cn. e. enable the spi by setting bit 0 of spi1cn. 2. configure the first dma channel for the xram-to-spi1data transfer: a. disable the first dma channel by clearing the corresponding bit in dma0en. b. select the first dma chan nel by writing to dma0sel. c. configure the selected dma channel to use th e xram-to-spi1dat peripheral request by writing 0x03 to dma0ncf. d. write 0 to dma0nm d to disable wrapping. e. write the address of the first byte of master output (mosi) data to dma0nbah:l. f. write the size of the spi tran sfer in bytes to dma0nszh:l. g. clear the address offset sfrs cma0a0h:l. 3. configure the second dma channel for the spi1dat-to-xram transfer: a. disable the second dma channel by cl earing the corresponding bit in dma0en.
si102x/3x 436 rev. 0.3 b. select the second dma ch annel by writing to dma0sel. c. configure the selected dma channel to use th e spi1dat-to-xram peripheral request by writing 0x04 to dma0ncf. d. enable dma interrupts for the second channel by setting bit 7 of dma0ncf. e. write 0 to dma0nm d to disable wrapping. f. write the address for the first byte of master input (miso) data to dma0nbah:l. g. write the size of the spi tr ansfer in bytes to dma0nszh:l. h. clear the address offset sfrs cma0a0h:l. i. enable the interrupt on the second channel by setting the corresponding bit in dma0int. j. enable dma interrupts by setting bit 5 of eie2. 4. clear the interrupt bits in dma0int for both channels. 5. enable both channels by setting the correspondi ng bits in the dma0en sfr to initiate the spi transfer operation. 6. wait on the dma interrupt. 7. clear the dma enables in the dma0en sfr. 8. clear the dma interrup ts in the dma0int sfr.
rev. 0.3 437 si102x/3x 31.9. master mode unid irectional data transfer a unidirectional spi master mode dm a transfer will tran sfer a specified number of bytes out on the mosi pin. the mosi data must be stored in xram before initiating the dma transfers. the spi1dat-to-xram peripheral request is not used. since the dma does no t read the spi1dat sfr, the spi will discard the miso data. a unidirectional transfer only requires one dma channel to tr ansfer xram data to the spi1dat sfr. the dma interrupt will indicate the completion of the data transfer to the spi1dat sfr. when the interrupt occurs, the dma has written all of the data to the spi 1dat sfr, but the spi has not transmitted the last byte. firmware may poll on the spibsy bit to determine when the spi has transm itted the last byte. firm - ware should not deassert the nss pin until af ter th e spi has transmitted the last byte. to initiate a master mode un idir ecti onal data transfer: 1. configure the spi1 sfrs normally for master mode. a. enable master mode by setting bit 6 in spi1cfg. b. configure the clock polarity (ckpol = 0) and clock phase (ckpha = 0) as desired in spi1cfg. c. configure spi1ckr for the desired spi clock rate. d. configure 3-wire master mode in spi1cn. e. enable the spi by setting bit 0 of spi1cn. 2. configure the desired dma channel for the xram-to-spi1dat transfer. a. disable the desired dma channel by clearing the corresponding bit in dma0en. b. select the desired dma ch annel by writing to dma0sel. c. configure the selected dma channel to use the xram-to-spi1dat xram peripheral request by writing 0x03 to dma0ncf. d. enable dma interrupts for the desired channel by setting bit 7 of dma0ncf. e. write 0 to dma0nm d to disable wrapping. f. write the address for the first byte of master output (mosi) data to dma0nbah:l. g. write the size of the spi tr ansfer in bytes to dma0nszh:l. h. clear the address offset sfrs cma0a0h:l. i. enable the interrupt on the desired channel by setting the corresponding bit in dma0int. j. enable dma interrupts by setting bit 5 of eie2. 3. clear the interrupt bit in dma0int for the desired channel. 4. enable the desired channel by setting the corres ponding bit in the dma0en sfr to initiate the spi transfer operation. 5. wait on the dma interrupt. 6. clear the dma enables in the dma0en sfr. 7. clear the dma interrup ts in the dma0int sfr. 8. if desired, wait on the spibsy bit in spi1c fg for the last byte transfer to complete. 31.10. spi special function registers spi1 is accessed and controlled through four special function registers in the system controller: spi1cn control register, spi1dat data re gister, spi1cfg configuration register, and spi1ckr clock rate register. the four special function registers related to the operation of the spi1 bus are described in the following sfr definitions.
si102x/3x 438 rev. 0.3 sfr page = 0x2; sfr address = 0xa1 sfr definition 31.1. spi1cfg: spi1 configuration bit 7 6 5 4 3 2 1 0 name spibsy msten ckpha ckpol type r r/w r/w r/w r r r r reset 0 0 0 0 0 1 1 1 bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in p rogress (master or slave mode). 6 msten master mode enable. when set to ?1?, enables master mode. th is bit must be set to 1 to communicate with the ezradiopro peripheral. 5 ckpha spi1 clock phase. 0: data centered on first edge of sck period. * 1: data centered on second edge of sck period. * 4 ckpol spi1 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3:0 reserved. read = 0111, write = don't care. note: in master mode, data on miso is samp led one sysclk befo re the end of each data bit, to provide maximum settling time for the slave device. see ta b l e 31.1 for timing parameters.
rev. 0.3 439 si102x/3x sfr page = 0x2; sfr address = 0xf8; bit-addressable sfr definition 31.2. spi1cn: spi1 control bit 7 6 5 4 3 2 1 0 name spif wcol modf nssmd[1:0] txbmt spien type r/w r/w r/w r/w r/w r r/w reset 0 0 0 0 0 1 1 0 bit name function 7 spif spi1 interrupt flag. this bit is set to logic 1 by hardware at th e end of a data transfer. if spi interrupts are enabled, an inte rrupt will be gene rated. this bit is not automatically cleared by hardware, and must be cleared by software. 6 wcol write collision flag. this bit is set to logic 1 if a write to spi1 da t is attempted when txbmt is 0. when this occurs, the write to spi1dat will be i gnored, and th e transmit buffer will not be written. if spi interrupts are enabled, an in terrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 5 modf mode fault flag. this bit is set to logic 1 by hardware w hen a master mode co llision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). if spi interrupts are enabled, an interrupt will be generat ed. this bit is not automatica lly cleared by hardware, and must be cleared by software. 4 reserved. read = varies; write = 0. 3:2 nssmd[1:0] slave select mode. must be set to 00b. spi1 can only be used in 3-wire master mode. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new da t a has been written to the transmit buffer. when data in the transmit buff er is transferred to the spi shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spien spi1 enable. 0: spi disabled. 1: spi enabled.
si102x/3x 440 rev. 0.3 sfr page = 0x2; sfr address = 0xa2 sfr page = 0x2; sfr address = 0xa3 sfr definition 31.3. spi1ckr: spi1 clock rate bit 7 6 5 4 3 2 1 0 name scr[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 scr[7:0] spi1 clock rate. these bits determine the frequency of the sck output when the spi1 module is co nfigur ed for master mode operation. the sck clock frequency is a divided ver - sion of the system clock, and is given in the following equation, where sysclk is th e system clock fre quency and spi1ckr is the 8-bit value held in the spi1ckr register. for 0 <= spi1ckr <= 255 example: if sysclk = 2 mhz and spi1ckr = 0x04, sfr definition 31.4. spi1dat: spi1 data bit 7 6 5 4 3 2 1 0 name spi1dat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 spi1dat[7:0] spi1 transmit and receive data. the spi1dat register is used to transmit and receive spi1 data. writing data to spi1da t places the data into the transmi t buffer and initiates a transfer when in master mode. a read of spi1dat returns the contents of the receive buffer. f sck sysclk 2 spi1ckr[7:0] 1 + ?? ? ------------------- --------------------------------------- - = f sck 2000000 241 + ?? ? -------------------------- = f sck 200 khz =
rev. 0.3 441 si102x/3x figure 31.3. spi master timing (ckpha = 0) table 31.1. spi timing parameters parameter description min max units master mode timing (see figure 31.3 ) t mckh sck high time 1 x t sysclk ? ns t mckl sck low time 1 x t sysclk ? ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns note: t sysclk is equal to one per iod of the device syst em clock (sysclk). sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih
si102x/3x 442 rev. 0.3
rev. 0.3 443 si102x/3x 32. ezradiopro ? 240?960 mhz transceiver si102x/3x devices include the ezradiopro family of ism wireless transceivers with continuous frequency tuning over 240?960 mhz. the wide operating voltage range of 1.8?3.6 v and low current consumption ma kes the ezradiopro an ideal solution for battery powered applications. the ezradiopro transceiver operates as a time divi sion duplexing (tdd) transceiver where the device alternately transmits and receives data packets. th e device uses a single-con version mixer to downcon - vert the 2-level fsk/gfsk/ook modulated receive signal to a low if frequency. following a programma - ble gain amplifier (pga) the signal is converted to the digital domain by a high performance ?? adc allowing filtering, demodulati on, slicing, and packet handling to be performed in the built-in dsp increasing the receiver?s performance and flexibility versus ana log based architectures. th e demodulated signal is then output to the system mcu through a programmable gpio or via the standard spi bus by reading the 64-byte rx fifo. a single high precision local oscilla tor (lo) is used for both transmit and rec e ive modes since the transmit - ter and receiver do not operate at the same time. t he lo is ge nerated by an integrated vco and ?? frac - tional-n pll synthesizer. the synthesizer is designed to su pp ort configurable data rates, output frequency and frequency deviation at any frequency between 240?960 mhz. the transmit fsk data is modulated direc t ly into the ?? data stream and can be shaped by a ga ussian low-pass filter to reduce unwanted spectral content. the pa output power of the si1020/21/22/23/30/31 /32/33 de vices can be configured between ?1 and +20 dbm in 3 db steps, while the pa output power of th e si10 24/25/26/27/34/35/3 6/37 devices can be configured between ?8 and +13 dbm in 3 db steps. the pa is single-ended to allow for easy antenna ma tch ing and low bom cost. the pa incorporates au tomatic ramp-up and rampdown control to reduce unwanted spectral spreading. the devices with +20 dbm output power can also be used to compensate for the reduced performance of a lower cost, lower performance antenna or antenna with size constraints due to a small form-factor. competing solutions requ ire large and expensive exte rnal pas to achieve com - parable performance. the ezradiopro transceivers su ppo rt frequency hopping, tx/rx switch control, and antenna diversity switch control to exte nd the link range and improve performance. the ezradiopro peripheral also controls three gp io pins: gpio_0, gpio_1, and gpio_2. see applica - tion note ?an415: ezradiopro programming guide? fo r det ails on initializing and using the ezradiopro peripheral.
si102x/3x 444 rev. 0.3 32.1. ezradiopro operating modes the ezradiopro transceivers provide several operating modes which can be used to optimize the power consumption for a given application. depending upon the system communication protocol, an optimal trade-off between the radio wake time and power consumption can be achieved. ta b l e 32.1 summarizes the operating modes of the ezradi o p ro transceivers. in general, any given oper - ating mode may be classified as an active mode o r a power saving mode. the table indicates which block(s) are enabled (active) in each correspondin g mode. with the exception of the shutdown mode, all can be dynamically selected by sending the appropriate commands over the spi. an ?x? in any cell means that, in the given mode of operation, that bl ock can be independently programmed to be either on or off, without noticeably impacting the current cons umption. the spi circuit bl ock includes the spi inter - face hardware and the device register space. the 32 khz osc block includes the 32.768 khz rc oscilla - tor or 32.768 khz crystal oscillator and wake -up timer . aux (auxiliary blo cks) includes the temperature sensor, general purpose adc, and low-battery detector. table 32.1. ezradiopro operating modes mode name circuit blocks digital ldo spi 32 khz osc aux 30 mhz xt al pll pa rx i vdd shut - down off (regis - ter contents los t) off of f off off off off off 15 na standby on (register conten ts retained) on off off off off off off 450 na sleep on on x off off off off 1 a sensor on x on off off off off 1 a ready on x x on off off off 600 a tuning on x x on on off off 8.5 ma trans - mit on x x on on on off 30 ma* receive on x x on on off on 18.5 ma note: using si1024/25/26/27/ 34/35/36/37 at +13 dbm with recommended reference design. these power modes ar e for the ezradiopro peripheral only and are independent of the mcu power modes.
rev. 0.3 445 si102x/3x 32.1.1. operating mode control there are four primary states in the ezradiopro transceiver radio state machine: shutdown, idle, tx, and rx (see figure 32.1 ). the shutdown state completely shuts down the radio to minimize current consumption. there are five different configurations/ optio ns for the idle state which can be selected to optimize the chip for the application. "register 07h. operating mode and func tion control 1" controls which operating mode/state is sele cted with the exception of shutdown which is controlled by the sdn pin. the tx and rx state may be reached automatica lly from any of the idle states by setting the txon/rxon bits in "register 07h. oper ating mode and function control 1". ta b l e 32.2 shows each of the operating modes with the time required to reach eith er rx or tx mode as well as the current consumption of each mode. the transceivers include a low-power digital regulate d supply (lpld o) which is internally connected in parallel to the output of the main digital regulator (and is available externally at the vr_dig pin). this com - mon digital supply voltage is connected to all digital ci rcuit b l ocks including the digital modem, crystal oscil - lator, spi, and register space. the lpldo has extr eme l y low quiescent current consumption but limited current supply capability; it is used only in the idle-standby an d idle-sleep modes. the main digital regulator is automatically enabled in all other modes. figure 32.1. state machine diagram table 32.2. ezradiopro operating modes response time state/mode response time to current in state /mode [a] tx rx shut down state 16.8 ms 16.8 ms 15 na idle states: standby mode sleep mode sensor mode ready mode tune mode 800 s 800 s 800 s 200 s 200 s 800 s 800 s 800 s 200 s 200 s 450 na 1 a 1 a 800 a 8.5 ma tx state na 200 s 30 ma @ +13 dbm rx state 200 s na 18.5 ma shut dwn id le* tx rx *five different options for idle shutdown
si102x/3x 446 rev. 0.3 32.1.1.1. shutdown state the shutdown state is the lowest current consumption state of the device with nominally less than 15 na of current consumption. the shutdown state may be entered by driving the sdn pin high. the sdn pin sho uld be held low in all states except the shutdown state. in the shutdown state, the contents of the registers are lost and there is no spi access. when the chip is connected to the power supply, a po r will be initiated af ter the falling edge of sdn. after a por, the device will be in read y mode with the buffers enabled. 32.1.1.1.1. idle state there are five different modes in the idle state wh ich ma y b e selected by "regi ster 07h. operating mode and function control 1". all modes have a tradeoff between current consumption and response time to tx/rx mode. this tradeoff is shown in table 32.2 . after the por event, swreset, or exiting from the shutdown state the chip will default to the id le-read y mode. after a por event the inte rrupt registers must be read to properly enter the sleep, sensor, or standby mode and to control the 32 khz clock correc tly . 32.1.1.1.2. standby mode standby mode has the lowest current consumption of th e five idle states with only the lpldo enabled to maintain the register values. in this mode the registers can be accessed in both read and write mode. the standby mode can be entered by writing 0h to "register 07h. operating mo de and function control 1". if an interrupt has occurred (i.e., the nirq pin = 0) the interrupt registers must be read to achieve the minimum current consumption. additionally, the adc shou ld not be selected as an in put to the gpio in this mode as it will cause ex cess current consumption. 32.1.1.1.3. sleep mode in sleep mode the lpldo is enabled along with the w a ke-up-timer, which can be used to accurately wake-up the radio at specified intervals. see ?wake-up timer and 32 khz clock source? on page 479 for more information on the wa ke-up-t i mer. sleep mode is entered by setting enwt = 1 (40h) in "register 07h. ope rating mode and function control 1". if an interrupt has occurr ed (i.e., the nirq pin = 0) the inter - rupt registers must be read to achieve the minimu m cu rrent consumption. also, the adc should not be selected as an input to the gp io in this mode as it will ca use excess curr ent consumption. 32.1.1.1.4. sensor mode in sensor mode either the low batt e r y detector, temperature sensor, or both may be enabled in addi - tion to the lpldo and wake-up-timer. the low battery detector can be enabled by setting enlbd = 1 in "reg ister 07h. operating mode and function control 1". see ?temperature sensor? on page 476 and ?low battery detector? on page 478 for more information on these features. if an interrupt has occurred (i.e., the nirq pin = 0) the interrupt registers must be read to achieve the minimum current consumption. 32.1.1.1.5. ready mode ready mode is designed to give a fast transition ti me to tx mod e with reasonable current consumption. in this mode the crystal oscillator remains enabled reducing t he time required to switch to tx or rx mode by eliminating the crystal start-up time. ready mode is entered by setting xton = 1 in "register 07h. oper - ating mode and function control 1". t o achieve the lowest current consumpt ion state the crystal oscillator buffer should be disabled in ?register 62h. crystal oscillator control and tes t.? to exit ready mode, bufovr (bit 1) of this regist er must be set back to 0. 32.1.1.1.6. tune mode in tune mode the pll remains enabled in addition to the other blocks enabled in the idle modes. this will give the fas t est response to tx m ode as the pll will remain locked but it results in th e highest current consumption. this mode of operation is designe d for frequency hopping spread spectrum systems (fhss). tune mode is entered by setting pllon = 1 in "register 07h. operating mode and function con - trol 1". it is not necessary to set xt o n to 1 for this mode, the internal state machine automatically enables the crystal oscillator.
rev. 0.3 447 si102x/3x 32.1.1.2. tx state the tx state may be entered from any of the idle modes when the txon bit is set to 1 in "register 07h. operating mode and function control 1". a built-in sequenc er takes care of all the actions required to tran - sition between states from enabling the cry s tal oscillator to ramping up the pa. th e following sequence of events will occur automatically when going from standby mode to tx mode by setting the txon bit. 1. enable the main digital ldo and the analog ldos. 2. s tart up crystal oscillator and wait unt il ready (controlled by an internal timer). 3. enable pll. 4. calibrate vco (this action is skipped when the skipvco bit is 1, default value is 0). 5. wait until pll settles to required transmit frequency (controlled by an internal timer). 6. activate power amplifier and wait until power rampin g is completed (controlled by an internal timer). 7. transmit packet. steps in this sequence may be eliminated depending on which idle mode the chip is configured to prior to setting the txon bit . by default, the vco and pll are calibrated every time the pll is enabled. 32.1.1.3. rx state the rx state may be entered from any of the idle mo des wh en the rxon bit is se t to 1 in "register 07h. operating mode and function control 1". a built-in sequenc er takes care of all the actions required to tran - sition from one of the idle modes to the rx state. the follow i ng sequence of events will occur automati - cally to get the chip into rx mode when going from standby mode to rx mode by setting the rxon bit: 1. enable the main digital ldo and the analog ldos. 2. s tart up crystal oscillator and wait unt il ready (controlled by an internal timer). 3. enable pll. 4. calibrate vco (this action is skipped when the skipvco bit is 1, default value is 0). 5. wait until pll settles to required receive frequency (controlled by an internal timer). 6. enable receive circuits: lna, mixers, and adc. 7. enable receive mode in the digital modem. depending on the configurat ion of the radio all or so me of the following functions will be performed auto - matically by the digital modem: agc, af c (optional), update status regi sters, bit synchronization, packet handling (optional) including sync word, header check, and crc. 32.1.1.4. de vice status the operational status of the ezradiopro periphera l can be read from "register 02h. device status". 32.2. interrupts the ezradiopro peripheral is capa ble of generating an interrupt signal (nirq) when certain events occur. the nirq pin is driven low to indicate a pending interrupt request. the ezradiopro interrupt does not have an internal interrupt vector. to use the interrupt, the nirq pin must be looped back to an external interrupt input. this interrupt si gnal will be generated when any one (or more) of the inter- rupt events (corresponding to the interrupt s t atus bits) shown below o ccur. the nirq pin will remain low until the interrupt status register(s) (registers 03h?04h ) containing the active interrupt status bit is read. the nirq output signal will then be rese t until the next change in status is detected. the inte rrupts must be add r/w function/ description d7 d6 d5 d4 d3 d2 d1 d0 por def. 02 r device status ffovfl ffunfl rxffem headerr freqerr cps[1] cps[0] ?
si102x/3x 448 rev. 0.3 enabled by the corresponding enable bit in the in terrupt enable registers (registers 05h?06h). all enabled interrupt bits will be cleared when the corresponding interrupt stat us register is read. if the inter - rupt is not enabled when the event oc curs it will not trigger the nirq pin, but the status may still be read at anytime in the interrupt status registers. important note : the nirq line should not be monitored for por after sdn or initial power up. the por signal is available by default on gpio0 and gpio1 and should be monitored as an alternative to nirq for por. as an alternative, software may wait 18 ms after sdn rising before po lling the interrupt s t atus regis - ters in 03h and 04h to check for por and chip ready ( x tal start-up/ready). this process may take up to 26 ms. after the initial interrupt is c l eared, the operation of the nirq pin will be normal. see ?an440: ezradiopro detailed register descri pt ions? for a complete list of interrupts. 32.3. system timing the system timing for tx and rx modes is shown in figures 32.2 and 32.3 . the figures demonstrate tran - sitioning from standby mode to tx or rx mode thro ugh the b uilt-in sequencer of required steps. the user only needs to program the desi red mode, and the intern al sequencer will properl y transition the part from its current mode. the vco will automatically calibrate at every frequen cy chan ge or power up. the pll t0 time is to allow for bias settling of the vco. the pll ts time is for the settling time of the pll, which has a default setting of 100 s. the total time for pll t0, pll cal, and pll ts under all conditions is 200 s. under certain a pplicatio ns, the pll t0 time and the pll cal may be skipped for faster turn-around time. contact appli - cations support if faster turnaround time is desired. figure 32.2. tx timing add r/w function/ description d7 d6 d5 d4 d3 d2 d1 d0 por def. 03 r interrupt status 1 ifferr itxffafull itxffaem irxffafull iext ipksent ipkvalid icrcerror ? 04 r interrupt status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor ? 05 r/w interrupt enable 1 enfferr entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror 00h 06 r/w interrupt enable 2 enswdet enpreava enpreainval enrssi enwut enlbd enchiprdy enpor 01h tx packet xtal settling time pll t0 pll cal pllts 600us configurable 0-70us, default = 50us 50us, may be skipped pre pa ramp pa ramp up pa ramp down configurable 0-310us, recommend 100us 6us, fixed configurable 5-20us, recommend 5us configurable 5-20us, recommend 5us
rev. 0.3 449 si102x/3x figure 32.3. rx timing 32.3.1. frequency control for calculating the necessary frequen cy register settings it is reco mmended that customers use silicon labs? wireless design suite (wds ) or the ezradiopro register ca lculator worksheet (in microsoft excel) available on the product website. these meth ods offer a simple method to quickly determine the correct settings based on the application requirements. the following information can be used to calcu - lated these values manually. 32.3.2. frequency programming in order to receive or transmit an rf signal, the desired channel frequency, f carrier , must be programmed into the transceiver. note that this frequency is the center frequency of the desired channel and not an lo frequency. the carrier frequency is generated by a fractional-n synthesizer, using 10 mhz both as the ref - erence frequency and the clock of the (3 rd order) ? modulator. this modulator uses modulo 64000 accu - mulators. this design was made to obtain the desired frequency resolution of the synthesizer. the overall d i vision ratio of the feedback loop consist of an integer part (n) and a fractional part (f).in a generic sense, the output frequency of the synthesizer is as follows: the fractional part (f) is determined by three differ en t va lues, carrier frequency (fc[15:0]), frequency off - set (fo[8:0]), and frequency deviati on (fd[7:0]) . due to the fine resolution and high loop bandwidth of the synthesizer, fsk modulation is applied inside the loop and is done by varying f according to the incoming data; this is discussed further in ?frequency deviation? on page 452 . also, a fixed offset can be added to fine-tune the carrier frequency and counteract crystal tole ra nce errors. for simplicity assume that only the fc[15:0] register will determine the fractional component. the equation for selection of the carrier frequency is shown below: rx packet xtal settling time pll t0 pll cal pllts 600us configurable 0-70us, default =50us 50us, may be skipped configurable 0-310us, recommend 100us )(10 fnmhz f out u
si102x/3x 450 rev. 0.3 the integer part (n) is determined by fb[4:0]. additi onally, the output frequency can be halved by connect - ing a 2 divider to the output. this divider is not insi de the loo p and is controlled by the hbsel bit in "regis - ter 75h. frequency band select". this effectively partitions the entire 240?960 mhz frequency range into two sep a rate bands: high band (hb) for hbsel = 1, and low band (lb) for hbsel = 0. the valid range of fb[4:0] is from 0 to 23. if a higher value is written into the register, it will default to a val ue of 23. t he integer part has a fixed offset of 24 added to it as shown in the formula above. ta b l e 32.3 dem onstrates the selec - tion of fb[4:0] for the corresponding frequency band. after selection of the fb (n) the fractional compone nt may be solved with the following equation: fb and fc are the actual numbers stor e d in the corresponding registers. add r/w function/ description d7 d6 d5 d4 d3 d2 d1 d0 por def. 73 r/w frequency off set 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h 74 r/w frequency of f set 2 fo[9] fo[8] 00h 75 r/w frequency band select sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 35h 76 r/w nominal carrier fre quen cy 1 fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] bbh 77 r/w nominal carrier fre quen cy 0 fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h table 32.3. frequency band selection fb[4:0] value n frequency band hbsel=0 hbsel=1 0 24 240?249.9 mhz 480?499.9 mhz 1 25 250?259.9 mhz 500?519.9 mhz 2 26 260?269.9 mhz 520?539.9 mhz 3 27 270?279.9 mhz 540?559.9 mhz 4 28 280?289.9 mhz 560?579.9 mhz 5 29 290?299.9 mhz 580?599.9 mhz 6 30 300?309.9 mhz 600?619.9 mhz 7 31 310?319.9 mhz 620?639.9 mhz 8 32 320?329.9 mhz 640?659.9 mhz )()1(10 fn hbsel mhz f carrier ? ? ? ? ? ) 64000 ]0:15[ 24]0:4[(*)1(*10 fc fb hbsel mhz f tx ?? ? ? 64000*24]0:4[ )1(*10 ]0:15[ ? ? ? ? ? ? ? ? ?? ? ? fb hbsel mhz f fc tx
rev. 0.3 451 si102x/3x the chip will automatically shift the freq uency of the synthe sizer down by 937.5 khz (30 mhz 32) to ac hieve the correct intermediate frequency (if) when rx mode is entered. low-si de injection is used in the rx mixing architecture; therefore, no frequency reprogramming is required when using the same tx frequency and switching between rx/tx modes. 32.3.3. easy frequency programming for fhss while registers 73h?77h may be used to program the carrier fre q uency of the transcei ver, it is often easier to think in terms of ?channels? or ?channel numbers? rather than an absolute frequency value in hz. also, there may be some timing-critical applications (such as for frequency hopping sy stems) in which it is desirable to change frequency by programming a single re gister. once the channel step size is set, the fre - quency may be changed by a single register corresponding to the channel number. a nominal frequency is fir s t set using registers 73h?77h, as described abov e. registers 79h and 7ah are then used to set a chan - nel step size and channel number, relative to t he n o minal setting. the frequency hopping step size (fhs[7:0]) is set in increments of 10 khz with a maximum channel step size of 2.56 mhz. the frequency ho pp ing channel select register then selects channels based on multiples of the step size. for example: if the nomina l freq uency is set to 900 mhz using registers 73h?7 7h and the channel step size is set to 1 mhz using "register 7ah. frequency hopping s t ep size". for example, if the "register 79h. frequency hopping channel select" is set to 5d, the resulting carrier frequency would be 905 mhz. once the no minal frequency and channel step size are pr ogrammed in the registers, it is only necessary to program the fhch[7:0] register in order to change the frequency. 9 33 330?339.9 mhz 660?679.9 mhz 10 34 340?349.9 mhz 680?699.9 mhz 11 35 350?359.9 mhz 700?719.9 mhz 12 36 360?369.9 mhz 720?739.9 mhz 13 37 370?379.9 mhz 740?759.9 mhz 14 38 380?389.9 mhz 760?779.9 mhz 15 39 390?399.9 mhz 780?799.9 mhz 16 40 400?409.9 mhz 800?819.9 mhz 17 41 410?419.9 mhz 820?839.9 mhz 18 42 420?429.9 mhz 840?859.9 mhz 19 43 430?439.9 mhz 860?879.9 mhz 20 44 440?449.9 mhz 880?899.9 mhz 21 45 450?459.9 mhz 900?919.9 mhz 22 46 460?469.9 mhz 920?939.9 mhz 23 47 470?479.9 mhz 940?960 mhz table 32.3. frequency band selection (continued) )10]0:7[(]0:7[ khz fhch fhsfnom f carrier ? ? ? ?
si102x/3x 452 rev. 0.3 32.3.4. automatic state transition for frequency change if registers 79h or 7ah are changed in either tx or rx mode, the state machine will automatically transition the chip back to tune, change the frequency, and automatically go back to either tx or rx. this feature is useful to reduce the number of spi commands requ ired in a frequency hopping system. this in turn reduces microcontroller activity, reducing current consum ption. the exception to this is during tx fifo mode. if a frequency change is init iated during a tx packet, then the part will complete the current tx packet and will only change the fr equency for subs equent packets. 32.3.5. frequency deviation the peak frequency deviation is configurable from 0.625 to 320 khz. the frequency deviation ( ? f) is con t rolled by the frequency deviation register (fd), address 71 and 72h, and is independent of the carrier frequency setting. when enabled, regardless of the setting of the hbsel bit (high band or low band), the resolution of the frequency deviatio n will remain in increments of 625 hz. when using frequency modula - tion the carrier frequency will de v i ate from the nominal center channel carrier frequency by ? f: figure 32.4. frequency deviation the previous equation should be used to calculate th e desired frequency deviation. if desired, frequency modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center fre - quency; see ?modulation type? on page 455 for further details. add r/w function/ description d7 d6 d5 d4 d3 d2 d1 d0 por def. 79 r/w frequency hopping channe l select fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0] 00h 7a r/w frequency hopping ste p size fhs[7] fhs[6] fhs[5] fhs[4] fhs[3] fhs[2] fhs[1] fhs[0] 00h hz f fd 625 ]0:8[ ' ' f peak deviation = hz fdf 625]0:8[ u ' frequency f carrier time f
rev. 0.3 453 si102x/3x 32.3.6. frequency offset adjustment when the afc is disabled the frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. it is not possible to have both afc and offset as internally they share the same register. the fre - quency offset adjustment and the afc both are implemented by shifting the synthesizer local oscillator frequency. this register is a signed register so in or der to get a negative offset it is necessary to take the twos complement of the positive offset number. the offset can be calculated by the following: the adjustment range in high band is 160 khz and in low band it is 80 khz. for example to compute an of fse t of +50 khz in high band mode fo[9:0] should be set to 0a0h. for an offset of ?50 khz in high band mo de the fo[9:0] register should be set to 360h. 32.3.7. automatic frequency control (afc) all afc settings can be easily obtained from the se tting s calculator. this is the recommended method to program all afc settings. this sectio n is intended to describe the operation of the afc in more detail to help understand the trade-offs of using afc.the receiver supports automatic frequency control (afc) to compensate for frequency differences between the transmitter and receiver reference frequencies. these differences can be caused by the absolute accuracy and temperature dependencies of the reference crys - tals. due to frequency offset compensation in the modem, th e receiver is tolerant to frequency offsets up to 0.25 times the if bandwidt h when the afc is disabled. when the af c is enabled, the received signal will be centered in the pass-band of the if filter, providi ng optimal sensitivity and selectivity over a wider range of frequency offsets up to 0.35 times the if bandwidt h. the trade-off of receiver sensitivity (at 1% per) versus carrier offset and the im pact of afc ar e illustrated in figure 32.5 . add r/w function/ description d7 d6 d5 d4 d3 d2 d1 d0 por def. 71 r/w modulation mode contro l 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h 72 r/w frequency devia - tion fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] 20h add r/w function/ description d7 d6 d5 d4 d3 d2 d1 d0 por def. 73 r/w frequency offset fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h 74 r/w frequency offset fo[9] fo[8] 00h ]0:9[)1(25.156 fo hbselhz set desiredoff ? ? ? ? )1(25.156 ]0:9[ ?? ? hbselhz set desiredoff fo
si102x/3x 454 rev. 0.3 figure 32.5. sensitivity at 1% per vs. carrier frequency offset when afc is enabled, the preamble length needs to be long enough to settle the afc. in general, one byte of preamble is sufficient to settle the afc. dis abling the afc allows the pr eamble to be shortened from 40 bits to 32 bits. note that with the afc disabled, the preamble length must still be long enough to settle the receiver and to detect the preamble (see ?preamble length? on page 470 ). the afc corrects the detected frequency offset by changing the frequency of th e fr actional-n p ll. when the preamble is detected, the afc will freeze for the re mainder of the packet. in multi-packet mode the afc is reset at the end of every packet and will re-acquire the frequency offset for the next packet. the afc loop includes a bandwidth limiting mechanism improving the rejection of out of band signals. when the afc loop is enabled, its pull-in-range is determined by the bandwidt h limiter value (afclimiter) which is located in reg - ister 2ah. afc_pull_in_range = afclimiter[7:0] x (hbsel+1) x 625 hz the afc limiter register is an unsigned register and its value can be obtained from the ezradiopro reg - ister calculator spreadsheet. the amount of error correction feedback to the frac tiona l-n pll b efore the preamble is detected is con - trolled from afcgearh[2:0]. the default value 000 re la te s to a feedback of 100% from the measured fre - quency error and is advised for most applications. e very bit added will half the feedback but will require a longer preamble to settle. the afc operates as follows. the frequency error of th e incomin g signal is measured over a period of two bit times, after which it corrects the local oscillator via the fractional-n pl l. after this corr ection, some time is allowed to settle the fractional-n pll to the new frequency before the next frequency error is measured. the duration of the afc cycle before the preamble is detected can be programm ed with shwait[2:0]. it is advised to use the default value 001, which sets the afc cycle to 4 bit times (2 for measurement and 2 for settling). if shwait[2:0] is programmed to 3'b000, there is no afc correction output. it is advised to use the default value 001, which sets the afc cycle to 4 bit times (2 for measurement and 2 for settling). the afc correction value may be read from register 2bh. the value read can be converted to khz with the follow ing formula: afc co rrection = 156.25hz x (hbsel +1) x afc_corr[7: 0]
rev. 0.3 455 si102x/3x 32.3.8. tx data rate generator the data rate is configurable between 0.123?256 kbps. for data rates below 30 kbps the ?txdtrtscale? bit in regi ster 70h should be set to 1. when higher data rates are used this bit should be set to 0 . the tx date rate is determined by the following formula in bps: for data rates higher than 100 kbps, register 58h should be changed from its default of 80h to c0h. non- optimal modulation and increased eye closure will result if this setting is not made for data rates higher than 100 kbps. the txdr register is only applicable to tx mode and does not need to be programmed for rx mod e . the rx bandwidth which is partly determined from the data rate is programmed separately. 32.4. modulation options 32.4.1. modulation type the ezradiopro transceivers support three different modulation options: gaussian frequency shift key - ing (gfsk), frequency shift keying (fsk), and on-off keying (ook). gfsk is the recommended modu - lation type as it provides the best per for m ance and cleanest modulation spectrum. figure 32.6 demonstrates the difference between fsk and gfsk for a data rate of 64 kbps. the time domain plots d e monstrate the effects of the gaus sian filtering. the frequency doma in plots demonstrate the spectral benefit of gfsk over fsk. the type of modulation is selected with the modtyp[1:0 ] bits in "register 71h. modulation mode control 2". note that it is also possibl e to obtain an unmodulated carrier signal by setting modtyp[1:0] = 00. frequency correction rx tx afc disabled freq offset register freq offset register afc enabled afc freq offset register add r/w function/ desc ription d7 d6 d5 d4 d3 d2 d1 d0 por def. 6e r/w tx data rate 1 txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[10] txdr[9] txdr[8] 0ah 6f r/w tx data rate 0 txdr[7] txdr[6] txdr[5] txdr[4] txdr[3] txdr[2] txdr[1] txdr[0] 3dh modtyp[1:0] modulation source 00 unmodulated carrier 01 ook 10 fsk 11 gfsk (enable tx data clk when direct mode is used) dr_tx (bps) txdr 15:0 ?? 1 mhz ? 2 16 5 txdtrtscale ? + ------------------------------------------------- = txdr[15:0] dr_tx(bps) 2 16 5 txdtrtscale ? + ? 1 mhz -------------------------------------------------------------------------------- - =
si102x/3x 456 rev. 0.3 figure 32.6. fsk vs. gfsk spectrums 32.4.2. modulation data source the transceiver may be configured to obtain its modulat ion dat a from one of three different sources: fifo mode, direct mode, and from a pn9 mode. in direct mode, the tx modulation data may be obtained from several different input pins. these options are set through the dtmod[1:0] field in "register 71h. modulation mode control 2". 32.4.2.1. fifo mode in fifo mode, the transmit and receive data is stored in in tegr ated fifo regist er memory. the fifos are accessed via "register 7fh. fifo access," and are mo st efficiently accessed with burst read/write opera - tion. in tx mode, the data bytes stored in fifo memory a r e "packaged" together with other fields and bytes of information to construct the final transmit packet struct ure. these other potential fields include the pream - ble, sync word, header, crc checksum, etc. the configuration of the packet structure in tx mode is add r/w function/ description d7 d6 d5 d4 d3 d2 d1 d0 por def. 71 r/w modulation mode co ntrol 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h dtmod[1:0] data source 00 direct mode using tx/rx data via gpio pin (gpio configuration required) 01 direct mode using tx/rx data via sdi pin (only when nsel is high) 10 fifo mode 11 pn9 (internally generated) tx modulation time domain waveforms -- fsk vs. gfsk -1.0 -0.5 0.0 0.5 1.0 -1.5 1.5 sigdata_fsk[0,::] 50 100 150 200 250 300 350 400 450 050 0 -0.5 0.0 0.5 -1.0 1.0 time, usec sigdata_gfsk[0,::] tx modulation spectrum -- fsk vs gfsk (continuous prbs) -80 -60 -40 -100 -20 modspectrum_fsk -200 -150 -100 -50 0 50 100 150 200 -250 250 -80 -60 -40 -100 -20 freq, khz modspectrum_gfsk datarate 64000.0 txdev 32000.0 bt_filter 0.5 modindex 1.0
rev. 0.3 457 si102x/3x determined by the automatic packet handler (if enabled), in conjunction with a variety of packet handler registers (see ta b l e 32.4 on page 469 ). if the automatic packet handler is disabled, the entire desired packet structure should be loaded into fifo memory; no o ther fields (such as preamble or sync word are automatically added to the bytes stored in fifo memo ry). for further information on the configuration of the fifos for a specific application or packet size, see ?data handling and packet handler? on page 465 . in rx mode, only the bytes of the received packet st r u cture that are considered to be "data bytes" are stored in fifo memory. which bytes of the received packet are considered "data bytes" is determined by the automatic packet handler (if enabled), in co njunction with the packet handler registers (see ta b l e 32.4 on page 469 ). if the automatic packet handler is disabl e d , all bytes following the sync word are considered data bytes and are stored in fifo memory . t hus, even if automa tic packet handling operation is not desired, the prea mble detection threshold and sync word st ill need to be progra mmed so that the rx modem knows when to start filling data into the fifo. w hen the fifo is being used in rx mode, all of the received data may still be observed directly (in real-time) by properly pr ogramming a gpio pin as the rxdata output pin; this can be quite useful during application development. when in fifo mode, the chip w ill automatically exit the tx or rx s t ate when either the ipksent or ipkvalid interrupt occurs. the chip will return to the idle mode state progra mmed in "register 07h. operating mode and function control 1". for exam ple, the chip may be placed into tx mode by setting the txon bit, but with the pllon bit additionally se t. the chip will transmit all of the contents of the fifo and the ipksent interrupt will occur. when this interr upt event occurs, the chip will clea r the txon bit and return to tune mode, as indicated by the set state of the pllon bit. if no other bits are additionally set in register 07h (besides txon initially), then the chip will return to the standby state. in rx mode, the rxon bit will be clea red if ipkv alid occurs and the rxmp k bit (rx multi-packet bit, spi reg - ister 08h bit [4]) is not set. when the rxmpk bit is se t, the p art will not exit the rx state after successfully receiving a packet, but will remain in rx mode. the microcontroller will need to de cide on the appropriate subsequent action, depending upon information such as an interrupt gener ated by crc, packet valid, or preamble detect. 32.4.2.2. direct mode for legacy systems that perform packet handling within an mcu o r other baseband chip, it may not be desirable to use the fifo. for this scenario, a direct mode is provided which bypasses the fifos entirely. in tx direct mode, the tx modulation data is applied to an input pin of the chip and processed in "real time" (i.e., not stored in a register for transmission at a later time). a variety of pins may be configured for use as the tx data input function. furthermore, an additional pin may be required for a tx clock o utput function if gfsk modulation is desired (only the tx data input pin is required for f sk). two options for the source of the tx data are available in the dtmod[1:0] field, and various config urations for the source of the tx data clock may be selected through the trclk[1:0] field. the eninv bit in spi register 71h will in v e rt the tx data; this is most likel y useful for diagnostic and testing purposes. in rx direct mode, the rx data and rx clock can be programmed for direct (real-time) output to gpio pins. the microcontroller may then process the rx data without using the fifo or packet handler functions trclk[1:0] tx/rx data clock configuration 00 no tx clock (only for fsk) 01 tx/rx data clock is available via gpio (g pio ne eds pr ogramming accordingly as well) 10 tx/rx data clock is available via sdo pin (only when nsel is high) 11 tx/rx data clock is available via the nirq pin
si102x/3x 458 rev. 0.3 of the rfic. in rx direct mode, t he chip must still acquire bit timing dur ing the preamble, and thus the pre - amble detection threshold (spi regi ster 35h) must still be programmed. once the pr eamble is detected, certain bit timing functions within the rx modem chan ge their operation for op timized performance over the remainder of the packet. it is not required that a sync word be present in the packet in rx direct mode; however, if the sync word is absent then the skipsyn bi t in spi register 33h must be set, or else the bit tim - ing and tracking function within the rx mode m will not be configured fo r optimum performance. 3 2.4.2.3. direct synchronous mode in tx direct mode, the chip may be configured for synchr o nous or asynchronous modes of modulation. in direct synchronous mode, the rfic is configured to pr ovide a tx clock signal as an output to the external device that is providing the tx data stream. this tx clock signal is a square wave with a frequency equal to the programmed data rate. the external modulation so urce (e.g., mcu) must accept this tx clock sig - nal as an input and respond by providing one bit of tx d a ta back to the rfic, synchronous with one edge of the tx clock signal. in this fashion, the rate of the tx data input stream from the external source is con - trolled by the programmed data rate of the rfic; no tx data bits are made available at the input of the rfic un til requested by another cycle of the tx clock signal. the tx data bits supplied by the external source are transmitted directly in real-time (i.e., not stored internally for later transmission). all modulation types (fsk/gfsk/ook) are v a lid in tx direct synchron ous mode. as will be discussed in the next section, there are limits on modulati on types in tx direct asynchronous mode. 32.4.2.4. direct asynchronous mode in tx direct asynchronous mode, the rfic no longer c ontr o ls the data rate of the tx data input stream. instead, the data rate is controlled only by the exter nal tx data source; the rfic simply accepts the data applied to its tx data input pin, at whatever rate it is supplied. this means that there is no longer a need for a tx clock output signal from the rfic, as there is no synchronous "handshaking" between the rfic and the external data source. the tx data bits supplied by the external source are transmitted directly in real-time (i.e., not stored internally for later transmission). it is not necessary to program the data rate parameter when operating in tx direct asynchronous mode. the c hip still internally samples the incoming tx data stream to determi ne when edge transitions occur; however, rather than sampling the data at a pre-programmed data rate, the chip now internally samples the incoming tx data stream at its maximum possible oversampling rate . this allows the chip to accu - rately determine the ti min g of the bit edge transitions without prior knowledge of the data rate. (of course, it is still necessary to program the desired pea k frequency deviation.) only fsk and ook modulation types are valid in tx direct asynchronous mode; gfsk modulation is not av ailable in asynchronous mode. this is because the rfic does not have knowledge of the supplied data rate, and thus cannot determine the appropriate gaussi an lowpass filter function to apply to the incoming data.
rev. 0.3 459 si102x/3x figure 32.7. direct synchronous mode example figure 32.8. direct asynchronous mode example 32.4.2.5. direct mode using spi or nirq pins it is possible to use the ezradiopro serial interface signals and nirq as the modulation clock and data. the miso signal can be configured to be the data cl ock by programming trclk = 10. if the nss signal is low then the function of the miso sign al will be spi data output. if the nss signal is high and trclk[1:0] is 10 then during rx and tx modes the data clock will be available on the miso signal. if trclk[1:0] is set to 11 and no interrupts are enabled in registers 05 or 06h, then the nirq pin can also be used as the tx/rx data clock. note: the miso and nss signals are internal conn ectio n s. the nirq signal is accessed through an external package pin. the mosi signal can be configured to be th e data source in both rx and tx modes if dtmod[1:0] = 01. in a similar fashion, if nss is low th e mosi signal will function as spi data-i n. if nss is high then in tx direct synchronous modulation. full control over the serial interface & using interrupt. bitrate clock and modulation via gpio?s. gpio configuration gp1 : tx data clock output gp2 : tx data input dataclk mod(data) vdd_rf tx rxp rxn vdd_dig ant gpio_0 gpio_1 gpio_2 xin xout sdn nirq nc vr_dig matching px.x px.x px.x direct asynchronous fsk modulation. modulation data via gpio2, no data clock needed in this mode. gpio configuration gp2 : tx data input mod(data) vdd_rf tx rxp rxn ant gpio_0 gpio_1 gpio_2 xin xout sdn nirq nc vr_dig px.x matching vdd_dig px.x
si102x/3x 460 rev. 0.3 mode it will be the data to be modulated and transmitted. in rx mo de it will be the re ceived demodulated data. figure 32.9 demonstrates using mosi and mi so a s the tx/rx data and clock: figure 32.9. microcontroller connections if the miso pin is not used for data clock then it may be programmed to be the interrupt function (nirq) by programming register 0eh bit 3. 32.4.3. pn9 mode in this mode the tx data is generated internally us ing a p s eudorandom (pn9 sequence) bit generator. the primary purpose of this mode is for use as a test mode to observe the modula ted spectrum without having to provide data. 32.5. internal functional blocks this section provides an overview some of the key blocks of the internal radio architecture. 32.5.1. rx lna depending on the part, the input frequency range for the lna is between 240?960 mhz. the lna provides g a in with a noise figure low enough to suppress the no ise of the following stages. the lna has one step of gain control which is controlled by the analog gain control (agc) algorithm. the agc algorithm adjusts the gain of the lna and pga so the receiver can handle signal levels from sensitivity to +5 dbm with optimal p e rformance. in the si1024/25/26/27/34/35 /36/37 , the tx and rx may be tied di rectly. see the tx/rx direct-tie refer - ence design available on www.silabs.com. when the direct tie is u sed the lna_sw bit in register 6dh, tx power must be set. 32.5.2. rx i-q mixer the output of the lna is fed internally to the input o f th e receive mixer. the receive mixer is implemented as an i-q mixer that provides both i and q channel outputs to the programmable gain amplifier. the mixer consists of two double-balanced mixers whose rf inputs are driven in parallel, lo cal oscillator (lo) inputs are driven in quadrature, and separate i and q i ntermediate f requency (if) outputs drive the programma - ble gain amplifier. the receive lo signal is suppli e d by an integrated vco and pll synthesizer operating between 240?960 mhz. the necessary quadrature lo signals are de rived from the divider at the vco out - put. 32.5.3. programmable gain amplifier the programmable gain amplifier (pga) provides the necessary gain to boost the signal level into the d y namic range of the adc. the pga must also have en ough gain switching to allo w for large input signals to ensure a linear rssi range up to ?20 dbm. the pga has steps of 3 db which are controlled by the agc a l gorithm in the digital modem. nss mosi msi o spi input don?t care spi input tx on command tx mode mod input tx off command spi input don?t care rx on command rx mode rx off command data output spi input spi input spi output spi output spi output spi output spi output don?t care don?t care data clk output data clk output
rev. 0.3 461 si102x/3x 32.5.4. adc the amplified iq if signals are digitized using an a nalog-to-digital converter (a dc), which allows for low current consumption and high dynamic range. the ban dpass response of the adc provides exceptional rejection of out of band blockers. 32.5.5. digital modem using high-performance adcs allows ch an nel filterin g, image rejection, and demodulation to be performed in the digital domain, resulting in reduced area while increasing flexib ility. the digital mo dem performs the following functions: ? channel selection filter ? tx modulation ? rx demodulation ? agc ? preamble detector ? invalid preamble detector ? radio signal strength indicator (rssi) ? automatic frequency compensation (afc) ? packet handling including ezmac ? features ? cyclic redundancy check (crc) the digital channel filter an d demodulator are optimized for ultra lo w power consumption and are highly configurable. supported modulation types are gfsk, fsk, and ook. the channel filter can be configured to support bandwidths ranging from 620 khz down to 2.6 khz. a large variety of data rates are supported r ang ing from 0.123 up to 256 kbps. the agc algorithm is implemented d igitally using an advanced control loop optimized for fast response time. the configurable preamble detector is us ed to improve the reliability of the sync-word detection. the sync- word detector is only enabled when a valid preamble is detected, significantly reducing the probability of false detection. the received signal strength indicator (rssi) provides a measure of the signal strength received on the tuned channel. the resolution of the rssi is 0.5 db. this high resolution rssi enables accurate channel po we r measurements for clear channel assessment (cca ), carrier sense (cs), and listen before talk (lbt) functionality. frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital auto - matic frequency control (af c ) in receive mode. a comprehensive programmable packet handler including k e y features of silicon labs? ezmac is inte - grated to create a variety of communication topologies ranging from peer-to-peer networks to mesh net - works. the extensive programmability of the p a cket header allows for ad vanced packet filtering which in turn enables a mix of broadcast, group, and point-to-point communication. a wireless communication channel can be corrupted by noise and in terference, and it is therefore impor - tant to know if the received data is free of errors . a cy clic redundancy check (crc) is used to detect the presence of erroneous bits in each packet. a crc is computed and appended at the end of each transmit - ted packet and verified by the receiver to confirm th at no er rors have occurred. the packet handler and crc can significantly reduce the load on the micr ocontroller reducing the over all current consumption. the digital modem includes the tx modulator which converts the tx data bits into the corresponding stream of digit al modulation values to be summed wit h the fractional input to the sigma-delta modulator. this modulation approach results in highly accurate resolution of the frequency deviation. a gaussian filter is implemented to support gfsk, considerably reducin g the energy in the adjacent channels. the default bandwidth-time product (bt) is 0.5 for all programmed data rates, but it may be adjusted to other values.
si102x/3x 462 rev. 0.3 32.5.6. synthesizer an integrated sigma delta ( ? ) fractional-n pll synthesizer capable of operating from 240?960 mhz is pr ovided on-chip. using a ? synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing. the transmit modulation is applied directly to the loop in the digital domain through the fractional divider which results in very pr ecise accuracy and control over the transmit deviation. depending on the part, the pll and ' - 6 mod ulator scheme is designed to support any desired frequency and channel spacing in the range from 240?960 mhz with a frequency resolution of 156.25 hz (low band) o r 312 .5 hz (high band). the transmit data rate can be programmed between 0.123?256 kbps, and the fre q uency deviation can be programmed between 1?320 khz. these parameters may be adjusted via r egi sters as shown in ?frequency control? on page 449 . figure 32.10. pll synthesizer block diagram the reference frequency to the pll is 10 mhz. the pll utilizes a differenti al l-c vco, with integrated on- chip induc tors. the output of the vco is followed by a configurable divider which will divide down the sig - nal to the desired output frequency band. the modulus o f the variable divide-by-n divider stage is con - trolled dynamically by the output from the ' - 6 mod u lator. the tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of 312.5 hz anywhere in the range between 240? 96 0 mhz. 32.5.6.1. vco the output of the vco is automatically divided down to th e co rrect output frequency depending on the hbsel and fb[4:0] fields in "register 75h. frequency band select". in receive mode, the lo frequency is automatically shifted downwards by the if frequency of 937.5 khz, allowing transmit and receive operation o n the same frequency. the vco integrates the resonator inductor and tuning varactor, so no external vco components are required. the vco uses a capacitance bank to cover the wide frequenc y range sp ecified. the capacitance bank will automatically be calibrated every time the synthesizer is enabled. in certain fast hopping applications this might not be desirable so the vco calibration ma y be skipped by setting the appropriate register. n lpf cp pfd delta- sigma fref = 10 m vco tx modulation selectable divider tx rx
rev. 0.3 463 si102x/3x 32.5.7. power amplifier the si1020/21/22/23/30/31/32 /33 devices have an internal integrated power amplifier (pa) capable of transmitting at output levels between +1 and +20 dbm. the si1024/25/26/27/34 /35/36 /37 de vices have a pa which is capable of transmitting output levels between ?8 to +13 dbm. the pa design is single-ended a nd is implemented as a two stage class ce amplifier with a high efficiency when transmitting at maximum power. the pa efficiency can only be optimized at one power level. changing the output power by adjust - ing txpow[2:0] will scale both the output power and cu rrent but the ef ficiency will not remain constant. the pa output is ramped up and down to prevent unwanted spectral splatter. with the si1024/25/26/27/34 /35/36 /37 devices, the tx and rx may be tied directly. see the tx/rx direct- tie reference design available on the silicon labs website for more details. when the direct tie is used, the lna_sw bit in register 6dh, tx power must be set to 1. 32.5.7.1. output power selection the output power is configurable in 3 db steps with the txpow[2:0] field in "register 6dh. tx power". extra output power can allow the use of a cheaper smaller antenna, greatly reducing the overall bom cost. the higher power setting of the chip achieves maximum po ssible range, but of course comes at the cost of higher tx current consumption. howe ver, depending on the duty cycle of the system, the effect on battery life may be insignificant. add r/w function/ description d7 d6 d5 d4 d3 d2 d1 d0 por def. 6d r/w tx power reserved reserved reserved reserved lna_sw txpow[2] txpow[1] txpow[0] 18h txpow[2:0] si10x0/1 output power 000 +1 dbm 001 +2 dbm 010 +5 dbm 011 +8 dbm 100 +11 dbm 101 +14 dbm 110 +17 dbm 111 +20 dbm txpow[2:0] si10x2/3/4/5 output power 000 ?8 dbm 001 ?5 dbm 010 ?2 dbm 011 +1 dbm 100 +4 dbm 101 +7 dbm 110 +10 dbm 111 +13 dbm
si102x/3x 464 rev. 0.3 32.5.8. crystal oscillator the transceiver includes an integrated 30 mhz crystal oscillator with a fast start-up time of less than 600 s when a suitable parallel resonant cryst al is u sed. the design is differential with the required crystal load capacitance integrated on-chip to minimize the numb er of external components. by default, all that is required off-chip is the 30 mhz crystal. the crystal load capacitance can be digitally pr ogr am med to accommodate crystals with various load capacitance requirements and to adjust the frequency of the crystal oscilla tor. the tuning of the crystal load capacitance is programmed through the xlc[6:0] field of "register 09h. 30 mhz crystal oscillator load cap a citance". the total internal capacitance is 12.5 pf and is adjustable in approximately 127 steps (97ff/st ep). the xtalshift bit provides a coarse sh ift in frequency but is not binary with xlc[6:0]. the crystal frequency adjustment ca n be used to compensa te for cryst al production tolerances. utilizing the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal can be canceled. the typical value of the total on-chip capa cit ance cint ca n be calculated as follows: cint = 1.8 pf + 0.085 pf x xlc[6:0] + 3.7 pf x xtalshift note that the coarse shift bit xtalsh if t is no t binary with xlc[6:0]. the to tal load capacitance cload seen by the crystal can be calculated by adding the sum of all external parasitic pcb capacitances cext to cint. if the maximum value of cint (16.3 pf) is not sufficient, an external capacitor can be added for exact tuning. add i tional information on calculating cext and crystal selection guidelines is provided in ?an417: si4x3x family crystal oscillator.? if afc is disabled then the synthesizer frequency may be further adjusted by programming the frequency of fset field fo[9:0]in "register 73h. frequency offset 1" and "register 74h. frequency offset 2", as dis - cussed in ?frequency control? on page 449 . the crystal oscillator frequency is di vided down internally and may be out put to the microc ontroller through one of the gpio pins for use as the system clock. in th is fashion, only one crysta l oscillator is required for the entire system and the bom cost is reduced. the available clock frequencies and gpio configuration are discussed further in ?output clock? on page 474 . the transceiver may also be driven with an external 30 mhz clock signal through the xout pin. when dr ivin g with an external reference or using a tcxo, the xtal load capacitance register should be set to 0. 32.5.9. regulators there are a total of six regulators integrated onto the tr ansceiver . with the exception of the digital regulator, all regulators are designed to operate with only internal decoupling. the digital regulator requires an exter - nal 1 f de coupling capacitor. all regulators are designed to operate with an input supply voltage from +1.8 to +3.6 v. the output stage of the of pa is not connected internally to a regulator and is connected dir e ctly to the battery voltage. a supply voltage should only be connected to the v dd pins . no voltage should be forced on the digital reg - ulator output. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 09 r/w crystal oscillator load capa citance xtalshift xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] 7fh
rev. 0.3 465 si102x/3x 32.6. data handli ng and packet handler the internal modem is designed to operate with a packet including a 010101... preamble structure. to con - figure the modem to operate with packet formats without a pr ea mble or other legacy packet structures con - tact customer support. 32.6.1. rx and tx fifos two 64 byte fifos are integrated into the chip, one for rx and one for tx, as shown in figure 32.11 . "register 7fh. fifo access" is used to acce ss both fifos. a burst write to address 7fh will write data to the tx fifo. a burst read from address 7fh will read data from the rx fifo. figure 32.11. fifo thresholds the tx fifo has two programmable thresholds. an inte rrupt event occurs when the data in the tx fifo reaches these thresholds. the first thre shold is the fifo almost full threshol d, txafthr[5:0]. the value in this register corresponds to the desired threshold value in number of byte s. when the data be ing filled into the tx fifo crosses this threshold limit, an interrupt to the microcontroller is generated so the chip can enter tx mode to transmit the contents of the tx fifo. the second threshold for tx is the fifo almost empty threshold, txaethr[5:0]. when the data being shifted out of the tx fifo drops below the almost empty threshold an interrupt will be gener ated. if more data is not loaded into the fifo then the chip automatically exits the tx state afte r the ipksent interrupt occurs. the ch ip will return to the mode selected by the remaining bits in spi register 07h. for example, the chip may be placed into tx mode by setting the txon bit, but with the xton bit addi tionally set. for this condition, the chip will transmit all of the contents of the fifo and the ip ksent interrupt will occur. when this interrupt event occurs , the chip will clear the txon bit and return to ready mode, as indicated by the set st ate of the xton bit. if the pllon bit d1 is set when entering tx mode (i.e., spi register 07h = 0ah), the chip will exit from tx mode after sending the packet and return to tune mode. however, the chip will no t automatically return to st andb y mode upon exit from the tx state, in the event the tx packet is initiated by setting spi register 07h = 08h (i.e., setting only txon bit d3). the chip will instead return to ready mode, with the crystal oscillator remaining enabled. this is intentional; the sys - tem may be configured such that the host mcu derive s it s clock fr om the mcu_clk output of the rfic (through gpio2), and this clock signal must not be shut down without allowing the host mcu time to pro - cess any interrupt signals th a t may have occurred. the host mcu mu st subsequently perform a write to spi register 07h = 00h to enter standby mode and obtain minimum current consumption. tx fifo rx fifo rx fifo almost full threshold tx fifo almost empty threshold tx fifo almost full threshold
si102x/3x 466 rev. 0.3 the rx fifo has one programmable threshold called th e fifo almost full threshold, rxafthr[5:0]. when the incoming rx data crosses the almost full threshold an interrup t will be generated to the microcon - troller via the nirq pin. the microcontroller will then need to read the dat a from the rx fifo. both the tx and rx fifos may be cleared or reset with the ffclrtx and ffclrrx bits. all interrupts may be e nab led by setting the interrupt enabled bits in "regist er 05h. interrupt enable 1" and ?register 06h. inter - rupt enable 2.? if the in terrupt s are not enabled the function will not generate an interrup t on the nirq pin but the bits will still be read correctl y in the interrupt status registers. 32.6.2. packet configuration when using the fifos, automatic packet handling ma y b e enabled for tx mode, rx mode, or both. "reg - ister 30h. data access control" through ?register 4bh. received packet le ngth? control the configuration, status, and decoded rx packet data for packet hand ling. the usual fields for network communication (such as preamble, synchronization word, headers, packet length, and crc) can be configured to be auto - matically added to the data payload. the fields ne ede d for packet generation normally change infrequently and can therefore be stored in registers. automatica lly adding these fields to the data payload greatly reduces the amount of communication betw een the microcontroller and the transceiver. the general packet structure is shown in figure 32.12 . the length of each field is shown below the field. the preamble pattern is always a series of alternating one s an d zeroes, starting with a zero. all the fields have programmable lengths to accommodate different applications. the most common crc polynominals are available for selection. figure 32.12. packet structure an overview of the packet handler configuration registers is shown in table 32.4 . add r/w function/ desc ription d7 d6 d5 d4 d3 d2 d1 d0 por def. 08 r/w operating & function control 2 antdiv[2] antdiv[1] antdiv[0] rxmpk autotx enldm ffclrrx ffclrtx 00h 7c r/w tx fifo c ontrol 1 reserved reserved txaf thr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0] 37h 7d r/w tx fifo c ontrol 2 reserved reserved txae thr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0] 04h add r/w function/ description d7 d6 d5 d4 d3 d2 d1 d0 por def. 7e r/w rx fifo control reserved reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0] 37h data preamble sync word tx header packet length crc 1-255 bytes 1-4 bytes 0-4 bytes 0 or 1 byte 0 or 2 bytes
rev. 0.3 467 si102x/3x 32.6.3. packet handler tx mode if the tx packet length is set the packet handler will send the number of bytes in the packet length field before returning to idle mode and asserting the packet sent interrupt. to resume sending data from the fifo the microcontroller needs to comma nd the chip to re-enter tx mode. figure 32.13 provides an exam - ple transaction where the packet length is set to three bytes. figure 32.13. multiple packets in tx packet handler 32.6.4. packet handler rx mode 32.6.4.1. packet handler disabled when the packet handler is disabled certain fields in the rec eived pack et are still required. proper modem operation requires preamble and sync when the fifo is being used, as shown in figure 32.14 . bits after sync will be treated as raw data with no qualification. this mode allows fo r the creation of a custom packet handler when the automatic qualificat ion parameters are not sufficient. manchester encoding is supported but data whitening, crc, and header checks are not. figure 32.14. required rx packet structure with packet handler disabled 32.6.4.2. packet handler enabled when the packet handler is enabled, all the fields of the packet structure need to be configured. register cont ents are used to construct the header field and length information encoded into the transmitted packet when transmitting. the receive fifo can be configured to handle packets of fixed or variable length with or without a header. if multiple packets are desired to be stored in the fifo, then there are options available for the different fields that will be stored in to the fifo. figure 32.15 demonstrates the options and settings available when multiple p a ckets are enabled. figure 32.16 demonstrates the operation of fixed packet length and correct/incorrect packets. data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 data 9 } } } this will be sent in the first transmission this will be sent in the second transmission this will be sent in the third transmission preamble sync data
si102x/3x 468 rev. 0.3 figure 32.15. multiple packets in rx packet handler figure 32.16. multiple packets in rx with crc or header error register data register data fifo data h eader (s) l ength rx_multi_pk_en = 1 h data rx_multi_pk_en = 0 txhdlen = 0 txhdlen > 0 fixpklen fixpklen 0 1 01 data data data data l l h rx fifo contents: transmission: data l h data l h data l h data l h write pointer write pointer rx fifo addr. 63 0 rx fifo addr. 63 0 data l h write pointer rx fifo addr. 63 0 data l h data l h write pointer rx fifo addr. 63 0 crc error data l h data l h write pointer rx fifo addr. 63 0 initial state pk 1 ok pk 2 ok pk 3 error pk 4 ok
rev. 0.3 469 si102x/3x 32.6.5. data whitening, ma nchester encoding, and crc data whitening can be used to avoid extended sequence s of 0s or 1s in the transmitted data stream to achieve a more uniform spectrum. when enabled, the payload data bits are xored with a pseudorandom sequence output from the built-in pn9 generator. the gen erator is initialized at the beginning of the pay - load. the receiver recovers the original data by re pe ating this operation. manchester encoding can be used to ensure a dc-free transmission and good sync hronization properties. when manchester encoding is used, the effective datarate is unchanged but the actual datarate (preamble length, etc.) is doubled due to the nature of the encoding. the effective datarate when using manchester encoding is limited to 128 kbps. the implementation of manchester encoding is shown in figure 32.18 . data whitening and manchester encoding can be selected with "register 70h. modul a t ion mode control 1". the crc is configured via "register 30h. data access control". figure 32.17 demonstrates the portions of the p acket which have manchester encoding, data whitening, and crc applied. crc can be app lied to only the data portion of the packet or to the data, packet length and header fields. figure 32.18 provides an example of how the manchester encoding is done and also the use of the manchester invert (enmaniv) function. table 32.4. packet handler registers add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def 30 r/w data access control enpacrx lsbfrst crcdonly skip2ph enpactx encrc crc[1] crc[0] 8dh 31 r ezmac status 0 rxcrc1 pksrch pkrx pkvalid crcerror pktx pksent ? 32 r/w header control 1 bcen[3:0] hdch[3:0] 0ch 33 r/w header control 2 skipsyn hdlen[2] hdlen[1] hdlen[0] fixpklen synclen[1] synclen[0] prealen[8] 22h 34 r/w preamble length prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] prealen[0] 08h 35 r/w preamble detection control preath[4] preath[3] preath[2] preath[1] preath[0] rssi_off[2] rssi_off[1] rssi_off[0] 2ah 36 r/w sync word 3 sync[31] sync[30] sync[29] sync[28] sync[27] sync[26] sync[25] sync[24] 2dh 37 r/w sync word 2 sync[23] sync[22] sync[21] sync[20] sync[19] sync[18] sync[17] sync[16] d4h 38 r/w sync word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[10] sync[9] sync[8] 00h 39 r/w sync word 0 sync[7] sync[6] sync[5] sync[4] sync[3] sync[2] sync[1] sync[0] 00h 3a r/w transmit header 3 txhd[31] txhd[30] txhd[29] txhd[28] txhd[27] txhd[26] txhd[25] txhd[24] 00h 3b r/w transmit header 2 txhd[23] txhd[22] txhd[21] txhd[20] txhd[19] txhd[18] txhd[17] txhd[16] 00h 3c r/w transmit header 1 txhd[15] txhd[14] txhd[13] txhd[12] txhd[11] txhd[10] txhd[9] txhd[8] 00h 3d r/w transmit header 0 txhd[7] txhd[6] txhd[5] txhd[4] txhd[3] txhd[2] txhd[1] txhd[0] 00h 3e r/w transmit packet length pklen[7] pklen[6] pklen[5] pklen[4] pklen[3] pklen[2] pklen[1] pklen[0] 00h 3f r/w check header 3 chhd[31] chhd[30] chhd[29] chhd[28] chhd[27] chhd[26] chhd[25] chhd[24] 00h 40 r/w check header 2 chhd[23] chhd[22] chhd[21] chhd[20] chhd[19] chhd[18] chhd[17] chhd[16] 00h 41 r/w check header 1 chhd[15] chhd[14] chhd[13] chhd[12] chhd[11] chhd[10] chhd[9] chhd[8] 00h 42 r/w check header 0 chhd[7] chhd[6] chhd[5] chhd[4] chhd[3] chhd[2] chhd[1] chhd[0] 00h 43 r/w header enable 3 hden[31] hden[30] hden[29] hden[28] hden[27] hden[26] hden[25] hden[24] ffh 44 r/w header enable 2 hden[23] hden[22] hden[21] hden[20] hden[19] hden[18] hden[17] hden[16] ffh 45 r/w header enable 1 hden[15] hden[14] hden[13] hden[12] hden[11] hden[10] hden[9] hden[8] ffh 46 r/w header enable 0 hden[7] hden[6] hden[5] hden[4] hden[3] hden[2] hden[1] hden[0] ffh 47 r received header 3 rxhd[31] rxhd[30] rxhd[29] rxhd[28] rxhd[27] rxhd[26] rxhd[25] rxhd[24] ? 48 r received header 2 rxhd[23] rxhd[22] rxhd[21] rxhd[20] rxhd[19] rxhd[18] rxhd[17] rxhd[16] ? 49 r received header 1 rxhd[15] rxhd[14] rxhd[13] rxhd[12] rxhd[11] rxhd[10] rxhd[9] rxhd[8] ? 4a r received header 0 rxhd[7] rxhd[6] rxhd[5] rxhd[4] rxhd[3] rxhd[2] rxhd[1] rxhd[0] ? 4b r received packet length rxplen[7] rxplen[6] rxplen[5] rxplen[4] rxplen[3] rxplen[2] rxplen[1] rxplen[0] ?
si102x/3x 470 rev. 0.3 figure 32.17. operation of data whitening, manchester encoding, and crc figure 32.18. manchester coding example 32.6.6. preamble detector the ezradiopro transceiver has integrated automa tic preamble detection. the preamble length is con - figurable from 1?255 bytes using the p r ealen[7:0] field in "register 33 h. header control 2" and "register 34h. preamble length", as described in ?32.6.2. packet co nfigu ration? . the preamble detection threshold, preath[4:0] as set in "reg ister 35 h. preamble detection control 1", is in units of 4 bits. the preamble detector searches for a preamble pa ttern with a length of preath[4:0]. if a false preamble detect occurs, the receiver will continui ng s earching for the preamble when no sync word is detected. once pr eamble is detected (false or real) then the part will th en start searching for sync. if no sync occurs then a timeout will occur and the devi ce will initiate search for preamble again. the time - out period is defined as the sync word length plus four bit s and will star t after a non-preamble pattern is recognized after a valid preamble detection. the pr eamble detector output may be programmed onto one of the gpio or read in the interrupt status registers. 32.6.7. preamble length the preamble detection threshold determines the number of valid preamble bits the radio must receive to qualify a valid preamble. the preamble threshold should be adjusted depending on the nature of the appli - cation. the required preamble length thres h old will depend on when receive mode is entered in relation to the start of the transmitted packet and the length of the transmit preamble. with a shorter than recom - mended preamble detection th reshold the probability of fa lse detec tion is directly related to how long the receiver operates on noise before the transmit preamb le is received. false dete ction on noise may cause the actual packet to be missed. the preamble detection threshold is programmed in register 35h. for most applications with a preamble length longer than 32 bi ts the default value of 20 is recommended for the pre - preamble sync header/ address pk length data crc crc (over data only) crc whitening manchester data before mancheste r data after machester ( manppol = 1, enmaninv = 0) data after machester ( manppol = 1, enmaninv = 1) data before manchester data after machester ( manppol = 0, enmaninv = 0) data after machester ( manppol = 0, enmaninv = 1) 111 11111 0 0001 000 0000 0 preamble = 0xff first 4bits of the synch. word = 0x2 preamble = 0x00 first 4bits of the synch. word = 0x2 0001 0
rev. 0.3 471 si102x/3x amble detection threshold. a shorter preamble detection threshold may be chosen if occasional false detections may be tolerated. when antenna diversity is enabled a 20-bit preamble detection threshold is recommended. when the receiver is synchronously enabled just before the start of the packet, a shorter preamble detection threshold may be used. ta b l e 32.5 demonstrates the recommended preamble detec - tion threshold and preamble length for various modes. it is possible to use the transceiver in a raw mode without the requirement for a 010101... preamble. con - tact customer support for further details. note: the recommended preamble length and preamble detecti on threshold listed above are to achieve 0% per. they may be shortened when occasional packet errors are tolerable. 32.6.8. invalid preamble detector when scanning channels in a frequency hopping system it is desirable to determine if a channel is valid in the minimum amount of time. the preamble detector ca n output an invalid preamble detect signal. which can be used to identify the channel as inva lid. after a configurable time set in register 60h[7:4], an invalid p r eamble detect signal is asserted indicating an invalid channel. the period for evaluating the signal for invalid preamble is defined as (inv_pre_th[3:0] x 4) x bit rate period. the preamble detect and invalid pre - amble detect signals are available in "register 03h. in ter r upt/status 1" and ?register 04h. interrupt/status 2.? 32.6.9. synchronization word configuration the synchronization word length for both tx and rx can be configured in reg 33h, synclen[1:0]. the expected or transmitted sync word can be configured from 1 to 4 bytes as defined below: ? synclen[1:0] = 00?expected/transmitted synchronization word (sync word) 3. ? synclen[1:0] = 01?expected/transmitted synchroniz ation word 3 first, fo llowed by sync word 2. ? synclen[1:0] = 10?expected/transmitted synchronizat ion word 3 first, followed by sync word 2, followed by sync word 1. ? synclen[1:0] = 1?send/expect synchron ization word 3 first, followed by sync word 2, followed by sync word 1, followed by sync word 0. the sync is transmitted or expected in the following sequence: sync 3 o sync 2 o sync 1 o sync 0. the sync word values can be programmed in registers 36h?39h. afte r preamble detection t he part will search for sync for a fixed period of time. if a sync is not recognized in this period then a timeout will occur and the search for preamble will be re-initiated. the timeout period after pr eamble detections is defined as the value programmed into the sync word length plus four additional bits. table 32.5. minimum receiver settling time mode approximate receiver settling t i me recommended preamble length with 8-bit detec tion threshold recommended preamble le ngth with 20-bit detection threshold (g)fsk afc disabled 1 byte 20 bits 32 bits (g)fsk afc enabled 2 byte 28 bits 40 bits (g)fsk afc disabled +an t enna diversity enabled 1 byte ? 64 bits (g)fsk afc enabled +an t enna diversity enabled 2 byte ? 8 byte ook 2 byte 3 byte 4 byte ook + antenna diversity en able d 8 byte ? 8 byte
si102x/3x 472 rev. 0.3 32.6.10. receive header check the header check is designed to support 1?4 bytes and broadcast headers. the header length needs to be set in register 33h, hdlen[2:0]. the headers to be checked need to be set in register 32h, hdch[3:0]. for instance, there can be four bytes of header in the packet structure but only one byte of the header is set to be checked (i.e., header 3). for the headers that are se t to be checked, the expe cted value of the header should be programmed in chhd[31:0] in registers 3f?42. the individual bits within the selected bytes to be checked can be enabled or disabled with the header en ables, hden[31:0] in regist ers 43?46. for example, if you want to check all bits in header 3 then hden[31: 24] should be set to ff but if only the last 4 bits are desired to be checked then it should be set to 00001111 (0f). broadcast headers can also be programmed by setting bcen[3:0] in register 32h. for broadcast header check the value may be either ?ffh? or the value stored in the check header register. a logic equi valent of the header check for header 3 is shown in figure 32.19 . a similar logic check will be done for header 2, header 1, and he ader 0 if enabled. figure 32.19. header 32.6.11. tx retransmission and auto tx the transceiver is capable of automatically retransmitti ng the last packet loaded in the tx fifo. automatic retransmission is set by entering the tx state with the txon bit without reloading the tx fifo. this feature is useful for beacon transmission or when retransm ission is required due to the absence of a valid acknowledgement. only packets that fit completely in the tx fifo can be automatically retransmitted. an automatic transmission function is available, allowi n g the radio to automatically start or stop a transmis - sion depending on the amount of data in the tx fifo. when autotx is set in ?register 08 . operating & function control 2", the transceiver will automatically enter the tx state when the tx fifo almost full threshold is exceeded. packets will be transmitted according to the configured packet length. to stop transmitting, clea r the packet sent or tx fifo almost empty inter - rupts must be cleared by reading register. bit wise rxhd[31:24] bit wise chhd[31:24] hden[31:24] = ffh hdch[3] header3_ok example for header 3 equivalence comparison = rxhd[31:24] equivalence comparison bcen[3]
rev. 0.3 473 si102x/3x 32.7. rx modem configuration a microsoft excel parameter calculator or wireless development suite (wds) calculator is provided to determine the proper settings for the modem. the calculator can be found on www.silabs.com or on the cd provided with the demo kits. an application note is av aila ble to describe how to use the calculator and to provide advanced descriptions of th e mod em settings and calculations. 32.7.1. modem settings for fsk and gfsk the modem performs channel selection and demodulation in the digital domain. the channel filter band - width is configurable from 2.6 to 620 khz. the receiver data-rate, modulation index, and bandwidth are set via re gisters 1c?25h. the modulation index is equal to 2 times the peak deviation divided by the data rate (rb). when manchester coding is disabled, the required channe l filter bandwid th is calculated as bw = 2fd + rb where fd is the frequency deviation and rb is the data rate. 32.8. auxiliary functions the ezradiopro has some auxiliary functions that duplicate the directly accessible mcu peripherals: adc, temperature sensor, and 32 khz oscillator. these auxiliary functi ons are ret a ined primarily for com - patibility with the si4430/1 /2. the directl y accessed mcu peripherals typically provide lower system cur - rent consumption and better analo g performanc e. h owever some of these ezradiopro auxiliary functions offer features not directly duplicated in t he mcu directly accessed peripherals, such as the low duty cycle mode operation. 32.8.1. smart reset the ezradiopro transceiver contains an enhanced integrated smart reset or por circuit. the por circuit contains both a classic level threshold reset as well as a slope de tector por. this reset circuit was designed to produce a reliable reset si gnal under any circumstan ces. reset will be initia ted if any of the fol - lowing conditions occur: ? initial power on, v dd starts from gnd: reset is active till v dd reaches v rr (see table); ? when v dd decreases below v ld for any reason: reset is active till v dd reaches v rr ; ? a software reset via ?register 08h. operating mode and function control 2?: reset is active for time t swrst ? on the rising edge of a v dd glitch when the supply voltage exceeds the following time functioned limit: figure 32.20. por glitch parameters reset t p t=0, vdd starts to rise t vdd(t) reset: vglitch>=0.4+t*0.2v/ms actual vdd(t) showing glitch reset limit: 0.4v+t*0.2v/ms vdd nom. 0.4v
si102x/3x 474 rev. 0.3 the reset will initialize all registers to their default values. the reset sign al is also availa ble for out put and use by the microcontroller by using the default setting fo r gpio_0. the inverted reset signal is available by default on gpio_1. 32.8.2. output clock the 30 mhz crystal oscillator frequency is divided down internally and may be output on gp io2. this fea - ture is useful to lower bom cost by using only one cryst al in the syst em. the output clock on gpio2 may be routed to the xtal2 input to provide a synchron ized clock source between the mcu and the ezradio - pro peripheral. the output clock frequency is selectabl e fro m one of 8 options, as shown below. except for the 32.768 khz option, all other frequencies are derived by dividing the cr ystal oscillator frequency. the 32.768 khz clock signal is derived from an in ternal rc os cillator or an external 32 khz crystal. the default setting for gpio2 is to output the clock signal with a frequency of 1 mhz. since the crystal oscillator is disa bled in sleep mode in order to sa ve current, the l o w-power 32.768 khz clock can be automatically switched to become the out put clock. this feature is called enable low fre - quency clock and is enabled by the enlfc bit in ?register 0ah. microcontroller output clock." when enlfc = 1 an d the chip is in sleep mode then the 32.768 khz clock will be provided regardless of the setting of mclk[2:0]. for example, if mclk[2:0] = 000, 30 mhz will be provided through the gpio output pin in all idle, table 32.6. por parameters parameter symbol comment min typ max unit release reset voltage vrr 0.85 1.3 1.75 v power-on v dd slope svdd tested v dd slope region 0.03 ? 300 v/ms low v dd limit vld vld rev. 0.3 475 si102x/3x tx, or rx states. when the chip enters sleep mode, the output cl ock will automatically switch to 32.768 khz from the rc oscillator or 32.768 xtal. another available feature for the output cloc k is the c lock tail, clkt[1:0] in ?register 0ah. microcontroller output clock." if the low frequency cl ock feature is not enabled (enlfc = 0), then the output is disabled in sleep mode. setting the clkt[1:0] field will provide additional cycles of the output clock befo re it shuts off. if an interrupt is trigger ed, the output clock will remain enabled regardless of the selected mode. as soon as the interrupt is read the state machine will then move to the selected mode. the minimum current con - sumption will not be achieved until the interrupt is read . for inst ance, if the ezradiopro peripheral is commanded to sleep mode but an interrupt has occurred the 30 mhz xtal will not be disabled until the in te rrupt has been cleared. 32.8.3. general purpose adc the ezradiopro peripheral includes an 8-bit sar adc independent of adc0. it may be used for general purpose analog sampling, as well as for digitizing th e ezradiopro temperature se nsor reading. in most cases, the adc0 subsystem direct ly accessible from the mcu will be preferred over the adc embedded inside the ezradiopro peripheral. registers 0fh "adc configuration", 10h "sensor offset" and 4fh "amplifier offset" can be used to configure the adc o peration. details of these registers are in ?an440: ezradiopro detailed register descriptions.? every time an adc conversion is desired, bit 7 "a d c start/adcdone" in register 0fh ?adc configuration? must be set to 1. the conversion time for the adc is 350 s. after the adc conversion is done and the a d cdone signal is showing 1, then the adc value may be read out of ?register 11h: adc value." when the adc is doing its conversion, the ad cstart/adcdone bit will read 0. when the adc has finished its conver - sion, the bit will be set to 1. a new adc conversion ca n be initiated by w r iting a 1 to the adcstart/adcdone bit. the architecture of the adc is shown in figure 32.21 . the signal and reference inputs of the adc are selected by adcsel[2:0] and adcref[1:0] in register 0 fh ?adc configu ration?, respectively. the default set - ting is to read out the temperature sensor using th e ban dgap voltage (vbg) as reference. with the vbg reference the input range of the adc is from 0?1.02 v with an lsb resolution of 4 mv (1.02/255). chang - ing the adc reference will change the lsb res o lution accordingly. a differential multiplexer and amplifier are provided for inter f acing external bridge sensors. the gain of the amplifier is selectable by adcgain[1: 0] in register 0fh. the majority of sensor bridges have supply voltage (vdd) dependent gain and offset. the reference voltage of the adc can be changed to either v dd /2 or v dd /3. a programmable v dd dependent offset voltage can be added using soffs[3:0] in register 10h. clkt[1:0] modulation source 00 0 cycles 01 128 cycles 10 256 cycles 11 512 cycles
si102x/3x 476 rev. 0.3 figure 32.21. general purpose adc architecture 32.8.4. temperature sensor the ezradiopro peripheral includes an integrated on-chip analog temperature sensor independent of the temperature sensor as sociated with adc0. the temperature sensor will be automatically enabled when the temperature sensor is selected as the inpu t of the ezradiopro adc or when the analog temp voltage is selected on the analog test bus. the temperature sensor value may be digitized using the ezra - diopro general-purpose adc and read out through "r e g ister 10h. adc sensor amplifier offset." the range of the temperature sensor is configurable. ta b l e 32.7 lists the settings for the different temperature ranges and performance. to use the temp sensor: 1. set the input for adc to the temperature sensor, "r e g ister 0fh. adc configur ation"?adcsel[2:0] = 000 2. set the reference for adc, "register 0f h. adc configuration"?adcref[1:0] = 00 3. set the temperature range for adc, "register 12 h. temperature sensor calibration"?tsrange[1:0] 4. set entsoffs = 1, "register 12h. temperature sensor calibration" 5. trigger adc reading, "register 0fh. adc configuration"?adcstart = 1 6. read temperature value?read contents of "register 11h. adc value" add r/w function/ descriptio n d7 d6 d5 d4 d3 d2 d1 d0 por def. 0f r/w adc configuration adcstart/adcdone adcsel[2] adcsel[1] adcsel[0] adcref[1] adcref[0] adcgain[1] adcgain[0] 00h 10 r/w sensor offset soffs[3] soffs[2] soffs[1] soffs[0] 00h 11 r adc value adc[7] adc[6] adc[5] adc[4] adc[3] adc[2] adc[1] adc[0] ? ? ? ? ? ? ? diff. mux diff. amp. input mux ref mux v in v ref ? ? adcsel [2:0] aoffs [4:0] adcgain [1:0] adcsel [2:0] adcref [1:0] adc [7:0] v dd / 3 v dd / 2 gpio1 gpio0 gpio2 temperature sensor v bg (1.2v) 8-bit adc 0 -1020mv / 0-255 soffs [3:0]
rev. 0.3 477 si102x/3x the slope of the temperature sensor is very linear and monotonic. for absolute accuracy better than 10 c calibra tion is necessary. the temperature sensor may be calibrated by setting entsoffs = 1 in ?register 1 2h. t emperature sensor control? and setting the offset with the tvoffs[7:0] bits in ?register 13h. tempera - ture value offset.? this method adds a positive offset digit a lly to the adc value th at is read in ?register 11h. adc value.? the other method of calibration is to use the tstrim which compensates the analog cir - cuit. this is done by setting entstrim = 1 and using the t s trim[2:0] bits to offset the temperature in ?register 12h. temperature sensor control.? with this method of calibration, a negative offset may be achieved. with both methods of ca libration better than 3 c absolute accura cy ma y be achieved. the different ranges for the temperature sensor and adc8 are demonstrated in figure 32.22 . the value of the adc8 may be translated to a temperature reading by adc8value x adc8 lsb + lowest temperature in temp range. for instance for a tsrange = 00, temp = adc8value x 0.5 ? 64. add r/ w function/ description d7 d6 d5 d4 d3 d2 d1 d0 por def. 12 r/w temperature sensor cont rol tsrange[1] tsrange[0] entsoffs entstrim tstrim[3] tstrim[2] vbgtrim[1] vbgtrim[0] 20h 13 r/w temperature value off set tvoffs[7] tvoffs[6] tvoffs[5] tvoffs[4] tvoffs[3] tvoffs[2] tvoffs[1] tvoffs[0] 00h table 32.7. temperature sensor range entoff tsrange[1] tsrange[0] temp. range unit slope adc8 lsb 1 0 0 ?64 ? 64 c 8 mv/c 0.5 c 1 0 1 ?64 ? 192 c 4 mv/c 1 c 1 1 0 0 ? 128 c 8 mv/c 0.5 c 1 1 1 ?40 ? 216 f 4 mv/f 1 f 0* 1 0 0 ? 341 k 3 mv/k 1.333 k note: absolute temperature mode, no temperature shift. th is mode is only for test purposes. por value of en_toff is 1.
si102x/3x 478 rev. 0.3 figure 32.22. temperature ranges using adc8 32.8.5. low battery detector a low battery detector (lbd) with digital read-out is integrated into the chip. a digital threshold may be pro - grammed into the lbdt[4 :0] field in "re gister 1ah. low battery detector threshold". when the digitized bat - tery voltage reaches this threshold an interrupt will be generated on the nirq pi n to the microcontroller . the microcontroller can confirm source of the interrupt by reading "register 03h. interrupt/status 1" and ?register 04h. interrupt/status 2.? if the lbd is enabled while the chip is in s l eep mode, it will automatically enable the rc oscillator which will periodically turn on the lbd circuit to measure the battery voltage. the batt ery voltage may also be read out through "register 1bh. battery voltage level" at any time when the lbd is enabled. the low bat - tery detect function is enabled by setting enlbd=1 in "re giste r 07h. operating mode and function control 1". the lbd output is digitized by a 5-bit adc. when the lbd function is enabled (enlbd = 1 in "register 07h. ope rating mode and function control 1") the battery voltage may be read at anytime by reading "register 1bh. battery voltage level." a battery voltage threshold may be programmed in ?register 1ah. low bat - tery detector threshold". when the battery voltage level drops below the battery voltage threshold an interrupt w ill be ge nerated on nirq pin to the microcontroller if the lbd interrupt is enabled in ?register add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 1a r/w low battery detector thre shold lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h 1b r battery voltage level 0 0 0 vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] ? temperature measurement with adc8 0 50 100 150 200 250 300 - 40 - 20 0 20 40 60 80 100 temperature [celsius] sensor range 0 sensor range 1 sensor range 2 sensor range 3 adc v alue
rev. 0.3 479 si102x/3x 06h. interrupt enable 2.? the microc ontroller will then need to verify the interrupt by reading the interrupt status register, addresses 03 and 04h. the lsb step size for the lbd adc is 50 mv, with the adc range demonstrated in the ta ble below. if the lbd is enabled the lbd and adc will automatically be enabled every 1 s for approximately 250 s to measure the voltage which minimizes the current consumption in se nso r mode. before an interrupt is activated four consecutive readings are required. 32.8.6. wake-up timer and 32 khz clock source the ezradiopro peripheral contains an integrated wake-up timer independent of the smartclock which can be used to periodically wake the chip from sl eep mode using the interrupt pin. the wake-up timer runs from the internal 32.768 khz rc oscillator. the wake-up timer can be configured to run when in sleep mode. if enwt = 1 in "register 07h. operat ing mode and func tion control 1" when entering sleep mode, the wake-up timer will count for a time specif ied defined in registers 14?16h, "wake up timer period". at the expiration of this period an interrupt will be g enerated on the ni rq pin if this interrupt is enabled. the software will then need to verify the in terrupt by reading the regi sters 03h?04h, "interrupt status 1 & 2". the wake-up timer value may be read at any time by the wtv[15:0] read only registers 17h? 18h. the formula for calculating the wake-up period is the following: use of the d variable in the formula is only necessary i f finer resolution is required than can be achieved by using the r value. adc value vdd voltage [v] 0 < 1.7 1 1.7?1.75 2 1.75?1.8 ? ? 29 3.1?3.15 30 3.15?3.2 31 > 3.2 wut register description wtr[4:0] r value in formula wtm[15:0] m value in formula adcvalue mv tage batteryvol ? ? ? 507.1 ms m wut r 768.32 232 ?? ?
si102x/3x 480 rev. 0.3 there are two different methods for utilizing the wake-up timer (wut) dep ending on if the wut interrupt is enabled in ?register 06h. interrupt enable 2.? if the wut interrupt is enabled then nirq pin will go low when the timer expires. the chip w ill also change state so that the 30 mhz xtal is enabled so that the microcon troller clock output is available for the micr ocontroller to use to process the interrupt. the other method of use is to not enable the wut interrupt and us e the wut gpio setting. in this mode of operation the chip will not change stat e until commanded by the mi crocontroller. the differen t modes of op erating the wut and the current consumpti on impacts are demonstrated in figure 32.23 . a 32 khz xtal may also be used for better timing accuracy. by setting the x32 ksel bit in register 07h "op e rating & function control 1", gpio0 is autom atically reconfigured so that an external 32 khz xtal may be connected to t his pin. in th is mode, the gpio0 is extremely sens itive to parasitic capacitance, so only the xtal should be connected to this pin with t he xtal physically located as close to the pin as pos - sible. once the x32 ksel bit is set, all internal functions such as wut , microcontroller clock, and ldc mode will use the 32 khz xtal and not the 32 khz rc oscillator. the 32 khz xtal accuracy is comprised of both the xtal p arameters and the inte rnal circuit. the xtal accuracy can be defined as the xtal initial error + xtal aging + xtal temperature drift + detuning from the internal oscillator circuit. the error caused by the internal circuit is typically less than 10 ppm. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 14 r/w wake-up timer period 1 wtr[4] wtr[3] wtr[2] wtr[1] wtr[0] 03h 15 r/w wake-up timer period 2 wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h 16 r/w wake-up timer period 3 wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 00h 17 r wake-up timer value 1 wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8] ? 18 r wake-up timer value 2 wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] ?
rev. 0.3 481 si102x/3x figure 32.23. wut interrupt and wut operation 32.8.7. low duty cycle mode the low duty cycle mode is available to automatically wake-up the receiver to ch eck if a valid signal is available. the basic operation of the low duty cycle mode is demonstrated in the figure below. if a valid preamble or sync word is not dete cted the chip will return to sleep mode until the beginning of a new wut period. if a valid preamble and sync are detected the receiv er on period will be ex tended for the low duty cycle mode duration (tldc) to rece ive all of the packet. the wut peri od must be set in conjunction with the low duty cycle mode duration. the r value (?register 14h. wake-up timer period 1?) is shared wut period gpiox = 00001 nirq spi interrupt read chip state current consumption sleep ready sleep ready sleep ready sleep 1 ua 1.5 ma 1 ua 1.5 ma 1 ua 1.5 ma wut period gpiox = 00001 nirq spi interrupt read chip state current consumption sleep 1 ua interrupt enable enwut = 1 ( reg 06h) interrupt enable enwut = 0 ( reg 06h)
si102x/3x 482 rev. 0.3 between the wut and the tldc. the ld c[7:0] bits are located in ?regi ster 19h. low duty cycle mode duration.? the time of the tldc is determined by the formula below: figure 32.24. low duty cycle mode 32.8.8. gpio configuration three general purpose ios (gpios) are available. nume rous functions such as specific interrupts, trsw control, etc. can be routed to the gpio pins as show n in the tables below. when in shutdown mode all the gpio pads are pulled low. note: the adc should not be selected as an input to the gpio in standby or sleep modes and will cause excess cur - rent consumption. the gpio settings for gpio1 and gpio2 are the same as for gpio0 with the exception of the 00000 default setting. the default sett ings for each gpio are listed below: for a complete list of the available gpios see ?a n 4 40: ezradiopro detailed register descriptions?. the gpio drive streng th may be adjusted with the gpioxdrv[1:0] bits. settin g a higher value will increase the drive strength and current capab ility of the gpio by changing the dr iver size. special care should be add r/w function/ descr iption d7 d6 d5 d4 d3 d2 d1 d0 por def. 0b r/w gpio0 configura tion gpio0drv[1] gpio0drv[0] pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h 0c r/w gpio1 co nfigura tion gpio1drv[1] gpio1drv[0] pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h 0d r/w gpio2 configura tion gpio2drv[1] gpio2drv[0] pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h 0e r/w i/o port configura tion extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 00h gpio 00000?default setting gpio0 por gpio1 por inverted gpio2 output clock ms ldc tldc r 768.32 24 ]0:7[ ? ? ?
rev. 0.3 483 si102x/3x taken in setting the drive strength and loading on gp io2 when the microcontroller clock is used. excess loading or inadequate drive may contribu te to increased spurious emissions. pin 6, ant may be used as an altern ate to control a tr switch. pin 6 is a hardwired version of gpio set - ting 11000, antenna 2 switch used for antenna diversit y . it can be manually controlled by the antdiv[2:0] bits in register 08h if antenna diversity is not used. see an440, register 08h for more details. 32.8.9. antenna diversity to mitigate the problem of frequency-selectiv e fading due to multi-path propagation, some transceiver sys - tems use a scheme known as antenna diversity. in this scheme, two antennas are used. each time the transceiver enters rx mode the receive signal strength fr om each antenna is evaluated. this evaluation process takes place during the preamble portion of the packet. the antenna with the strongest received signal is then used for the remainde r of that rx packet. the same an tenna will also be used for the next corresponding tx packet. this chip fully supports antenna d i versity with an integrated antenna diversity control algorithm. the required signals needed to control an external spdt rf switch (such as pin diode or gaas switch) are available on the gpiox pins. the ope ration of these gpio signals is programmable to allow for different antenna diversity architectures and co nfigurations. the antdiv[2:0] bits are found in register 08h ?operating & function control 2.? the gpio pins are capable of sourcing up to 5 ma of current, so it may be used dir e ctly to forward-bias a pin diode if desired. the antenna diversity algorithm will automatically to ggle back and forth betwe en the antennas until the packet starts to arrive. the recommended preamble leng th for optimal antenna selection is 8 bytes. a spe - cial antenna diversity algorithm (antdiv[2:0] = 110 or 111) is included that allows for shorter preamble le ngths for beacon mode in tdma-like systems wher e the arrival of the packet is synchronous to the receiver enable. the recommended preamble length to obtain optimal antenna selection for synchronous mode is 4 bytes. 32.8.10. rssi and clear channel assessment received signal strength indicator (rssi) is an estimate of the signal strength in the channel to which the receiver is tuned. the rssi value can be read from an 8-bit register with 0.5 db resolution per bit. figure 32.25 demonstrates the relationship between input po wer level and rssi value. the ab solute value of the rssi will change slightly dep ending on the modem se ttings. the r ssi may be read at anytime, but add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 08 r/w operating & function control 2 ant div[2] antdiv[1] antdiv[0] rxmpk autotx enldm ffclrrx ffclrtx 00h table 32.8. antenna diversity control antdiv[2:0] rx/tx state non rx/tx state gpio ant1 gpio ant2 gpio ant1 gpio ant2 000 0 1 0 0 001 1 0 0 0 010 0 1 1 1 011 1 0 1 1 100 antenna diversity algorithm 0 0 101 antenna diversity algorithm 1 1 110 antenna diversity algo rithm in beacon mode 0 0 111 antenna diversity algo rithm in beacon mode 1 1
si102x/3x 484 rev. 0.3 an incorrect error may rarely occur. the rssi value may be incorrect if read during the update period. the update period is approximately 10 ns every 4 tb. for 10 kbps, this would result in a 1 in 40,000 probability that the rssi may be read inc orrectl y. this probability is extremely low, but to avoid this, one of the follow - ing options is recommended: majority po lling, reading the rssi value within 1 t b of the rssi interrupt, or us ing the rssi threshold described in the next paragraph for clear channel assessment (cca). for cca, threshold is programmed into rssith[7:0] in "register 27 h. rssi threshold for clear channel indicator." after the rssi is evaluated in the preamble, a decision is made if the signal strength on this channel is above or below the threshold. if the signal strength is above the programmed threshold then the rssi status bit, irssi, in "register 04h. interrupt/status 2" will be set to 1. the rssi stat us can also be routed to a gpio line by configuring the gpio configuration register to gpiox[3:0] = 1110. figure 32.25. rssi value vs. input power 32.9. reference design reference designs are available at www.silabs.com for man y common applicat ions which include recom - mended schematics, bom, and layout. tx matching co mp one nt values for the di fferent frequency bands can be found in the application notes ?an435: si4032/4432 pa matching? and ?an436: si4030/4031/4430/4431 pa matching.? rx matching component values for different frequency bands can be found in ?an427: ezradiopro si433x and si443x rx lna matching.? add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 26 r received signal strength indicator rssi[7] rssi[6] rssi[5] rssi[4] rssi[3] rssi[2] rssi[1] rssi[0] ? 27 r/w rssi threshold for clear channel indicator rssith[7] rssith[6] rssith[5] rssith[4] rssith[3] rssith[2] rssith[1] rssith[0] 00h rssi vs input power 0 50 100 150 200 250 -120 -100 -80 -60 -40 -20 0 20 in pow [dbm] rssi
rev. 0.3 485 si102x/3x l2 is an optional placement place instead of r0 if filtering is necessary matched to 50 ohm source / load. d1 p6.7/lcd31 d5 p6.7/lcd31 a1 p4.0/lcd8 a2 p3.7/lcd7 b1 p6.6/lcd30 a3 p3.6/lcd6 b2 p6.5/lcd29 a4 p3.5/lcd5 b3 p6.4/lcd28 a5 p3.4/lcd4 b4 p6.3/lcd27 a6 p3.3/lcd3 b5 p6.2/lcd26 a7 p3.2/lcd2 b6 p6.1/lcd25 a8 p3.1/lcd1 b7 p6.0/lcd24 a9 p3.0/lcd0 b8 p5.7/lcd23 a10 p2.7/com3 b9 p5.6/lcd22 a11 p2.6/com2 b10 p2.5/com1 a12 p2.4/com0 b11 nirq a13 xout a14 xin d6 gnd d2 gnd d4 p4.4/lcd12 d8 p4.4/lcd12 a38 p0.4/tx/adc4 a37 p0.5/rx/adc5 b22 p4.5/lcd13 a36 p0.6/cnvstr/adc6 b21 p4.6/lcd14 a35 p0.7/iref/adc7 b20 p4.7/lcd15 a34 p1.0/pc0 b19 p5.0/lcd16 a33 p1.1/pc1 b18 p5.1/lcd17 a32 gnd b17 gnd a31 p1.2/xtal3 b16 gnd a30 p1.3/xtal4 b15 p5.2/lcd18 a29 vlcd b14 p5.3/lcd19 a28 p1.4/adc8 b1 3 p5 .4/lcd20 a27 p1.5/int01/adc9 b12 p5.5/lcd21 a26 p1.6/int01/adc10 a25 vdd_dig d7 p1.7/adc11 d3 vr_dig a48 p7.0/c2d a47 rstb/c2ck b29 viorf a46 vdc b28 gnd a45 gnddc b27 ind a44 vbatdc b26 vio a43 vbat b25 p4.1/lcd a42 p0.0/vref/adc0 b24 p4.2/lcd10 a41 p0.1/agnd/adc1 b23 p4.3/lcd11 a40 p0.2/xtal1/adc2 a39 p0.3/xtal2/adc3 a15 sdn a16 nc a17 vdd_rf a18 tx a19 rxp a20 rxn a21 ant_a a22 gpio_0 a23 gpio_1 a24 gpio_2 e0 gnd_epad u1 si1024-a1-gm x1 32.768khz-7-t r6 no pop r5 no pop 12 l1 0.56uh 1 c 2 a z1 no-pop c6 0.01uf x7r c5 0.1uf x7r c4 2.2uf x5r c3 0.01uf x7r c2 0.1uf x7r c1 2.2uf x5r c16 0.1uf c18 33pf c17 100pf r13 0.0 12 l2 no pop 1 4 2 3 q2 30mhz tz1430a c10 100pf c11 0.1uf sj3 sj4 r1 1k c13 0.1uf x7r sj5 sj6 sj7 c0 l0 rdc lc lr lr2 cr2 cr1 cm lm cm2 lm2 cm3 cc1 c15 2.2uf trx1 sma c9 1.0uf c8 10uf x5r p1.5/cts p6.7/lcd31 p4.0/lcd8 p3.7/lcd7 p6.6/lcd30 p3.6/lcd6 p6.5/lcd29 p3.5/lcd5 p6.4/lcd28 p3.4/lcd4 p6.3/lcd27 p3.3/lcd3 p6.2/lcd26 p3.2/lcd2 p6.1/lcd25 p3.1/lcd1 p6.0/lcd24 p3.0/lcd0 p5.7/lcd23 p2.7/com3 p5.6/lcd22 p2.6/com2 p2.5/com1 p2.4/com0 p7.0/c2d rst/c2ck p4.4/lcd12 p0.4/tx p0.5/rx p4.5/lcd13 p0.6/cnvstr p4.6/lcd14 p0.7/iref0 p4.7/lcd15 p1.0/pc0 p5.0/lcd16 p1.1/pc1 p5.1/lcd17 p5.2/lcd18 p5.3/lcd19 p1.4 p5.4/lcd20 p4.1/lcd9 p0.0/vref p4.2/lcd10 p0.1/agnd p4.3/lcd11 p0.2/xtal1 p0.3/xtal2 gnd gnd gnd sdn gnd irq gnd gnd gpio_0 gpio_1 gpio_2 ant_a gnd vdc vbat vio p1.2 p1.3 gnd vdd_rf p1.7 p1.6 vbat gnd vbat vdc vdd_rf vrf vdd_rf gnd gnd gnd p1.7 p1.6 p5.5/lcd21 gnd gnd figure 32.26. si1024 split rf tx/rx direct-tie reference design?schematic
si102x/3x 486 rev. 0.3 matched to 50 ohm source / load. gpio1 / vc1 gpio2 / vc2 tx rx 0 01 1 switch controls are active low. l2 is an optional placement place instead of r0 if filtering is necessary d1 p6.7/lcd31 d5 p6.7/lcd31 a1 p4.0/lcd8 a2 p3.7/lcd7 b1 p6.6/lcd30 a3 p3.6/lcd6 b2 p6.5/lcd29 a4 p3.5/lcd5 b3 p6.4/lcd28 a5 p3.4/lcd4 b4 p6.3/lcd27 a6 p3.3/lcd3 b5 p6.2/lcd26 a7 p3.2/lcd2 b6 p6.1/lcd25 a8 p3.1/lcd1 b7 p6.0/lcd24 a9 p3.0/lcd0 b8 p5.7/lcd23 a10 p2.7/com3 b9 p5.6/lcd22 a11 p2.6/com2 b10 p2.5/com1 a12 p2.4/com0 b11 nirq a13 xout a14 xin d6 gnd d2 gnd d4 p4.4/lcd12 d8 p4.4/lcd12 a38 p0.4/tx/adc4 a37 p0.5/rx/adc5 b22 p4.5/lcd13 a36 p0.6/cnvstr/adc6 b21 p4.6/lcd14 a35 p0.7/iref/adc7 b20 p4.7/lcd15 a34 p1.0/pc0 b19 p5.0/lcd16 a33 p1.1/pc1 b18 p5.1/lcd17 a32 gnd b17 gnd a31 p1.2/xtal3 b16 gnd a30 p1.3/xtal4 b15 p5.2/lcd18 a29 vlcd b14 p5.3/lcd19 a28 p1.4/adc8 b1 3 p5 .4/lcd20 a27 p1.5/int01/adc9 b12 p5.5/lcd21 a26 p1.6/int01/adc10 a25 vdd_dig d7 p1.7/adc11 d3 vr_dig a48 p7.0/c2d a47 rstb/c2ck b29 viorf a46 vdc b28 gnd a45 gnddc b27 ind a44 vbatdc b26 vio a43 vbat b25 p4.1/lcd a42 p0.0/vref/adc0 b24 p4.2/lcd10 a41 p0.1/agnd/adc1 b23 p4.3/lcd11 a40 p0.2/xtal1/adc2 a39 p0.3/xtal2/adc3 a15 sdn a16 nc a17 vdd_rf a18 tx a19 rxp a20 rxn a21 ant_a a22 gpio_0 a23 gpio_1 a24 gpio_2 e0 gnd_epad u1 si1020-a1-gm c8 10uf x5r x1 32.768khz-7-t r6 no pop r5 no pop 12 l1 0.56uh 1 c 2 a z1 no pop c6 0.01uf x7r c5 0.1uf x7r c4 2.2uf x5r c3 0.01uf x7r c2 0.1uf x7r c1 2.2uf x5r sj2 sj1 1 out1 2 gnd 3 out2 4 vc2 5 rf_in 6 vc1 u3 upg2214tb c16 0.1uf ch cm cc1 c18 33pf c0 cc2 cr2 cm3 cm2 cr1 c19 100pf c20 100pf c17 100pf lm l0 lh lc lr rdc lm2 rh 49.9 trx sma r13 0.0 l2 no pop 1 4 2 3 q2 xtl-smt_tz1430a_30mhz c10 100pf c11 0.1uf c9 1.0uf sj3 sj4 r1 1k c13 0.1uf x7r sj5 sj6 sj7 c15 2.2uf x5r p1.5/cts p6.7/lcd31 p4.0/lcd8 p3.7/lcd7 p6.6/lcd30 p3.6/lcd6 p6.5/lcd29 p3.5/lcd5 p6.4/lcd28 p3.4/lcd4 p6.3/lcd27 p3.3/lcd3 p6.2/lcd26 p3.2/lcd2 p6.1/lcd25 p3.1/lcd1 p6.0/lcd24 p3.0/lcd0 p5.7/lcd23 p2.7/com3 p5.6/lcd22 p2.6/com2 p2.5/com1 p2.4/com0 p7.0/c2d rst/c2ck p4.4/lcd12 p0.4/tx p0.5/rx p4.5/lcd13 p0.6/cnvstr p4.6/lcd14 p0.7/iref0 p4.7/lcd15 p1.0/pc0 p5.0/lcd16 p1.1/pc1 p5.1/lcd17 p5.3/lcd19 p1.4 p5.4/lcd20 p4.1/lcd9 p0.0/vref p4.2/lcd10 p0.1/agnd p4.3/lcd11 p0.2/xtal1 p0.3/xtal2 gnd gnd gnd sdn gnd irq gnd gnd gnd gnd gnd gnd gnd gnd gpio_0 gpio_1 gpio_2 ant_a gnd vdc vbat vio p1.2 p1.3 gnd vdd_rf p1.7 p1.6 vbat gnd vbat vdc vdd_rf vrf vdd_rf gnd p1.7 p1.6 p5.5/lcd21 p5.2/lcd18 gndgnd figure 32.27. si1020 switch matching reference design?schematic
rev. 0.3 487 si102x/3x 32.10. application notes and reference designs a comprehensive set of application notes and reference designs are available to assist with the develop - ment of a radio system. a partial list of a pplications notes is given below. for the complete list of applic at ion notes, latest referenc e designs and demos visit the silicon labs website . ? an361: wireless mbus implementation using ezradiopro devices ? an379: antenna diversity with ezradiopro ? an414: ezradiopro layout design guide ? an415: ezradiopro programming guide ? an417: si4x3x family crystal oscillators ? an419: arib std-t67 narrow-band 426/429 mhz measured on the si4431-a0 ? an427: ezradiopro si433x and si443x rx lna matching ? an429: using the dc-dc converter on the f9xx seri es mcu for single batt ery operation with the ezradiopro rf devices ? an432: rx ber measurement on ezradiopro with a looped pn sequence ? an435: si4032/4432 pa matching ? an436: si4030/4031/ 4430/4431 pa matching ? an437: 915 mhz measurement results and fcc compliance ? an439: ezradiopro quick start guide ? an440: si4430/31/32 register descriptions ? an445: si4431 rf performance and etsi compliance test results ? an451: wireless m-bus software implementation ? an459: 950 mhz measurement result s and arib complianc e ? an460: 470 mhz measurement results for china ? an463: support for non-standard packet structures and raw mode ? an466: si4030/31/32 register descriptions ? an467: si4330 register descriptions ? an514: using the ezlink reference design to create a two-channel pwm motor control circuit ? an539: ezmacpro overview 32.11. customer support technical support for the complete fa mily of silicon labs wireless produc ts is available by accessing the wireless section of the s ilicon labs' website at www.silabs.com/wireless . for mcu support, please visit www.silabs.com/mcu. for answers to common questions please visit the wireless and mcu knowledge base at www.silabs.com/support/knowledgebase .
si102x/3x 488 rev. 0.3 32.12. register ta ble and descriptions table 32.9. ezradiopro internal register descriptions add r/w function/desc data por default d7 d6 d5 d4 d3 d2 d1 d0 00 r device type 0 0 0 dt[4] dt[3] dt[2] dt[1] dt[0] 00111 01 r device version 0 0 0 vc[4] vc[3] vc[2] vc[1] vc[0] 06h 02 r device status ffovfl ffunfl rxffem headerr reserved reserved cps[1] cps[0] ? 03 r interrupt status 1 ifferr itxffafull itxffaem irxffafull iext ipksent ipkvalid icrcerror ? 04 r interrupt status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor ? 05 r/w interrupt enable 1 enfferr entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror 00h 06 r/w interrupt enable 2 enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor 03h 07 r/w operating & function con - trol 1 swres enlbd enwt x32ksel txon rxon pllon xton 01h 08 r/w operating & function con - trol 2 antdiv[2] antdiv[1] antdiv[0] rxmpk autotx enldm ffclrrx ffclrtx 00h 09 r/w crystal oscillator load cap a citance xtalshft xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] 7fh 0a r/w microcontroller output clock reserved reserved clkt[1] clkt[0] enlfc mclk[2] mclk[1] mclk[0] 06h 0b r/w gpio0 configuration gpio0drv[1] gpio0drv[0] pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h 0c r/w gpio1 configuration gpio1drv[1] gpio1drv[0] pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h 0d r/w gpio2 configuration gpio2drv[1] gpio2drv[0] pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h 0e r/w i/o port configuration reserved extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 00h 0f r/w adc configuration adcstart/ adc - done adcsel[2] adcsel[1] adcsel[0] adcref[1] adcref[0] adcgain[1] adcgain[0] 00h 10 r/w adc sensor amplifier offset reserved reserved reserved reserved adcoffs[3] adcoffs[2] adcoffs[1] adcoffs[0] 00h 11 r adc value adc[7] adc[6] adc[5] adc[4] adc[3] adc[2] adc[1] adc[0] ? 12 r/w temperature sensor control tsrange[1] tsrange[0] entsoffs entstrim tstrim[3] tstrim[2] tstrim[1] tstrim[0] 20h 13 r/w temperature value offset tvoffs[7] tvoffs[6] tvoffs[5] tvoffs[4] tvoffs[3] tvoffs[2] tvoffs[1] tvoffs[0] 00h 14 r/w wake-up timer period 1 reserved reserved reserved wtr[4] wtr[3] wtr[2] wtr[1] wtr[0] 03h 15 r/w wake-up timer period 2 wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h 16 r/w wake-up timer period 3 wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 01h 17 r wake-up timer value 1 wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8] ? 18 r wake-up timer value 2 wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] ? 19 r/w low-duty cycle mode dura - tion ldc[7] ldc[6] ldc[5] ldc[4] ldc[3] ldc[2] ldc[1] ldc[0] 00h 1a r/w low battery detector thre s hold reserved reserved reserved lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h 1b r battery voltage level 0 0 0 vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] ? 1c r/w if filter bandwidth dwn3_bypass ndec[2] ndec[1] ndec[0] filset[3] filset[2] filset[1] filset[0] 01h 1d r/w afc loop gearshift over - ride afcbd enafc afcgearh[2] afcgearh[1] afcgearh[0] 1p5 bypass matap ph0size 40h 1e r/w afc timing control swait_timer[1] swait_timer[0] shwait[2] shwait[1] shwait[0] anwait[2] anwait[1] anwait[0] 0ah 1f r/w clock recovery gearshif t override reserved reserved crfast[2] crfast[1] crfast[0] crslow[2] crslow[1] crslow[0] 03h 20 r/w clock recovery o v ersampling ratio rxosr[7] rxosr[6] rxosr[5] rxosr[4] rxosr[3] rxosr[2] rxosr[1] rxosr[0] 64h 21 r/w clock recovery o f fset 2 rxosr[10] rxosr[9] rxosr[8] stallctrl ncoff[19] ncoff[18] ncoff[17] ncoff[16] 01h 22 r/w clock recovery o f fset 1 ncoff[15] ncoff[14] ncoff[13] ncoff[12] ncoff[11] ncoff[10] ncoff[9] ncoff[8] 47h 23 r/w clock recovery o f fset 0 ncoff[7] ncoff[6] ncoff[5] ncoff[4] ncoff[3] ncoff[2] ncoff[1] ncoff[0] aeh 24 r/w clock recovery t i ming loop gain 1 reserved reserved reserved rxncocomp crgain2x crgain[10] crgain[9] crgain[8] 02h 25 r/w clock recovery t i ming loop gain 0 crgain[7] crgain[6] crgain[5] crgain[4] crgain[3] crgain[2] crgain[1] crgain[0] 8fh 26 r received signal strength in dic ator rssi[7] rssi[6] rssi[5] rssi[4] rssi[3] rssi[2] rssi[1] rssi[0] ? 27 r/w rssi threshold for clear chan nel in dicator rssith[7] rssith[6] rssith[5] rssith[4] rssith[3] rssith[2] rssith[1] rssith[0] 1eh 28 r antenna diversity register 1 adrssi1[7] adrssia[6] adrssia[5] adrssia[4] adrssia[3] adrssia[2] adrssia[1] adrssia[0] ? 29 r antenna diversity register 2 adrssib[7] adrssib[6] adrssib[5] adrssib[4] adrssib[3] adrssib[2] adrssib[1] adrssib[0] ? 2a r/w afc limiter afclim[7] afclim[6] afclim[5] afclim[4] afclim[3] afclim[2] afclim[1] afclim[0] 00h 2b r afc correction read afc_corr[9] afc_corr[8] afc_corr[7] afc_corr[6] afc_corr[5] afc_corr[4] afc_corr[3] afc_corr[2] 00h 2c r/w ook counter value 1 afc_corr[9] afc_corr[9] ookfrzen peakdeten madeten ookcnt[10] ookcnt[9] ookcnt[8] 18h 2d r/w ook counter value 2 ookcnt[7] ookcnt[6] ookcnt[5] ookcnt[4] ookcnt[3] ookcnt[2] ookcnt[1] ookcnt[0] bch 2e r/w slicer peak hold reserved attack[2] attack[1] attack[0] decay[3] decay[2] decay[1] decay[0] 26h 2f reserved
rev. 0.3 489 si102x/3x note: detailed register descriptions are available in ?a n440: ezradiopro detailed register descriptions. 30 r/w data access control enpacrx lsbfrst crcdonly skip2ph enpactx encrc crc[1] crc[0] 8dh 31 r ezmac status 0 rxcrc1 pksrch pkrx pkvalid crcerror pktx pksent ? 32 r/w header control 1 bcen[3:0] hdch[3:0] 0ch 33 r/w header control 2 skipsyn hdlen[2] hdlen[1] hdlen[0] fixpklen synclen[1] synclen[0] prealen[8] 22h 34 r/w preamble length prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] prealen[0] 08h 35 r/w preamble detection control preath[4] preath[3] preath[2] preath[1] preath[0] rssi_off[2] rssi_off[1] rssi_off[0] 2ah 36 r/w sync word 3 sync[31] sync[30] sync[29] sync[28] sync[27] sync[26] sync[25] sync[24] 2dh 37 r/w sync word 2 sync[23] sync[22] sync[21] sync[20] sync[19] sync[18] sync[17] sync[16] d4h 38 r/w sync word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[10] sync[9] sync[8] 00h 39 r/w sync word 0 sync[7] sync[6] sync[5] sync[4] sync[3] sync[2] sync[1] sync[0] 00h 3a r/w transmit header 3 txhd[31] txhd[30] txhd[29] txhd[28] txhd[27] txhd[26] txhd[25] txhd[24] 00h 3b r/w transmit header 2 txhd[23] txhd[22] txhd[21] txhd[20] txhd[19] txhd[18] txhd[17] txhd[16] 00h 3c r/w transmit header 1 txhd[15] txhd[14] txhd[13] txhd[12] txhd[11] txhd[10] txhd[9] txhd[8] 00h 3d r/w transmit header 0 txhd[7] txhd[6] txhd[5] txhd[4] txhd[3] txhd[2] txhd[1] txhd[0] 00h 3e r/w transmit packet length pklen[7] pklen[6] pklen[5] pklen[4] pklen[3] pklen[2] pklen[1] pklen[0] 00h 3f r/w check header 3 chhd[31] chhd[30] chhd[29] chhd[28] chhd[27] chhd[26] chhd[25] chhd[24] 00h 40 r/w check header 2 chhd[23] chhd[22] chhd[21] chhd[20] chhd[19] chhd[18] chhd[17] chhd[16] 00h 41 r/w check header 1 chhd[15] chhd[14] chhd[13] chhd[12] chhd[11] chhd[10] chhd[9] chhd[8] 00h 42 r/w check header 0 chhd[7] chhd[6] chhd[5] chhd[4] chhd[3] chhd[2] chhd[1] chhd[0] 00h 43 r/w header enable 3 hden[31] hden[30] hden[29] hden[28] hden[27] hden[26] hden[25] hden[24] ffh 44 r/w header enable 2 hden[23] hden[22] hden[21] hden[20] hden[19] hden[18] hden[17] hden[16] ffh 45 r/w header enable 1 hden[15] hden[14] hden[13] hden[12] hden[11] hden[10] hden[9] hden[8] ffh 46 r/w header enable 0 hden[7] hden[6] hden[5] hden[4] hden[3] hden[2] hden[1] hden[0] ffh 47 r received header 3 rxhd[31] rxhd[30] rxhd[29] rxhd[28] rxhd[27] rxhd[26] rxhd[25] rxhd[24] ? 48 r received header 2 rxhd[23] rxhd[22] rxhd[21] rxhd[20] rxhd[19] rxhd[18] rxhd[17] rxhd[16] ? 49 r received header 1 rxhd[15] rxhd[14] rxhd[13] rxhd[12] rxhd[11] rxhd[10] rxhd[9] rxhd[8] ? 4a r received header 0 rxhd[7] rxhd[6] rxhd[5] rxhd[4] rxhd[3] rxhd[2] rxhd[1] rxhd[0] ? 4b r received packet length rxplen[7] rxplen[6] rxplen[5] rxplen[4] rxplen[3] rxplen[2] rxplen[1] rxplen[0] ? 4c-4e reserved 4f r/w adc8 control reserved reserved adc8[5] adc8[4] adc8[3] adc8[2] adc8[1] adc8[0] 10h 50-5f reserved 60 r/w channel filter coefficient add ress inv_p re_th[3] inv_pre_th[2] inv_pre_th[1] inv_pre_th[0] chfiladd[3] chfiladd[2] chfiladd[1] chfiladd[0] 00h 61 reserved 62 r/w crystal oscillator/ cont rol t est pwst[2] pwst[1] pwst[0] clkhyst enbias2x enamp2x bufovr enbuf 24h 63-6c reserved 6d r/w tx power reserved reserved reserved reserved ina_sw txpow[2] txpow[1] txpow[0] 18h 6e r/w tx data rate 1 txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[10] txdr[9] txdr[8] 0ah 6f r/w tx data rate 0 txdr[7] txdr[6] txdr[5] txdr[4] txdr[3] txdr[2] txdr[1] txdr[0] 3dh 70 r/w modulation mode control 1 reserved reserved txdtrtscale enphpwdn manppol enmaninv enmanch enwhite 0ch 71 r/w modulation mode control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h 72 r/w frequency deviation fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] 20h 73 r/w frequency offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h 74 r/w frequency offset 2 reserved reserved reserved reserved reserved reserved fo[9] fo[8] 00h 75 r/w frequency band select reserved sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 75h 76 r/w nominal carrier frequency 1 fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] bbh 77 r/w nominal carrier frequency 0 fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h 78 reserved 79 r/w frequency hopping chan - nel select fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0] 00h 7a r/w frequency hopping step si ze fh s[7] fhs[6] fhs[5] fhs[4] fhs[3] fhs[2] fhs[1] fhs[0] 00h 7b reserved 7c r/w tx fifo control 1 reserved reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0] 37h 7d r/w tx fifo control 2 reserved reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0] 04h 7e r/w rx fifo control reserved reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0] 37h 7f r/w fifo access fifod[7] fifod[6] fifod[5] fifod[4] fifod[3] fifod[2] fifod[1] fifod[0] ? table 32.9. ezradiopro internal register descriptions (continued) add r/w function/desc data por default d7 d6 d5 d4 d3 d2 d1 d0
si102x/3x 490 rev. 0.3 32.13. required changes to default register values the following register writes should be performed during device initialization. 1. the value 0x40 should be written to register 59h. 2. if the device will be operated in the 240?320 mhz or 480?640 mhz ba nds at a temperature above 60 c, then register 59h should be written to 0x43 and register 5ah should be written to 0x02.
rev. 0.3 491 si102x/3x 33. timers each mcu includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer fo r use with the adc, smbus, or for general purpose use. these timers can be used to measure time inte rvals, count external even ts and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. ti m er 2 and timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. additionally, timer 2 and ti m er 3 have a capture mode that can be used to measure the smartclock, comparator, or external clock period w ith respect to anoth er oscillator. the ability to measur e the comparator period with respect to another oscillator is particularly useful when interfacing to capacitive sensors. timers 0 and 1 may be clocked by one of five sources, dete rmined by the timer mode select bits (t1m ? t0m) and the clock scale bits (sca1?sca0). the clock scale bits define a pre- scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 33.1 for pre-scaled cl ock s e lection). timer 0/1 may then be configured to use this pre-sc ale d clock signal or th e system clock. timer 2 and ti mer 3 may be clocked by the system clock, the system clock divided by 12. timer 2 may additionally be clocked b y the smartclock divided by 8 or the comparator0 output. timer 3 may additionally be clocked by the ex ternal oscillator clock source divided by 8 or the comparator 1 output. timer 0 and timer 1 may also be operated as counters. when func tioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre - quency of up to one-fourth the system clock frequen cy ca n be counted. the input signal need not be peri - odic, but it should be held at a gi ve n level for at least two full system cl ock cycles to ensure the level is properly sampled. timer 0 and timer 1 modes: timer 2 modes: timer 3 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto- reload two 8-bit timers with auto-reload t wo 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only)
si102x/3x 492 rev. 0.3 sfr page = 0x0; sfr address = 0x8e sfr definition 33.1. ckcon: clock control bit 7 6 5 4 3 2 1 0 name t3mh t3ml t2mh t2ml t1m t0m sca[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 t3mh timer 3 high byte clock select. selects the clock supplied to the timer 3 high byte (split 8-bit timer mode only). 0: timer 3 high byte uses the clock defin ed by th e t3 xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. 6 t3ml timer 3 low byte clock select. selects the clock supplied to timer 3. selects the clock supplie d to the lower 8-bit timer in split 8-bit timer mode. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. 5 t2mh timer 2 high byte clock select. selects the clock supplied to the timer 2 high byte (split 8-bit timer mode only). 0: timer 2 high byte uses the clock defin ed by th e t2 xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. 4 t2ml timer 2 low byte clock select. selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supp lied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. 3 t1m timer 1 clock select. selects the clock source supplied to timer 1. ignored when c/t1 is set to 1. 0: timer 1 uses the clock defined by the prescale bits sca[1:0]. 1: timer 1 uses the system clock. 2 t0m timer 0 clock select. selects the clock source supplied to timer 0. ignored when c/t0 is set to 1. 0: counter/timer 0 uses the clock defined by th e pr escale bits sca[1:0]. 1: counter/timer 0 uses the system clock. 1:0 sca[1:0] timer 0/1 prescale bits. these bits control the timer 0/1 clock prescaler: 00: system clock divided by 12 01: system clock divided by 4 10: system clock divided by 48 11: external clock divided by 8 (synchronized with the system clock)
rev. 0.3 493 si102x/3x 33.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer co ntrol register (tcon) is used to enable timer 0 and ti m er 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie regis - ter ( section ?17.5. interrupt register descriptions? on page 241 ); timer 1 interrupts can be enabled by set - ting the et1 bit in the ie register ( section ?17.5. interrupt register descriptions? on page 241 ). both counter/timers operate in one of four primary m ode s sele cted by setting the mode select bits t1m1 ? t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 33.1.1. mode 0: 13 -bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and o peration of timer 0. however, both timers operate identically, and timer 1 is configured in the same ma nn er as described for timer 0. the th0 register holds the eight msbs of the 13-bit c ounte r/timer. tl0 holds the five lsbs in bit positions tl0.4 ? tl0.0. the three upper bits of tl0 (tl0.7 ? tl0.5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 (tcon.5) is set and an interr upt will occur if timer 0 interrupts are e nab led. the c/t0 bit (tmod.2) selects the counter/time r's clock source. when c/t0 is s et to logic 1, high-to-low tran sitions at the selected timer 0 input pin (t0) increment the timer register (refer to section ?27.3. priority crossbar decoder? on page 362 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system clock. when t 0m is cleared, timer 0 is clocked by the source selected by the clock scale bit s in ckcon (see sfr definition 33.1 ). setting the tr0 bit (tcon.4) enables the ti mer when either gate0 (tmod.3) is logic 0 or the input signal int0 is active as defined by bit in 0pl in register it01cf (see sfr definition 17.7 ). setting gate0 to 1 allows the timer to be controlled by the external input signal int0 (see section ?17.5. interrupt register descriptions? on page 241 ), facilitating pulse width measurements setting tr0 does not force the timer to re se t. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. tim er 1 is configured and controlled using the releva nt tcon and tmod bits just as with timer 0. the inpu t signal int1 is used with timer 1; the int1 polarity is defined by bit in1pl in register it01cf (see sfr definition 17.7 ). table 33.1. timer 0 running modes tr0 gate0 int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled note: x = don't care
si102x/3x 494 rev. 0.3 figure 33.1. t0 mode 0 block diagram 33.1.2. mode 1: 16 -bit counter/timer mode 1 operation is the same as mode 0, except that the counter /timer re gisters use all 16 bits. the coun - ter/timers are enabled and configured in mode 1 in the same manner as for mode 0. 33.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer over flow flag tf0 (tcon.5) is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enabled, an interr upt will occ u r when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired va lue before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit ( tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or when the input signal int0 is active as defined by bit in 0pl in register it01cf (see section ?17.6. external interrupts int0 and int1? on page 248 for details on the external input signals int0 and int1 ). tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 int0 t0 crossbar it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor
rev. 0.3 495 si102x/3x figure 33.2. t0 mode 2 block diagram 33.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit co unte r/timers held in tl0 and th0. the coun - ter/timer in tl0 is co n tr olled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf 0. tl0 can use either the system clock or an ex ternal input signal as its timebase. the th0 register is restricted to a timer function so urced by the system clock or presca led clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 overflow flag tf1 on overfl ow an d thus contr ols the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operating in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the smbus and/or uart, and/or initiate adc conv ersions . while timer 0 is operating in mode 3, timer 1 run control is handled through its mode set - tings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, con f igure it for mode 3. tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
si102x/3x 496 rev. 0.3 figure 33.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 0.3 497 si102x/3x sfr page = all pages; sfr address = 0x88; bit-addressable sfr definition 33.2. tcon: timer control bit 7 6 5 4 3 2 1 0 name tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf1 timer 1 overflow flag. set to 1 by hardware when timer 1 overflows. this flag can be cleared by software but is autom atically cleared when the cpu vectors to the timer 1 interrupt service ro utine . 6 tr1 timer 1 run control. timer 1 is enabled by setting this bit to 1. 5 tf0 timer 0 overflow flag. set to 1 by hardware when timer 0 overflows. this flag can be cleared by software but is autom atically cleared when the cpu vectors to the timer 0 interrupt service ro utine . 4 tr0 timer 0 run control. timer 0 is enabled by setting this bit to 1. 3 ie1 external interrupt 1. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 1 service routine in edge-triggered mode. 2 it1 interrupt 1 type select. this bit selects whether the configured int1 interrupt will be edge or level sensitive. int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 17.7 ). 0: int1 is level triggered. 1: int1 is edge triggered. 1 ie0 external interrupt 0. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 0 service routine in edge-triggered mode. 0 it0 interrupt 0 type select. this bit selects whether the configured int0 interrupt will be edge or level sensitive. int0 is configured active low or high by the in0pl bit in register it01cf (see sfr definition 17.7 ). 0: int0 is level triggered. 1: int0 is edge triggered.
si102x/3x 498 rev. 0.3 sfr page = 0x0; sfr address = 0x89 sfr definition 33.3. tmod: timer mode bit 7 6 5 4 3 2 1 0 name gate1 c/t1 t1m[1:0] gate0 c/t0 t0m[1:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 gate1 timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of int1 logic level. 1: timer 1 enabled only when tr1 = 1 and int1 is active as defined by bit in1pl in register it01cf (see sfr definition 17.7 ). 6 c/t1 counter/timer 1 select. 0: timer: timer 1 incremented by clock defined by t1m bit in register ckcon. 1: counter: timer 1 incremented by high-to-low transitions on external pin (t1). 5:4 t1m[1:0] timer 1 mode select. these bits select the timer 1 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, timer 1 inactive 3 gate0 timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of int0 logic level. 1: timer 0 enabled only when tr0 = 1 and int0 is active as defined by bit in0pl in register it01cf (see sfr definition 17.7 ). 2 c/t0 counter/timer 0 select. 0: timer: timer 0 incremented by clock defined by t0m bit in register ckcon. 1: counter: timer 0 incremented by high-to-low transitions on external pin (t0). 1:0 t0m[1:0] timer 0 mode select. these bits select the timer 0 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, two 8-bit counter/timers
rev. 0.3 499 si102x/3x sfr page = 0x0; sfr address = 0x8a sfr page = 0x0; sfr address = 0x8b sfr definition 33.4. tl0: timer 0 low byte bit 7 6 5 4 3 2 1 0 name tl0[7:0] type r/w reset 00000000 bit name function 7:0 tl0[7:0] timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. sfr definition 33.5. tl1: timer 1 low byte bit 7 6 5 4 3 2 1 0 name tl1[7:0] type r/w reset 00000000 bit name function 7:0 tl1[7:0] timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1.
si102x/3x 500 rev. 0.3 sfr page = 0x0; sfr address = 0x8c sfr page = 0x0; sfr address = 0x8d sfr definition 33.6. th0: timer 0 high byte bit 7 6 5 4 3 2 1 0 name th0[7:0] type r/w reset 00000000 bit name function 7:0 th0[7:0] timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. sfr definition 33.7. th1: timer 1 high byte bit 7 6 5 4 3 2 1 0 name th1[7:0] type r/w reset 00000000 bit name function 7:0 th1[7:0] timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1.
rev. 0.3 501 si102x/3x 33.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l ( low byte) and tmr2h (high byte). timer 2 may oper ate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 can also be used in capture mode to measure the smartclock or the comp arator 0 period with respect to anot her oscillator . the ability to measure the comparator 0 period with resp ect to the system clock is make s using touch sense switches very easy. timer 2 may be clocked by the system cl ock, the system clock divide d by 12, smartclock divided by 8, or comparator 0 output. note that the smartclock divided by 8 and comparator 0 output is synchronized with t h e system clock. 33.2.1. 16-bit time r with auto-reload when t2split (tmr2cn. 3) is zero, timer 2 operates as a 16-bit time r with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, smartclock divided by 8, or comparator 0 output. as the 1 6 -bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded into the timer 2 register as shown in figure 33.4 , and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be gen erated on each timer 2 overflow. additionally, if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn. 5), an interr upt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. figure 33.4. timer 2 16-bit mode block diagram sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m smartclock / 8 sysclk / 12 00 t2xclk[1:0] 01 11 comparator 0
si102x/3x 502 rev. 0.3 33.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bit timers (tmr2h and tmr2l ). both 8-bit timers oper - ate in auto-reload mode as shown in figure 33.5 . tmr2rll holds the reload va lue for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr 2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be configur ed to use sysc lk, sysclk divided by 12, smartclock divided by 8 or comparator 0 output. the timer 2 clock select bits (t2mh and t2ml in ckc o n) select either sysclk or the clock defined by the timer 2 external clock select bits (t2x c l k[1:0] in tmr2 cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00 ; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tm r2 h overflows. if timer 2 interrupts are enabled and tf2len (tmr2cn.5) is set, an interrupt is gener - ated each time either tmr2l or tmr2h overflows. wh en tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags a r e not cleared by hardware and must be manually cleared by software. figure 33.5. timer 2 8-bit mode block diagram 33.2.3. comparator 0/smartclock capture mode the capture mode in timer 2 allows either comparator 0 or the smartclock period to be measured against the sys tem clock or the system clock divided by 12. comparator 0 and the smartclock period can a l so be compared against each other. timer 2 capture mode is enabled by setting tf2cen to 1. timer 2 sho u ld be in 16-bit auto-reload mode when using capture mode. t2mh t2xclk[1:0] tmr2h clock source t2ml t2xclk[1:0] tmr2l clock source 0 00 sysclk / 12 0 00 sysclk / 12 0 01 smartclock / 8 0 01 smartclock / 8 0 10 reserved 0 10 reserved 0 11 comparator 0 0 11 comparator 0 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr2 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2cen tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m smartclock / 8 sysclk / 12 00 t2xclk[1:0] 01 11 comparator 0
rev. 0.3 503 si102x/3x when capture mode is enable d, a capture event will be gener ated either ev ery comparator 0 rising edge or every 8 smartclock clock cycles, depending on th e t2xclk1 setting. when the capture event occurs, the contents of timer 2 (tmr2h:tmr2l) are loaded into the timer 2 reload registers ( t mr2rlh:tmr2rll) and the tf2h flag is set (triggering an interrupt if timer 2 interrupts are enabled). by re cord ing the difference between two succ essive timer capture values, the comparator 0 or smart - clock period can be determined with respect to the timer 2 clock. the timer 2 clock should be much faster than the capture clock to achieve an accurate reading. for example, if t2ml = 1b, t2xclk1 = 0b, and tf2cen = 1b, timer 2 will clock every sysclk and cap - ture every smartclock clock divided by 8. if the sysclk is 24.5 mh z and the difference between two successive captures is 5984, then t he smartclock clock is as follows: 24.5 mhz/(5984/8) = 0.032754 mhz or 32.754 khz. this mode allows software to de termine the exact smar tclock freque ncy in self-oscillate mode and the time between consecutive comparator 0 rising edges, which is useful fo r d etecting changes in the capaci - tance of a touch sense switch. figure 33.6. timer 2 capture mode block diagram smartclock / 8 sysclk 0 1 t2xclk1 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr2l tmr2h tclk tr2 tmr2rll tmr2rlh capture tmr2cn t2split t2xclk1 tf2cen tf2l tf2h t2xclk0 tr2 tf2len tf2cen interrupt sysclk / 12 x0 t2xclk[1:0] 01 11 comparator 0 0 1 smartclock / 8 comparator 0
si102x/3x 504 rev. 0.3 sfr page = all pages; sfr ad dress = 0xc8; bit-addressable sfr definition 33.8. tmr2cn: timer 2 control bit 7 6 5 4 3 2 1 0 name tf2h tf2l tf2len tf2cen t2split tr2 t2xclk[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf2h timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0xffff to 0x0000. when the ti m er 2 interrupt is enabled, setting this bit causes the cpu to vector to the ti m er 2 interrupt service routine. this bit is not auto m atically cleared by hardware. 6 tf2l timer 2 low byte overflow flag. set by hardware when the timer 2 low byte overflows from 0xff to 0x00. tf2l will be se t when the low byte over flows regardless of the timer 2 mode. this bit is not a u tomatically cleared by hardware. 5 tf2len timer 2 low byte interrupt enable. when set to 1, this bit enables timer 2 low byte interrupts. if timer 2 interrupts are also enabled, an interr upt will be generat ed when the low byte of timer 2 over - flows. 4 tf2cen timer 2 capture enable. when set to 1, this bit enables timer 2 capture mode. 3 t2split timer 2 split mode enable. when set to 1, timer 2 operates as two 8-bit timers wi th auto-reload. otherwise, timer 2 operates in 16-bit auto-reload mode. 2 tr2 timer 2 run control. timer 2 is enabled by setting this bit to 1. in 8-bit mode, th is bit enables/disables tmr2h only; tmr2l is always enabled in split mode. 1:0 t2xclk[1:0] timer 2 external clock select. this bit selects the ?external? and ?capture trigger? clock sources for timer 2. if tim er 2 is in 8-bit mode, this bit selects the ?external? clock source for both timer by tes. t imer 2 clock select bits (t2mh and t2ml in register ckcon) may s t ill be used to select between the ?external? clock and the system clock for either timer. note: external clock sources are sy nc hronized with the system clock. 00: external clock is sysclk/12. ca pt ure trigger is smartclock/8. 01: external clock is comparator 0. capture trigger is smartclock/8. 10: external clock is sysclk/12. capture trigger is comparator 0. 11: external clock is smartclock/8 . cap ture trigger is comparator 0.
rev. 0.3 505 si102x/3x sfr page = 0x0; sfr address = 0xca sfr page = 0x0; sfr address = 0xcb sfr definition 33.9. tmr2rll: timer 2 relo ad register low byte bit 7 6 5 4 3 2 1 0 name tmr2rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rll[7:0] timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. sfr definition 33.10. tmr2rlh: timer 2 relo ad register high byte bit 7 6 5 4 3 2 1 0 name tmr2rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rlh[7:0] timer 2 reload register high byte. tmr2rlh holds the high byte of the reload value for timer 2.
si102x/3x 506 rev. 0.3 sfr page = 0x0; sfr address = 0xcc sfr page = 0x0; sfr address = 0xcd sfr definition 33.11. tmr2l: timer 2 low byte bit 7 6 5 4 3 2 1 0 name tmr2l[7:0] type r/w reset 00000000 bit name function 7:0 tmr2l[7:0] timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8- bit mode, tmr2l contains the 8-bit low byte timer value. sfr definition 33.12. tmr2h timer 2 high byte bit 7 6 5 4 3 2 1 0 name tmr2h[7:0] type r/w reset 00000000 bit name function 7:0 tmr2h[7:0] timer 2 low byte. in 16-bit mode, the tmr2h register contains the high byte of the 16-bit timer 2. in 8- bit mode, tmr2h contains the 8-bit high byte timer value.
rev. 0.3 507 si102x/3x 33.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l ( low byte) and tmr3h (high byte). timer 3 may oper ate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t3split bit (tmr2cn.3) defines the timer 3 operation mode. timer 3 can also be used in c apture mode to measure the exte rnal oscillator source or the smar tclock oscillator period with respect to another oscillator. timer 3 may be clocked by the system clock, the system cloc k divided by 12, external oscillator source divided by 8, or the smartclock oscillator. the external oscillator source di vided by 8 and smartclock oscillator is synchronize d with the system clock. 33.3.1. 16-bit time r with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, external oscillator clock sour ce divided by 8, or smartclock oscillator. as the 16-bit ti mer register increments and overflows from 0xffff to 0x 0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tmr3rll) is loaded into the timer 3 register as shown in figure 33.7 , and the timer 3 high byte overflow flag (tmr3cn. 7 ) is set. if timer 3 interrupts are enabled (if eie1.7 is set), an interrupt will be generated on each t i mer 3 overflow. additionally, if timer 3 interrupts are enabled and the tf3len bit is set (tmr3cn.5), an interrupt will be generated each ti me the lower 8 bits (tmr3l) overflow from 0xff to 0x00. figure 33.7. timer 3 16-bit mode block diagram sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split t3xclk1 tf3cen tf3l tf3h t3xclk0 tr3 interrupt tf3len to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m external clock / 8 sysclk / 12 00 t3xclk[1:0] 01 11 smartclock
si102x/3x 508 rev. 0.3 33.3.2. 8-bit timers with auto-reload when t3split is set, timer 3 operates as two 8-bi t timers (tmr3h and tmr3l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 33.8 . tmr3rll holds the reload va lue for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr 3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be configured to use sysclk, sysc lk divided by 12, the external oscillator clock source divided by 8, or the smartclock. the timer 3 clock select bits (t3mh and t3ml in ckcon) select either sysclk or t he clock defined by the timer 3 external clock select bits (t3xclk[1:0] in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00 ; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over - flows. if timer 3 interrupts are enabled and tf3len (tm r 3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3le n is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 33.8. timer 3 8-bit mode block diagram 33.3.3. smartclock/external oscillator capture mode the capture mode in timer 3 allows either smartclock or the external oscillator period to be measured against the system clock or the system clock divided by 12. smartclock and the ex ternal oscillator period can also be compared against each other. t3mh t3xclk[1:0] tmr3h clock source t3ml t3xclk[1:0] tmr3l clock source 0 00 sysclk / 12 0 00 sysclk / 12 0 01 smartclock 0 01 smartclock 0 10 reserved 0 10 reserved 0 11 external clock / 8 0 11 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr3 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split t3xclk1 tf3cen tf3len tf3l tf3h t3xclk0 tr3 to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m external clock / 8 sysclk / 12 00 t3xclk[1:0] 01 11 smartclock
rev. 0.3 509 si102x/3x setting tf3cen to 1 enables the smartclock/external oscillator capture mode for timer 3. in this mode, t3split sh ould be set to 0, as the full 16-bit timer is used. when capture mode is e nabled, a capture ev ent will be generated either ever y smartclock rising edge or every 8 external clock cycles, depending on the t3xclk1 setting. when the capture event occurs, the contents of timer 3 (tmr3h:tmr3l) are loaded into the timer 3 reload registers (tmr3rlh:tmr3rll) a nd the tf3h flag is set (triggering an interrupt if timer 3 interrupts are enabled). by recording the differ - ence between two successive timer capture values, the smar tclock or external clock period can be determined with re spect to the timer 3 clock. the timer 3 clock should be much faste r than the capture clock to achieve an accurate reading. for example, if t3ml = 1b, t3xclk1 = 0b, and tf3cen = 1b, timer 3 will clock every sysclk and cap - ture every smartclock rising edge. if sysclk is 24 .5 mhz and the difference between two successive captures is 350 counts, then the smartclock period is as follows: 350 x (1 / 24.5 mhz) = 14.2 s. this mode allows software to determine the exact frequency of th e external oscillator in c and rc mode or the time between consecutive smartclock rising edges , which is useful for determining the smartclock frequency. figure 33.9. timer 3 capture mode block diagram external clock/8 sysclk 0 1 t3xclk1 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr3l tmr3h tclk tr3 tmr3rll tmr3rlh capture tmr3cn t3split t3xclk1 tf3cen tf3l tf3h t3xclk0 tr3 tf3len tf3cen interrupt sysclk/12 x0 t3xclk[1:0] 01 11 smartclock 0 1 smartclock external clock/8
si102x/3x 510 rev. 0.3 sfr page = 0x0; sfr address = 0x91 sfr definition 33.13. tmr3cn: timer 3 control bit 7 6 5 4 3 2 1 0 name tf3h tf3l tf3len tf3cen t3split tr3 t3xclk[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf3h timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occ ur when timer 3 overflows from 0xffff to 0x0000. when the ti m er 3 interrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt s e rvice routine. this bit is not automatically cleared by hardware. 6 tf3l timer 3 low byte overflow flag. set by hardware when the timer 3 low byte overflows from 0xff to 0x00. tf3l will be se t when the low byte overflows regardless of the timer 3 mode. this bit is not au to matically cleared by hardware. 5 tf3len timer 3 low byte interrupt enable. when set to 1, this bit enables timer 3 low byte inte rrupts . if timer 3 interrupts are also enabled, an interrupt will be ge nerated when the lo w byte of timer 3 overflows. 4 tf3cen timer 3 smartclock/external osci llator capture enable. when set to 1, this bit enables timer 3 capture mode. 3 t3split timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bi t auto- re load timers. 2 tr3 timer 3 run control. timer 3 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr3h only ; tmr3l is alwa ys enabled in split mode. 1:0 t3xclk[1:0] timer 3 external clock select. this bit selects the ?external? and ?capture trigger? clock sources for timer 3. if tim er 3 is in 8-bit mode, this bit selects the ?external? cloc k source for both timer bytes. timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the ?external? cl ock and the system cloc k for either timer. note: external clock sources are sy nc hronized with the system clock. 00: external clock is sysclk /12. capture trigger is smartclock. 01: external clock is external oscilla tor/8. capture trigger is s martclock. 10: external clock is sysclk/12. capt ure trigger is exte rnal oscillator/8. 11: external clock is smar tclock. capture trigger is external oscillator/8.
rev. 0.3 511 si102x/3x sfr page = 0x0; sfr address = 0x92 sfr page = 0x0; sfr address = 0x93 sfr definition 33.14. tmr3rll: timer 3 relo ad register low byte bit 7 6 5 4 3 2 1 0 name tmr3rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rll[7:0] timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3. sfr definition 33.15. tmr3rlh: timer 3 relo ad register high byte bit 7 6 5 4 3 2 1 0 name tmr3rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rlh[7:0] timer 3 reload register high byte. tmr3rlh holds the high byte of the reload value for timer 3.
si102x/3x 512 rev. 0.3 sfr page = 0x0; sfr address = 0x94 sfr page = 0x0; sfr address = 0x95 sfr definition 33.16. tmr3l: timer 3 low byte bit 7 6 5 4 3 2 1 0 name tmr3l[7:0] type r/w reset 00000000 bit name function 7:0 tmr3l[7:0] timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit mode, tmr3l contains the 8-bit low byte timer value. sfr definition 33.17. tmr3h timer 3 high byte bit 7 6 5 4 3 2 1 0 name tmr3h[7:0] type r/w reset 00000000 bit name function 7:0 tmr3h[7:0] timer 3 high byte. in 16-bit mode, the tmr3h register contains the high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value.
rev. 0.3 513 si102x/3x 34. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. each capt ure/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled. the counter/timer is driven by a programmable timebase that can select between seve n sources: system clock, system clock divided by four, system clock divided by twelve, the external osc illator clock source divided by 8, smartclock divided by 8, timer 0 overflows, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, frequency output, 8 to 11-bit pwm, or 16-bit pwm (each mode is described in sec - tion ?34.3. capture/compare modules? on page 516 ). the external oscillator cloc k option is ideal for real- time clock (rtc) functionality, allowing the pca to be clocked by a precision ex ternal oscillator while the internal oscillator drives the syst em clock. the pca is configured and controlled through the system con - troller's special function registers. the pca block diagram is shown in figure 34.1 important note: the pca module 5 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled . see section 34.4 for details. figure 34.1. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 cex1 eci crossbar cex2 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 capture/compare module 4 capture/compare module 3 capture/compare module 5 / wdt cex4 cex5 cex3 smartclock/8
si102x/3x 514 rev. 0.3 34.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the lo w byte (lsb). reading pc a0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accurate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2 ? cps0 bits in the pca0md register select the timebase for the counter/timer as shown in ta b l e 34.1 . when the counter/timer overflows from 0xffff to 0x0 000, the coun ter overflow fl ag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically clea re d by hardware when the cpu vectors to the in terrupt service routine, and must be cleared by soft - ware. clearing the cidl bit in the pca0md register a llows the pca to continue normal operation while the cpu is in idle mode. table 34.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 0 1 1 high-to-low transitions on eci (max rate = system clock divided by 4) 100system clock 101 external oscillator source divided by 8 1 110 smartclock oscillator source divided by 8 2 111reserved notes: 1. external oscillator source divided by 8 is synchronized with the system clock. 2. smartclock oscillator source divided by 8 is synchronized with the system clock.
rev. 0.3 515 si102x/3x figure 34.2. pca counter/timer block diagram 34.2. pca0 interrupt sources figure 34.3 shows a diagram of the pca interrupt tree. th ere a re eight independent event flags that can be used to generate a pca0 interrupt. they are: the mai n pca counter overflow flag (cf), which is set upon a 16-bit overflow of the pca0 counter, an inte rmediate overflow flag (covf), which can be set on an overflow from the 8th, 9th, 10th, or 11th bit of t he pca0 counter, and the individual flags for each pca channel (ccf0, ccf1, ccf2, ccf3, ccf4, and ccf5), which are set according to the operation mode of that module. these event flags are always set when the trigger condition occurs. each of these flags can be individually selected to genera te a pca0 interrupt, using the corr esponding interrupt enable flag (ecf for cf, ecov for covf, and eccfn for each ccfn). pc a0 interrupts must be globally enabled before any individual interrupt sources are recognized by the pr ocessor. pca0 interrupts are globally enabled by set - ting the ea bit and the epca0 bit to logic 1. pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 smartclock/8 110
si102x/3x 516 rev. 0.3 figure 34.3. pca interrupt block diagram 34.3. capture/compare modules each module can be configured to operate independent ly in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit pulse width modulator. each module has special functi on registers (sfrs) associ ated with it in the cip- 51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. ta b l e 34.2 summarizes the bit settings in the pca0cpmn and pca0pwm registers used to select the pca capture/compare module?s oper a t ing mode. note that all modules set to use 8, 9, 10, or 11-bit pwm mode must use the same cycle length (8-11 bits). setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. table 34.2. pca0cpm and pca0pwm bit settings for pca capture/compare modules operational mode pca0cpmn pca0pwm bit number76543210765 4?2 1?0 capture triggered by positive edge on cexn xx10000a0xbxxx xx capture triggered by negative edge on cexn xx01000a0xbxxx xx capture triggered by any transition on cexn xx11000a0xbxxx xx pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 pca counter/timer 16- bit overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 5) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0pwm a r s e l c o v f c l s e l 0 c l s e l 1 e c o v pca counter/timer 8, 9, 10 or 11-bit overflow 0 1 set 8, 9, 10, or 11 bit operation 0 1 pca module 3 (ccf3) pca module 4 (ccf4) eccf4 0 1 pca module 5 (ccf5) eccf5 eccf3 0 1
rev. 0.3 517 si102x/3x 34.3.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin ca uses the pca to capture the value of the pca coun - ter/timer and load it into the corresponding module 's 16 -bi t capture/compar e register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi - tion that triggers the capture: low-to-high transition (p o s itive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is e nab led. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser - vice routine, and must be clea red by sof tware. if bo th cappn and capnn bi ts are set to logic 1, then the state of the port pin associated wit h cexn can be read directly to de termine whether a rising-edge or fall - ing-edge caused the capture. software timer xc00100a0xbxxx xx high speed output xc00110a0xbxxx xx frequency output xc00011a0xbxxx xx 8-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a 0 x b xxx 00 9-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 01 10-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 10 11-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 11 16-bit pulse width modulator 1 c 0 0 e 0 1 a 0 x b xxx xx notes: 1. x = don?t care (no functional difference for individual module if 1 or 0). 2. a = enable interrupts for this module (pca interrupt triggered on ccfn set to 1). 3. b = enable 8th, 9th, 10th or 11th bit overfl ow interrupt (depends on setting of clsel[1:0]). 4. c = when set to 0, the digital comparator is off. for high speed and frequency output modes, the associated pin will not toggle. in any of the pwm modes, this generates a 0% duty cycle (output = 0). 5. d = selects whether the capture/compare register (0) or the auto-reload register (1) for the associated channel is accessed via addresses pca0cphn and pca0cpln. 6. e = when set, a match event will cause the ccfn flag for the associated channel to be set. 7. all modules set to 8, 9, 10 or 11-bit pw m mode use the same cycle length setting. table 34.2. pca0cpm and pca0pwm bit settings for pca capture/compare modules operational mode pca0cpmn pca0pwm
si102x/3x 518 rev. 0.3 figure 34.4. pca capture mode diagram note: the cexn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware. 34.3.2. software timer (compare) mode in software timer mode, the pca c ounter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if th e ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser - vice routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn regis - ter enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt x000x x
rev. 0.3 519 si102x/3x figure 34.5. pca software timer mode diagram 34.3.3. high-speed output mode in high-speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/comp are flag (ccfn) in pca0cn is set to logic 1. an in te rrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not auto - matically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared b y software. setting the togn, matn, and ecomn bi ts in the pca0cpmn register enables the high- speed output mode. if ecomn is cleare d, the associated pin will retain it s state, and not toggle on the next match event. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt
si102x/3x 520 rev. 0.3 figure 34.6. pca high-speed output mode diagram 34.3.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out - put is toggled. the frequency of the square wave is then defined by equation 34.1 . equation 34.1. square wave frequency output where f pca is the frequency of the clock selected by the cps2 ? 0 bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn reg - ister. the matn bit should normally be set t o 0 in this mode. if the matn bit is set to 1, the ccfn flag for the channel will be set when t he 16-bit pca0 counter an d the 16-bit capt ure/compare register for the chan - nel are equal. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt f cexn f pca 2 pca0 cphn ? ------------------- --------------------- - = note: a value of 0x00 in the pca0cphn register is equal to 256 for this equation.
rev. 0.3 521 si102x/3x figure 34.7. pca frequency output mode 34.3.5. 8-bit, 9-bit, 10-bit and 11- bit pulse wi dth modulator modes each module can be used independently to generate a pulse width modulated (pwm) output on its associ - ated cexn pin. the frequency of the output is depe nde nt on the timebase for the pca counter/timer, and the setting of the pwm cycle length (8, 9, 10 or 11 -bits). for backwards-compa tibility with the 8-bit pwm mode available on other devices, the 8-bit pwm mode operates slightly differen t than 9, 10 and 11-bit pwm modes. it is important to note that all channels co nfigured for 8/9/10/11-bit pwm mode will use the same cycle length. it is not possible to configure one channel for 8-bit pwm mode and another for 11- bit mode (for example). however, other pca channels can be configured to pin capture, high-speed out - put, software timer, frequency output, or 16-bit pwm mode independently. 34.3.5.1. 8-bit pulse width modulator mode the duty cycle of the pwm output signal in 8-bit pwm mode is varied using the module's pca0cpln cap - ture/compare register. when the value in the low byte of the pca counter/timer (pca0l) is equal to the value in pca0cpln, the output on th e cexn pin will be set. when the coun t value in pca0l overflows, the cexn output will be reset (see figure 34.8 ). also, when the counter/timer lo w byte (pca0l ) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the valu e stor ed in the module?s capture/compare high byte (pca0cphn) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to 00b enables 8-bit pulse width modulator mode. if the matn bit is se t to 1, the ccfn flag for the modu le will be set each time an 8-bit comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occur every 256 pca clock cycles. the duty cycle for 8-bit pwm mode is given in equation 34.2 . important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 34.2. 8-bit pwm duty cycle using equation 34.2 , the largest duty cycle is 100% (pca0cph n = 0) , and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be g e nerated by clearing the ecomn bit to 0. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset duty cycle 256 pca0 cphn ? ?? 256 ------------------ ----------------- ---------------- =
si102x/3x 522 rev. 0.3 figure 34.8. pca 8-bit pwm mode diagram 34.3.5.2. 9/10/11-bit pulse width modulator mode the duty cycle of the pwm output signa l in 9/10/11-bit pwm mode should be varied by writing to an ?auto- reload? register, which is dual-mapped into the pc a0cphn and pca0cpln register locations. the data written to define the duty cycle should be right-just ified in the registers. the auto-reload registers are accessed (read or written) when the bit arsel in pca0pwm is set to 1. the capture/compare registers are accessed when arsel is set to 0. when the least-significant n bits of the pca0 coun ter ma tch the value in the associated module?s cap - ture/compare register (pca0cpn), the output on cexn is asserted high. when the counter overflows from the nth bit, cexn is asserted low (see figure 34.9 ). upon an overflow from the nth bit, the covf flag is set, and the value stored in the module?s auto-reload r egister is load ed into th e capture/compare register. the value of n is determined by the clsel bits in register pca0pwm. the 9, 10 or 11-bit pwm mode is selected by setting the ecomn and pwmn bits in the pca0cpmn regis - ter, and setting the clsel bits in register pca0pwm to the desired cycle length (other than 8-bits). if the ma tn bit is set to 1, the ccfn fl ag for the module will be set each ti me a comparator ma tch (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (f alling edge), which will occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) pca clock cycles . the duty cycle for 9/10/11-bit pwm mode is given in equation 34.3 , where n is the number of bits in the pwm cycle. important note about pca0cphn and pca0cpln registers : when writing a 16-bit value to the pca0cpn registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 34.3. 9, 10, and 11-bit pwm duty cycle a 0% duty cycle may be generated by clearing the ecomn bit to 0. 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l c l s e l 0 c l s e l 1 e c o v x0 0 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset covf c o v f duty cycle 2 n pca0 cpn ? ?? 2 n -------------------------------- ----------- - =
rev. 0.3 523 si102x/3x figure 34.9. pca 9, 10 and 11-bit pwm mode diagram 34.3.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. 16-bit pwm mode is independent of the other (8/9/10/11-bit) pwm modes. in this mode, the 16-bit capture/compare module defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the out - put on cexn is asserted high; when the 16-bit counte r over flows, cexn is asserted low. to output a vary - ing duty cycle, new value writes should be synchr onized with pc a cc fn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a vary - ing duty cycle, match interrupts should be enabled (eccfn = 1 and ma tn = 1) to help synchronize the capture/compar e register writes. if the matn bit is set to 1, the ccfn flag for the module will be set each time a 16-bit comparator match (rising edge) occurs. the cf flag in pca0cn can be used to detect the overflow (falling edge). the duty cycl e for 16-bit pwm mode is given by equation 34.4 . important note about capture/compare registers : when writing a 16-bit value to the pca0 cap - ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 34.4. 16-bit pwm duty cycle using equation 34.4 , the largest duty cycle is 100% (pca0cpn = 0), an d the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. n-bit comparator pca0h:l (capture/compare) pca0cph:ln (right-justified) (auto-reload) pca0cph:ln (right-justified) cexn crossbar port i/o enable overflow of n th bit pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l c l s e l 0 c l s e l 1 e c o v x enb enb 0 1 write to pca0cpln write to pca0cphn reset r/w when arsel = 1 r/w when arsel = 0 set ?n? bits: 01 = 9 bits 10 = 10 bits 11 = 11 bits c o v f duty cycle 65536 pca0 cpn ? ?? 65536 ------------------------------------ ---------------- - =
si102x/3x 524 rev. 0.3 figure 34.10. pca 16-bit pwm mode 34.4. watchdog timer mode a programmable watchdog timer (wdt) function is avai lable through the pca module 5. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph2) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, modu le 5 o perates as a watchdog timer (wdt). the mod - ule 5 high byte is compared to the pca counter high b y te; the module 5 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. the wdt will generate a reset shortly after code begins execution. to avoid this re set, the wdt should be explicitly disabled (and option - ally re-configured and re-enabled if it is used in the system). 34.4.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2 ? cps0) are frozen. ? pca idle control bit (cidl) is frozen. ? module 5 is forced into software timer mode. ? writes to the module 5 mode register (pca0cpm5) are disabled. while the wdt is enabled, writes to the cr bit will not c h ange the pca counter state; the counter will run until the wdt is disabled. the pca counter run control bit (cr) will re ad zero if the wdt is enabled but user software has not enabled th e pca counter. if a match occurs between pca0cph5 and pca0h while the wdt is enabled, a reset will be generated. to pr event a wdt reset, the wd t may be up dated with a write of any value to pca0cph5. up on a pca0cph5 write, pca0h plus the offset held in pca0cpl5 is loaded into pca0cph5. (see figure 34.11 .) pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset
rev. 0.3 525 si102x/3x figure 34.11. pca module 5 with watchdog timer enabled note that the 8-bit offset held in pca0cph5 is comp ared to the upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a reset. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the valu e of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 34.5 , where pca0l is the value of the pca0l register at the time of the update. equation 34.5. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflow s while there is a match between pca0cph5 and pca0h. software may force a wdt reset by writing a 1 to the ccf5 flag (pca0cn.5) while the wdt is enabled. 34.4.2. watchdog timer usage to configure the wdt, perform the following tasks: ? disable the wdt by writing a 0 to the wdte bit. ? select the desired pca clock source (with the cps2 ? cps0 bits). ? load pca0cpl5 with the desi red wdt update offset value. ? configure the pca idle mode (set cidl if the wd t should be suspended while the cpu is in idle mode). ? enable the wdt by setting the wdte bit to 1. ? reset the wdt timer by writing to pca0cph5. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog time r is en abled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any rese t. th e pca0 coun ter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl5 defaults to 0x00. using equation 34.5 , this results in a wdt timeout interval of 256 pca clock cycles, or 3072 system clock cycles. ta b l e 34.3 lists some example time - out intervals for typical system clocks. pca0h enable pca0l overflow reset pca0cpl5 8-bit adder pca0cph5 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph2 8-bit comparator offset 256 pca0 cpl5 u 256 pca0 l ? + =
si102x/3x 526 rev. 0.3 table 34.3. watchdog timer timeout intervals 1 system clock (hz) pca0cpl5 timeout interval (ms) 24,500,000 255 32.1 24,500,000 128 16.2 24,500,000 32 4.1 3,062,500 2 255 257 3,062,500 2 128 129.5 3,062,500 2 32 33.1 32,000 255 24576 32,000 128 12384 32,000 32 3168 notes: 1. assumes sysclk/12 as the pca clock source, and a pca0l value of 0x00 at the update time. 2. internal sysclk reset frequency = internal oscillator divided by 8.
rev. 0.3 527 si102x/3x 34.5. register d escriptions for pca0 following are detailed descriptions of the special func tion registers related to the operation of the pca. sfr page = all pages; sfr ad dr es s = 0xd8; bit-addressable sfr definition 34.1. pca0cn: pca control bit 7 6 5 4 3 2 1 0 name cf cr ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 cf pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service r outine. this bit is not automatically cleared by hardware and must be cleared by software. 6 cr pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. 5:0 ccf[5:0] pca module n capture/compare flag. these bits are set by hardware when a matc h or capture occurs in the associated pca module n. when the ccfn interrupt is en abled, setting this bi t causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software.
si102x/3x 528 rev. 0.3 sfr page = 0x0; sfr address = 0xd9 sfr definition 34.2. pca0md: pca mode bit 7 6 5 4 3 2 1 0 name cidl wdte wdlck cps2 cps1 cps0 ecf type r/w r/w r/w r r/w r/w r/w r/w reset 0 1 0 0 0 0 0 0 bit name function 7 cidl pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally w hile the system co ntroller is in idle mode. 1: pca operation is suspended while th e sys tem controller is in idle mode. 6 wdte watchdog timer enable. if this bit is set, pca module 5 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 5 enabled as watchdog timer. 5 wdlck watchdog timer lock. this bit locks/unlocks the watchdog timer e nable. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. 4 unused read = 0b, write = don't care. 3:1 cps[2:0] pca counter/timer pulse select. these bits select the timebase source for the pca counter 000: system clock divided by 12 001: system clock divided by 4 010: timer 0 overflow 011: high-to-low transitions on eci (max rate = syste m clock divided by 4) 100: system clock 101: external clock divided by 8 (synchronized with the system clock) 110: smartclock divided by 8 (synchronized with the system clock) 111: reserved 0 ecf pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow in terrupt request w hen cf (pca0cn.7) is set. note: when the wdte bit is set to 1, the other bits in t he pca0md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled.
rev. 0.3 529 si102x/3x sfr page = 0x0; sfr address = 0xdf sfr definition 34.3. pca0pwm: pca pwm configuration bit 7 6 5 4 3 2 1 0 name arsel ecov covf clsel[1:0] type r/w r/w r/w r r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7 arsel auto-reload register select. this bit selects whether to read and write the normal pca capture/compare registers (pca0cpn), or the auto-reload registers at the same sfr addresses. this function is used to define the reload value for 9, 10, and 11-bit pwm modes. in all other modes, the auto-reload registers have no function. 0: read/write capture/compare registers at pca0cphn and pca0cpln. 1: read/write auto-reload regi sters at pca0cphn and pca0cpln. 6 ecov cycle overflow interrupt enable. this bit sets the masking of the cycle overflow flag (covf) interrupt. 0: covf will not gene rate pca interrupt s. 1: a pca interrupt will be ge nerated w h en covf is set. 5 covf cycle overflow flag. this bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main pca counter (pca0). the specific bit used for this flag depends on the setting of the cycle length select bits. the bit can be set by hardware or software, but must be cleared by soft - ware. 0: no overflow has occurred since th e last time this bit was cleared. 1: an overflow has occurred since t he last time this bit was cleared. 4:2 unused read = 000b; write = don?t care. 1:0 clsel[1:0] cycle length select. when 16-bit pwm mode is not selected, th ese bits select the length of the pwm cycle, between 8, 9, 10, or 11 bits. this affects all channels configured for pwm which are not using 16-bit pwm mode. these bits are ignored for individual channels config - ured to16-bit pwm mode. 00: 8 bits. 01: 9 bits. 10: 10 bits. 11: 11 bits.
si102x/3x 530 rev. 0.3 sfr address, page: pca0cpm0 = 0xda , 0x0; pca0cpm1 = 0xdb , 0x0; pca0cpm2 = 0xdc, 0x0 ? pca0cpm3 = 0xdd , 0x0; pca0cpm4 = 0xde , 0x0; pca0cpm5 = 0xce, 0x0 sfr definition 34.4. pca0cpmn: pca capture/compare mode bit 7 6 5 4 3 2 1 0 name pwm16n ecomn cappn capnn matn togn pwmn eccfn type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 pwm16n 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6 ecomn comparator function enable. this bit enables the comparator function for pca module n when set to 1. 5 cappn capture positive function enable. this bit enables the positive edge capture for pca module n when set to 1. 4 capnn capture negative function enable. this bit enables the negative edge capture for pca module n when set to 1. 3 matn match function enable. this bit enables the match function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare regist er cause the ccfn bit in pca0md register to be set to logic 1. 2 togn toggle function enable. this bit enables the toggle function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare register cause the logic level on the cexn pin to toggle . if the pwmn bit is also set to logic 1, the module oper - ates in frequency output mode. 1 pwmn pulse width modulation mode enable. this bit enables the pwm function for pca module n when set to 1. when enabled, a pulse width modulated signal is output on the cexn pin. 8 to 11-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm1 6n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0 eccfn capture/compare flag interrupt enable. this bit sets the masking of the ca pture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. note: when the wdte bit is set to 1, the pca0cpm5 register cannot be modified, and module 5 acts as the watchdog timer. to change the contents of the pca0cpm5 register or the function of module 5, the watchdog timer must be disabled.
rev. 0.3 531 si102x/3x sfr page = 0x0; sfr address = 0xf9 sfr page = 0x0; sfr address = 0xfa sfr definition 34.5. pca0l: pca counter/timer low byte bit 7 6 5 4 3 2 1 0 name pca0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0[7:0] pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. note: when the wdte bit is set to 1, the pca0l register canno t be modified by software. to change the contents of the pca0l register, the watchdog timer must first be disabled. sfr definition 34.6. pca0h: pca counter/timer high byte bit 7 6 5 4 3 2 1 0 name pca0[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0[15:8] pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. reads of this register will re ad the contents of a ?snapshot ? register, whose contents are updated only when the cont ents of pca0l are read (see section 34.1 ). note: when the wdte bit is set to 1, the pca0h register cannot be modified by software. to change the contents of the pca0h register, the watchdog timer must first be disabled.
si102x/3x 532 rev. 0.3 sfr addresses: pca0cpl0 = 0xfb , pca0cpl1 = 0xe9 , pca0cpl2 = 0xeb, ? pca0cpl3 = 0xed , pca0cpl4 = 0xfd , pca0cpl5 = 0xd2 sfr pages: pca0cpl0 = 0x0 , pca0cpl1 = 0x0 , pca0cpl2 = 0x0, ? pca0cpl3 = 0x0 , pca0cpl4 = 0x0 , pca0cpl5 = 0x0 sfr addresses: pca0cph0 = 0xfc , pca0cph1 = 0xea , pca0cph2 = 0xec, ? pca0cph3 = 0xee , pca0cph4 = 0xfe , pca0cph5 = 0xd3 sfr pages: pca0cph0 = 0x0 , pca0cph1 = 0x0 , pca0cph2 = 0x0, ? pca0cph3 = 0x0 , pca0cph4 = 0x0 , pca0cph5 = 0x0 sfr definition 34.7. pca0cpln: pca capt ure module low byte bit 7 6 5 4 3 2 1 0 name pca0cpn[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0cpn[7:0] pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. this register address also allows acce ss to the lo w byte of the corresponding pca channel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will clear the module?s ecomn bit to a 0. sfr definition 34.8. pca0cphn: pca capture module high byte bit 7 6 5 4 3 2 1 0 name pca0cpn[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0cpn[15:8] pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. this register address also allows access to the high byte of the corresponding pca ch ann el?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will set the module?s ecomn bit to a 1.
rev. 0.3 533 si102x/3x 35. c2 interface si102x/3x devices include an on-chip silicon labs 2-wire (c 2) debug interface to allow flash program - ming and in-system debugging with the production part ins t alled in the end applic ation. the c2 interface uses a clock signal (c2ck) and a bi-directional c2 data signal (c2d) to transfer information between the device and a host system. see the c2 interface specification for details on the c2 protocol. 35.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming through the c2 inter - face. all c2 registers are accessed through the c2 inte r f ace as described in the c2 interface specification. c2 register definition 35.1. c2add: c2 address bit 7 6 5 4 3 2 1 0 name c2add[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 c2add[7:0] c2 address. the c2add register is accessed via the c2 interface to select the target data register for c2 data read and data write commands. address description 0x00 selects the device id register for data read instructions 0x01 selects the revision id register for dat a read instructions 0x02 selects the c2 flash programming control register for data read/w rite instruc tions 0xb4 selects the c2 flash programm ing dat a register for data read/write instructions
si102x/3x 534 rev. 0.3 c2 address: 0x00 c2 address: 0x01 c2 register definition 35.2. deviceid: c2 device id bit 7 6 5 4 3 2 1 0 name deviceid[7:0] type r/w reset 0 0 0 1 0 1 0 0 bit name function 7:0 deviceid[7:0] device id. this read-only register returns the 8-bit device id: 0x2a (si102x/3x). c2 register definition 35.3. revid: c2 revision id bit 7 6 5 4 3 2 1 0 name revid[7:0] type r/w reset varies varies varies varies varies varies varies varies bit name function 7:0 revid[7:0] revision id. this read-only register returns the 8-bit revision id. for example: 0x00 = revision a.
rev. 0.3 535 si102x/3x c2 address: 0x02 c2 address: 0xb4 c2 register definition 35.4. fpctl: c2 flash programming control bit 7 6 5 4 3 2 1 0 name fpctl[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 fpctl[7:0] flash programming control register. this register is used to enable flash programming via the c2 interface. to enable c2 flash programming, the following codes must be written in order: 0x02, 0x01. note that once c2 flash programming is ena bled, a system reset must be issued to resume normal operation. c2 register definition 35.5. fpdat: c2 flash programming data bit 7 6 5 4 3 2 1 0 name fpdat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 fpdat[7:0] c2 flash programming data register. this register is used to pass flash commands, addresses, and data during c2 flash accesses. valid commands are listed below. code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase
si102x/3x 536 rev. 0.3 35.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming may be performed. this is possible because c2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface ca n safely ?borrow? the c2ck ( rst ) and c2d pins. in most applications, external resistors are required to isolate c2 interface traffic from the user application. a typical isolation configuration is shown in figure 35.1 . figure 35.1. typical c2 pin sharing the configuration in figure 35.1 assumes the following: 1. the user input (b) cannot change stat e while the target device is halted. 2. the rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d c2ck rst (a) input (b) output (c) c2 interface master c8051fxxx
rev. 0.3 537 si102x/3x n otes :
si102x/3x 538 rev. 0.3 c ontact i nformation silicon laboratories inc. 400 west cesar chavez ? austin, tx 78701 please visit the silicon labs technical support web page: ? https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ? and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibility for any consequen ces resulting from the use of information included herein. additi onally, silicon laborator ies assumes no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories reserves the right to make change s without further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liabi lity arising out of the application or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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